ST AN1126 Application note
AN1126
V
®
APPLICATION NOTE
CURRENT SHARING OF THE L4973
IN A MULTIPHASE APPLICATION
by Domenico Arrigo & Giuseppe Gattavari
INTRODUCTION
The L4973 family is a 3.5A monolithic s tep-down dc-dc converter, available in POWERDIP18( 12+3+3)
and SO20L (12+4+4) plastic packages. The operating input supply voltage range is f rom 8V to 55V, and
the output ranges from 3.3V (L4973D3.3) and 5.1V(L4973D5.1) to 40V. Other regulated outputs below
3.3V are also possible (See Application Note AN938).
Using two L4973D is possible to deliver up to 7A with a good sharing between the two sections or a re-
dundant 3.5A. The two devices work at a switching frequency of 200kHz. At Vcc = 24V, V o = 5.1V at 7A
the efficiency is 87%. At 3.5A output, the efficiency is 90%.
Electrical Specifications
Input Voltage range 8V-30V
Output Voltage 5.1V ±3% (Line, Load and Temperature)
Output Voltage Ripple 47mV (0.92%/Vo)
Output Current range 0 to 7A
Max Output Ripple current 15%
Min Iomax Current limit 8A
Switching frequency 200kHz
Current Sharing Operating Principle
The current sharing configuration, shown in fig. 1, is based upon two L497x devices U1 and U2. Any device in the L497x family can be used for this purpose.
The U1 regulator acts as a master which regulates the output voltage.
The second section U2 works as a current follower. Its task is to deliver an output current equal to the
Figure 1. Current Sharing Operating Princi ple
Rint
I -FB
Rs
Vout
I +
Rs
Cout
Vcc
U1
COMP
cc
Vcc
COMP
L497x
FB
U2
L497x
GND
OUT
Cint
OP-AMP
OUT
GND
L
+
L
May 1999
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AN1126 APPLICATION NOTE
current delivered from the first section. An op-amp compares the voltage drop through Rs which is proportional to the cur rent deliv er ed from the U2 section with the voltage drop across Rs proportional to the
current delivered from the U1 section. T he Cin and Rin components introduce a pole and a zero in the
current loop which allows integration of the error signal. The current loop regulates I
result the output current delivered to the load is Iout = 2I- = 2I+ for every load condition.
Current Sharing Accuracy
The accuracy of the current sharing between the two sections depends on the op-amp offset voltage,
Voff, and the value of Rs and its ac curacy . The of fset voltage introduce an error in the sensing voltage ,
Vs=Rs Iout/2 . The relative percentage current error due to the offset is given by :
e%= (∆ I/I) ⋅ 100 = (Voffset ⋅ 100) / (Rs ⋅ Iout)
This error is minimum at maximum load. The larger the value of Rs, the smaller the error. Rs must be
chosen as a compromise between error minimization and system efficiency.
For example with Iout = 7A choosing Rs = 25mΩ ,considering a maximum offset voltage of 3mV
(LM358A), the maximum relative percentage error is 1.7% (120mA @ Iout = 7A).
The total error is given by the sum of this error plus the error due to the sensing resistor ( which corresponds to its accuracy of 1% ). So the maximum error is 2.7% (190mA @Iout = 7A)
Layout Hints
The PCB layout requires some care. The power paths of the two sections must be as short and symmetrical as possible. The current sensing wires must be parallel and s hort to avoid induced noises. The
sensing resistor must be non induct ive. The ground pins of the two devices must be at the same voltage
and connected to the output ground point.
Figure 2. Layout hints.
+
equal to I- . As a
to the
current
FB
I -FB
Rs
to the
current
FB
Vout
Cout
GND
I +
Rs
Vcc
GND
COMP
Vcc
Vcc
COMP
U1
L497x
U2
L497x
L
OUT
GND
GND
L
OUT
Syncronization or Multiphase
In a current sharing application the two sections c an be synchronized. This permits a reduction of noise
induced from one section to another. In this case a single RC network can be used for both the oscillators and the two SYNC pins are connected.
In many application, instead of synchronizing the two oscillator, it is useful to introduce a delay between
the two PWM signals in order to achieve a multiphase application. The phase shift between the two
PWM signals can be easily achieved by two methods :
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AN1126 APPLICATION NOTE
Case 1)
Programmable Phase Delay.
Fig. 3 shows how to program a phase delay with a monostable multivibrator whos e on time is equal to
the desired phase delay.
Case 2)
Fixed Phase Delay.
Figure 3 shows a method of setting a delay time for the 2nd PWM section to be slightly larger than the
ON-time of the 1st PWM section.
Figure 3. Case 1) Programmable Phase Delay.
Vcc
R1
OSC
GND
U1
L4973D3.3
SYNC
Vcc
1B
M74HC123
1A
GND
Vref=5.1C2
CLR
_
1Q
Vcc
OSC
U2
L4973D3.3
SYNC
U1
GND
U2
PWM OUTPUTS
0
α
0
Figure 4. Case 2) Programmable Phase Delay.
L
18V
*
L
Vcc
necessary if Vcc>18V
*
OUT1
OUT2
Vcc
R1
OSC
C2
Vcc
OSC
U1
L4973D3.3
Vref=5.1
SYNC
U2
L4973D3.3
t
PWM OUTPUTS
Rs
Vout
Cout
Rs
U1
0
U2
0
t
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AN1126 APPLICATION NOTE
Multiphase Benefits
The main benefits are :
Minimization of the RMS current through the input capacitor therefore increasing of the efficiency and
reducing of the capacitor cost and size.
Minimization of ripple current through the output capacitor and ground path.
Fast load transient response.
Improved reliability /MTBF.
RMS current through the input capacitor are equivalent in Case 1) and Case 2). Even though the circuitry of Case 2) is simplifier than Case 1), Case 1) provides the opportunity to optimize this ripple current.
Minimization of the RMS Current Through the Input Capacitor.
In Case 1) , Figure 3 shows the RMS current through the input capacitor, referred to the output current
(Iout), for various phase delays, α , of the two PWM sections. This assumes a duty cycle of 0.5 and a
ripple current through the coil of 0.1⋅ Iout.
For α equal to a half period (180 degrees of phase delay) the RMS current is approximately zero. If the
two PWM signals are synchronized the RMS value is Irms = Iout/2. For example if Vout = 5V and
Iout = 7A the Output Power is 35W. If the Input capacitor has an ESR of 100mOhm the phase delay
allows a savings of 1.23W which corresponds to the 3.5% of the power delivered to the load.
Figure 5. RMS current through the input capacitor for a different phase delay, α , with a duty
cycle of 0.5.
[ A ]
α=120
°
Iout/2
0
- Iout/2
α=40
0
Assuming the same duty cycle for the two sections, the RMS Current through the input filter for different
duty cycle, considering a phase delay of the second PWM signal equal to the Ton of the first section (
Case 2) ), is given approximately (the output c urrent ripple can be negleted for this calculation) by the
following formula:
2
− (Iout ⋅
I
RMS
(α)
Iout
√
=
⋅
√2 ⋅ δ
2
Iout
√
where δ = duty cycle
2
(3
⋅
2
⋅ δ −1)
√
⋅
α=180
°
δ
2
− (iout ⋅
2
)
°
if
δ)
α=90
°
α=0
time
0.5
δ ≤
2
if δ > 0.5
°
Multiphase (1)
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AN1126 APPLICATION NOTE
Iout is the total output current equal to the sum of the individual output currents delivered from the two
sections.
Figure 6. Input current of the two sections for different dut y cycle.
PWM1
PWM2
PWM1
PWM2
1
0
0
t
δ=0.5
1
0
0
t
δ<0.5
1
PWM1
PWM2
0
0
t
δ>0.5
If the PWM signals are synchronized without any delay, the RMS current through the input filter as a
function of duty cycle is :
Irmssync
(Iout
(δ) =
√
⋅ √δ )
2
− (Iout ⋅
2
synchronized (2)
δ)
Figure 7. RMS current through the input capacitor with synchronizat ion and with multiphase.
Iout
[ A ]
3Iout/4
δ
Irms ( )
Irmssync ( )
δ
Iout/2
Irms
Iout/4
Irmssync
0
0 0.1 0.2 0.3 0 .4 0.5 0.6 0.7 0.8 0.9 1
δ
Figure 7 shows Equations (1) and (2) versus the duty cycle.
The maximum RMS current with synchronized PWMs is 1/2 of the total output current and it is obtained
for δ = 0.5.
In contrast, considering the multiphase PWM,
RMS value is 1/4 of the total output current.
the RMS value is 0 with δ = 0.5
So the maximum RMS current with multiphased PWMs
and the max value of the
is a half of that syncronized PWMs.
For every duty cycle condition the RMS current with multiphase application is lower than the case with
synchronized PWMs and it is quite regular for different duty cycles.
It allows to optimize the input capacitor for the real working condition. In the synchronized case the input
capacitor has to be dimensioned f or the worst case of δ = 0.5 that can be far from the real working conditions.
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