ST AN1089 Application note

AN1089

®

APPLICATION NOTE

CONTROL LOOP MOD ELING OF L6561-BASED TM PFC

by Claudio Adragna

This paper provides a model and a tool for evaluating and improving the control loop characteristics
of L6561-based PFC preregulators in boost topology and operated in Transition Mode (TM).

Such a subject is now becoming topical since TM PFC preregulators are more and more used in sys­tems other than electronic lamp ballast where the input voltage range is limited and the load current
is almost constant.

The ability to operate under large variations of bot h input voltage and load current, as well as the use
of TM PFC systems as preregulators for switching converters, requires a more accurate design of the
control loop. The goal will be not only to ensure a narrow bandwidth in or der to achieve a high Power
Factor, but also to have enough phase margin so as to make sure the system is stable over a large
range of operating conditions.

INTRODUCTION

PFC preregulators based on the boost topology working in Transition Mode (TM, see fig. 1) have been
widespread in electronic lamp ballast systems. This kind of equipm ent almost always works under a sin­gle mains supply (110 or 220 VAC, with some tolerance) and the use of a PFC preregulator is mainly
aimed at optimising the downstream half-bridge lamp driver and improving their inherent extremely poor
PF.

The PFC preregulator sees the downstream stage as a constant load, so it is requested to work under a
limited range of operat ing conditions. From the control loop standpoint, this means that the frequency
compensation of the error amplifier can be very simple, t ypically just a feedback capacitor. Its capaci­tance will be high enough to ensure the crossover frequency of the open loop gain is low, so as to
achieve a high PF (see Ref. [1]).

Figure 1. Typical L6561-based TM PFC preregulator

Vcc

+

-

Vac

March 2000

R9

R10

5

8

3

21

L6561

Compensation

Network

6

R7

Vo

7

4

Rs

R8

Co

1/12

AN1089 APPLICATION NOTE

Things get more complicated when an electronic ballast can supply two lamps and is required t o work
even if one lamp is not used or is exhausted, so that it is expected to work at half load as well.

The L6561, thanks to its highly linear , wide dynamics multiplier, extends the use of TM PFC boost pre­regulators to applications that experience a wide range of operating condit ions, both in terms of input
voltage variations and load change. High power (60 to70 W) AC-DC adapters for portable equipment
and computer monitor SMPS’ are the most noticeable examples.

This, however, calls for a more accurate design of the control loop than the one illustrated in Ref.[1]. The
control goal will no longer be to achieve only a low crossover frequency but also an adequate phase
margin. Besides ensuring stability over a large variety of operating conditions, this is necessary to pre­vent dangerous oscillations of the output voltage as a result of load changes.

PFC Boost Preregulator Control Loop

To the aim of finding a compensation network able to achieve the above mentioned control goal, it is
necessary to get an insight into the control loop of such systems. This can be synthesised as shown in
the block diagram of fig. 2.

Figure 2. Control loop of a PFC Preregulator: Block Diagram

Virms

ZCD

G3

+

-

ERROR AMPLIFIER

G1(s)

Vref VoV

COMP

MULTIPLIER

G2

FEEDBACK

H

V

cspk

PWM MODULATOR POWER ST AG E

+

-

I

Lpk

G4(s)

Figure 3. Control loop of a PFC Preregulator: electrical circuit and main quantities

Vi

R9

R10

KP· Vi

L6561

L

V

cs

MULT CS ZCD

V

cs

MULTIPLIER

4

3

G2

Q

Rs

G3

5

STARTER

ZCD

-

PWM

+

COMPARATOR

V

G4(s)

D

Co

COMP

COMP

H

DRIVER

Q

S

VREF

R

(2.5V)

+

E/A

-

2

G1(s)

E/A

COMPENSATION

NETWORK

Vo

R7

R8

GD

7

INV

1

REF

V

2/12

AN1089 APPLICATION NOTE

Fig. 3 illustrates how the various blocks of fig. 2 relate with the electrical circuit, both external and inside
the L6561. For details on the internal circuit and its operation please refer to Ref. [1].

The loop gain of PFC preregulators must have a very low crossover frequency (fc) so as to maintain

COMP

(Error Amplifier output) fairly constant over a given line cycle and ensure a high PF.

V
As a rule of thumb, fc should not exceed 20-25 Hz at maximum mains voltage.
This allows to assume that the c ontrol action t akes place on the peak amplitude ( or, which is the same,

the RMS value) of the various quantities inside the loop.
The first step is to determine the transfer function of the power stage, G4(s), defined as:

dV

dV

G4(s) =

dI

Lpk

o

=

dI

dI

o

o

⋅

dI

o

Lpk

Figure 4. Power stage model,G4(s)

Io

=

I

o

Co RoRe

_________________

1

⋅

2

(1 − D) ⋅

I

Lpk

⋅ sin

Figure 5. Boost PFC currents

I

Lpk

Switch current

Vo

_________________________
√2 ⋅

1

⋅

=

θ

2

Inductor current

peak envelope

Diode current

Low frequency

Diode current

where Vo is the DC output voltage, Io the DC output
current and I

Lpk

is the peak value of the inductor cur-

rent.
Under the above assumption, the power stage can

be modeled as illustrated in fig. 4: a controlled cur­rent source (with a shunt resistor Re) t hat drives the
output bulk capacitor Co and the load resistance Ro
(= Vo / Io). The zero due to the ESR associated with
Co is far beyond the crossover frequency thus it is
neglected.

The current source can be characterised with the fol­lowing considerations: the low frequency component
of the boost diode current is found by averaging the
discharge portion of the inductor current (the white
triangles of fig. 5) over a given switching cycle.

The low frequency current, averaged over a mains
half-cycle yields the DC output current Io:

V

irms

⋅ sin

V

o

θ ⋅

I

⋅ sin

Lpk

2

V

⋅

irms

⋅ I

Lpk

V

o

√

θ

=

4

where D is the switch duty cycle, θ is the in­stantaneous phase angle of the mains volt-

irms

age and V

its effective (RMS) value.
The AC model illustrated in fig. 4 can be
found by calculating the total differential of
the above expression of Io. A few algebraic
manipulations would show that the shunt re­sistor Re always equals the DC load resis­tance Ro, thus it changes depending on the
power delivered by the system. Now it is
necessary to consider two separate cases.

If the load is purely r esistive (or equiv alent to
a resistor, like in the case of a lamp ballast
circuit), the AC load resistance equals Ro.
The parallel of this resistance with Re, com­bined with the output bulk capacitor, gives

Io

origin to a pole located at:

SWITCH

ON

OFF

2

=

ω

p

R

⋅ C

o

o

which is usually in the range of 1 to 5 Hz.

3/12

AN1089 APPLICATION NOTE

In case the PFC preregulator provides a DC bus supplying a downstream switching converter, the load
should be regarded as a "constant power" load rather than a resistor. In fact, as long as a switching con­verter is in regulation, the power it demands of the source is practically independent of the input voltage
(converter’s efficiency changes very little).

In this case, the AC load resistance is equal to -Ro (if the DC bus decreases the current demanded of
the PFC increases, whence the negative sign). As a result, the parallel combination with Re tends to in­finity and the two resistances cancel. The current source drives only the output capacitor and the pole lo­cation tends to zero. In the end, G4(s) will be given by:

2



√

V

irms

⋅

⋅

V

o

V

irms

⋅

⋅

V

o

G4(s) =



8





2

√



4



The gain of the PWM modulator, G3, which includes the current loop, is simply:

R

o

R

1 + s ⋅

1

.

(constant power load

s ⋅C

o

(resistive load)

⋅ C

o

o

2

)

Figure 6. Plot of KM vs. E/A output

KM

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

2.5 3 3.5 4 4.5 5 5.5

VCOMP

where Rs is the sense resistor connected be­tween the source of the external MOSFET and
ground (across which the L6561 reads the induc­tor current through pin 3).

To calculate the transfer function G2 of the multi­plier block, one can consider that a variation

COMP

V

∆

, due to a line and/or load change, modi­fies the peak amplitude Vcspk of the rectified
sinusoid at the output of the multiplier.
Therefore:

dV

G2 =

dV

G3 =

cspk

COMP

dI

Lpk

=

dV

cspk

R

= KM ⋅ KP ⋅

1

s

V

√2⋅

irms

where KM is the gain of the multiplier and KP the partition ratio of the resistor divider that feeds a portion
of the input voltage into pin 3.

The electrical characteristics of the L6561 specify K
but actually KM decreases for low values of V

COMP

along with the tolerance limits. Since V

V

M

ation of K

partly compensates for t he increase of G2 with V

COMP

COMP

M

= 0.6 ±25% (@V

. In fig. 6 t he typical value of KM is plotted against

gets lower when the mains voltage is high, this vari-

irms

COMP

= 4V, including temperature)

, thus providing a mild voltage feedfor­ward effect.
If one wants to take this non-linearity into account, he or she should linearise the large-signal multiplier
gain in the neighborhood of the quiescent point of the error amplifier, so as to get the small-signal gain
(km). Please refer to [1] and the Appendix for the relevant calculation technique.
Ultimately, the control-to-output transfer function will be:

⋅ V

P

V

O

⋅ V

P

Rs ⋅ V

2

O

irms

2

irms

⋅

⋅

R

o

R

s

1

s ⋅ C

⋅

1 + s ⋅

O

G(s) =

dV

dV

O

= G2 ⋅ G3 ⋅ G4(s) =

COMP



km ⋅ K

1

⋅



4





km ⋅ K

1

⋅



2



where the small-signal multiplier gain km could be assumed equal to K

4/12

1
R

(resistive load

⋅ C

O

O

2

(constant power load

for simplicity.

M

)

)