ST AN1089 Application note

AN1089

®	APPLICATION NOTE

CONTROL LOOP MODELING OF L6561-BASED TM PFC

by Claudio Adragna

This paper provides a model and a tool for evaluating and improving the control loop characteristics of L6561-based PFC preregulators in boost topology and operated in Transition Mode (TM).

Such a subject is now becoming topical since TM PFC preregulators are more and more used in systems other than electronic lamp ballast where the input voltage range is limited and the load current is almost constant.

The ability to operate under large variations of both input voltage and load current, as well as the use of TM PFC systems as preregulators for switching converters, requires a more accurate design of the control loop. The goal will be not only to ensure a narrow bandwidth in order to achieve a high Power Factor, but also to have enough phase margin so as to make sure the system is stable over a large range of operating conditions.

INTRODUCTION

PFC preregulators based on the boost topology working in Transition Mode (TM, see fig. 1) have been widespread in electronic lamp ballast systems. This kind of equipment almost always works under a single mains supply (110 or 220 VAC, with some tolerance) and the use of a PFC preregulator is mainly aimed at optimising the downstream half-bridge lamp driver and improving their inherent extremely poor PF.

The PFC preregulator sees the downstream stage as a constant load, so it is requested to work under a limited range of operating conditions. From the control loop standpoint, this means that the frequency compensation of the error amplifier can be very simple, typically just a feedback capacitor. Its capacitance will be high enough to ensure the crossover frequency of the open loop gain is low, so as to achieve a high PF (see Ref. [1]).

Figure 1. Typical L6561-based TM PFC preregulator

				R7
	Vcc
		Compensation
+		Network
+
	R9	2	1	Vo
	5	2	1	Vo
	8		7	Co
-		L6561	7	Co
-		L6561
Vac	3	6	4
			4

	R10
			Rs	R8
March 2000				1/12

AN1089 APPLICATION NOTE

Things get more complicated when an electronic ballast can supply two lamps and is required to work even if one lamp is not used or is exhausted, so that it is expected to work at half load as well.

The L6561, thanks to its highly linear, wide dynamics multiplier, extends the use of TM PFC boost preregulators to applications that experience a wide range of operating conditions, both in terms of input voltage variations and load change. High power (60 to70 W) AC-DC adapters for portable equipment and computer monitor SMPS’ are the most noticeable examples.

This, however, calls for a more accurate design of the control loop than the one illustrated in Ref.[1]. The control goal will no longer be to achieve only a low crossover frequency but also an adequate phase margin. Besides ensuring stability over a large variety of operating conditions, this is necessary to prevent dangerous oscillations of the output voltage as a result of load changes.

PFC Boost Preregulator Control Loop

To the aim of finding a compensation network able to achieve the above mentioned control goal, it is necessary to get an insight into the control loop of such systems. This can be synthesised as shown in the block diagram of fig. 2.

Figure 2. Control loop of a PFC Preregulator: Block Diagram

					Virms
					ZCD
					G3
Vref	ERROR AMPLIFIER	VCOMP	MULTIPLIER	Vcspk	PWM MODULATOR	ILpk	POWER STAGE	Vo
	+				+
	G1(s)		G2		-		G4(s)
	-				-
			FEEDBACK
			H

Figure 3. Control loop of a PFC Preregulator: electrical circuit and main quantities

		L		G4(s)			H
Vi			Q					Vo
			Q	D
R9					Co		R7
		Vcs						VREF
		Vcs
R10			Rs				R8
			G3
KP · Vi	MULT	CS	ZCD
	3	4	5	STARTER		DRIVER
				STARTER		DRIVER
			ZCD			Q		GD
					S	Q	7
			-				7
			-				VREF
	Vcs			PWM	R		VREF
	Vcs				R		(2.5V)
							(2.5V)
			+ COMPARATOR
L6561		MULTIPLIER				E/A	+	INV
L6561		MULTIPLIER		VCOMP		E/A	1	INV
				VCOMP			-
					2		-
					2
		G2		COMP		G1(s)
		G2				G1(s)
							E/A
					COMPENSATION
						NETWORK

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AN1089 APPLICATION NOTE

Fig. 3 illustrates how the various blocks of fig. 2 relate with the electrical circuit, both external and inside the L6561. For details on the internal circuit and its operation please refer to Ref. [1].

The loop gain of PFC preregulators must have a very low crossover frequency (fc) so as to maintain VCOMP (Error Amplifier output) fairly constant over a given line cycle and ensure a high PF.

As a rule of thumb, fc should not exceed 20-25 Hz at maximum mains voltage.

This allows to assume that the control action takes place on the peak amplitude (or, which is the same, the RMS value) of the various quantities inside the loop.

The first step is to determine the transfer function of the power stage, G4(s), defined as:

( ) = dVo = dVo × dIo G4 s

dILpk dIo dILpk

where Vo is the DC output voltage, Io the DC output Figure 4. Power stage model,G4(s) current and ILpk is the peak value of the inductor cur-

rent.

Under the above assumption, the power stage can

be modeled as illustrated in fig. 4: a controlled cur-

rent

source (with a shunt resistor Re) that drives the

output bulk capacitor Co and the load resistance Ro

(= Vo / Io). The zero due to the ESR associated with

Co is far beyond the crossover frequency thus it is

neglected.

The current source can be characterised with the fol-

lowing considerations: the low frequency component

of the boost diode current is found by averaging the

discharge portion of the inductor current (the white

triangles of fig. 5) over a given switching cycle.

The low frequency current, averaged over a mains

half-cycle yields the DC output current Io:

_________________

_________________________

``Ö2

× Virms

× sin q × ILpk × sin q

`Ö 2

Virms × ILpk

Io =

× (1 - D) × ILpk × sin q

Figure 5. Boost PFC currents

		Inductor current
		peak envelope
		ILpk
	Switch current	Diode current
		Low frequency
		Diode current
		Io
	SWITCH	ON
	SWITCH	OFF
		OFF

where D is the switch duty cycle, q is the instantaneous phase angle of the mains voltage and Virms its effective (RMS) value.

The AC model illustrated in fig. 4 can be found by calculating the total differential of the above expression of Io. A few algebraic manipulations would show that the shunt resistor Re always equals the DC load resistance Ro, thus it changes depending on the power delivered by the system. Now it is necessary to consider two separate cases.

If the load is purely resistive (or equivalent to a resistor, like in the case of a lamp ballast circuit), the AC load resistance equals Ro. The parallel of this resistance with Re, combined with the output bulk capacitor, gives origin to a pole located at:

wp = Ro 2× Co

which is usually in the range of 1 to 5 Hz.

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AN1089 APPLICATION NOTE

In case the PFC preregulator provides a DC bus supplying a downstream switching converter, the load should be regarded as a "constant power" load rather than a resistor. In fact, as long as a switching converter is in regulation, the power it demands of the source is practically independent of the input voltage (converter’s efficiency changes very little).

In this case, the AC load resistance is equal to -Ro (if the DC bus decreases the current demanded of the PFC increases, whence the negative sign). As a result, the parallel combination with Re tends to infinity and the two resistances cancel. The current source drives only the output capacitor and the pole location tends to zero. In the end, G4(s) will be given by:

ì``Ö2

Virms

(resistive load)

Ro ×

1 + s ×

G4(s) = í

``Ö2

Virms

1 .

(constant power load)

s ×Co

The gain of the PWM modulator, G3, which includes the current loop, is simply:

Figure 6. Plot of KM vs. E/A output	G3 =	dILpk	=	1

KM		dVcspk		Rs

0.9	where Rs is the sense resistor connected be-

0.8
	tween the source of the external MOSFET and

0.7	ground (across which the L6561 reads the induc-

0.6	tor current through pin 3).
	To calculate the transfer function G2 of the multi-
0.5
	plier block, one can consider that a variation

0.4	DVCOMP, due to a line and/or load change, modi-

0.3	fies the peak amplitude Vcspk of the rectified
	sinusoid at the output of the multiplier.

0.2	Therefore:

0.1								dVcspk
	3	3.5	4	4.5	5	5.5
2.5							G2 =		= KM × KP × ``Ö2 × Virms
			VCOMP					dVCOMP

where KM is the gain of the multiplier and KP the partition ratio of the resistor divider that feeds a portion of the input voltage into pin 3.

The electrical characteristics of the L6561 specify KM = 0.6 ±25% (@VCOMP = 4V, including temperature) but actually KM decreases for low values of VCOMP. In fig. 6 the typical value of KM is plotted against VCOMP along with the tolerance limits. Since VCOMP gets lower when the mains voltage is high, this variation of KM partly compensates for the increase of G2 with Virms, thus providing a mild voltage feedforward effect.

If one wants to take this non-linearity into account, he or she should linearise the large-signal multiplier gain in the neighborhood of the quiescent point of the error amplifier, so as to get the small-signal gain (km). Please refer to [1] and the Appendix for the relevant calculation technique.

Ultimately, the control-to-output transfer function will be:

km × KP × V 2irms

(resistive load)

RO ×

dVO

Rs 1 + s ×

G(s) =

= G2 × G3 × G4(s) = í

dVCOMP

km × KP × V 2irms

(constant power load)

Rs × VO

s × CO

where the small-signal multiplier gain km could be assumed equal to KM for simplicity.

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