The L6234 is a DMOSs triple half-bridge driver with input supply voltage up 52V and output current of
5A. It can be used in a very wide range of applications.
It has been realized in Multipower BCD60II technology which allows the combination of isolated DMOS
transistors with CMOS and Bipolar circuits on the same chip. It is available in Power DIP 20 (16+2+2)
and in Power SO 20 packages.
All the inputs are TTL/CMOS compatible and each half bridge can be driven by its own dedicated input
and enable.
The DMOS structure has an intrinsic free wheeling body diode so the use of external diodes, which are
necessary in the bipolar configuration, can be avoided. The DMOS structure allows a very low quiescent
current of 6.5 mA typ. at Vs=42V , irrespective of the load.
DEVICE DESCRIPTION
The device is composed of three channels. Each channel is composed of a half bridge with two power
DMOS switches ( typ. Rdson of 300mW @ 25°C) and intrinsic free wheeling diodes. Each channel includes two TTL/CMOS and uP compatible comparators, and a logic block to interface the inputs with the
drivers. The device includes an internal bandgap reference of 1.22V, a 10V voltage reference to supply
the internal circuitry of the device, a central charge pump to drive the upper DMOS switch, thermal shutdown protection and an internal hysteretic function which turns off the device when the junction temperature exceeds approximately 160 °C. Hysteresys is about 20 °C.
Figure 1. L6234 Block Diagram
April 2001
IN1
EN1
IN2
EN2
IN3
EN3
C3
10nF
CHARGE
PUMP
THERMAL
PROTECTION
1µF
VREFVCP
C4 220nF
C5
VBOOT
T1
T2
T3
T4
T5
T6
Vs
VsC2
OUT1
OUT2
SENSE1
OUT3
SENSE2
D98IN940A
100nF
GND
V
10V
REF
D2
1N4148
D1
1N4148
100µF
BRUSHLESS
MOTOR
WINDINGS
R
SENSE
Vs
C1
1/14
]
AN1088 APPLICATION NOTE
PIN DESCRIPTION.
Vs ( INPUT SUPPLY VOLTAGE PINS).
Figure 2.
V
S
These are the two input supply voltage pins. The unregulated
input DC voltage can range from 7V to 52V.
With inductive loads the recommended operating maximum
supply voltage is 42V to prevent overvoltage applied to the
DMosfets. In fact considering a full bridge configuration (see
ON/OFF
T1
L
B
-V
F
T3
C
(VS+VF)
ON
V
F
OFF
fig. 2), when the br idge is switched of f (ENABLE CHOPPING)
the current recirculation produces a negative voltage to the
source of the lower DMOS switches (point A). In this condition the drain-source voltage of T
Dinamically V
slope, dI/dt, and also V
can be same Volts depending on the current
F
sense
and T4 is VS + VF + V
1
sense
, depending on the parasitic in-
ductance and current slope can be some Volts. So the drain-
T2T4
.
-V
A
SENSE
Rsense
ON/OFF
S
D98IN938A
source voltage of T1 and T4 DMOS switches can reach more
than 10V over the V
voltage. The input capacitors C1 and C2 are chosen in order to reduce overvoltage
S
due to current decay and to parasitic inductance. For this reason C2 has to be placed as closed as possible to V
and GND pins.
S
The device can sustain a 4A DC input current f or each of the two Vs pi ns, in accordance with the
power dissipation.
Figure 3. Reference Voltage vs.
OUT1, OUT2, OUT3 (OUTPUTS).
These are the output pins
that correspond to the mid point of each half bridge. They are
designed to sustain a DC current of 4A.
SENSE1, SENSE2.
SENSE1 is the common source of the lower DMOS of the half
bridge 1 and 2.
SENSE2 is the source of the lower DMOS of the half bridge
3.
Each of these pins can handle a current of 5A.
A resistance, Rsense, connected to these pins provides feed-
back for motor current control.
Care must be taken with the negative voltage applied to these
pins : negative DC voltage lower than -1V could damage the
device. For duration lower than 300ns the device can sustain
pulsed negative voltage up to -4V.
For example, if enable chopping current control method is
used, negative voltage pulses appear to these pins, due to the
current recirculation through the sensing resistor.
Vref ( Voltage Reference).
This is t he internal 10V voltag e reference pi n to bias the log ic
and the lo w volt a ge circu it ry of the d evic e. A 1µF electrolytic capacitor connected from this pin to GND ens ur es the s tability of the
Vref [V]
11
10
9
8
7
6
5
4
3
2
1
0
-50-250255075100 125 150
Figure 4. Reference Voltage vs.
Vref [V]
12
10
8
Junction Temperature.
Vs = 52V
Vs = 24V
Vs = 10V
Vs = 7V
Tj [°C]
Supply Voltage.
DMOS drive circuit. This pin can be externally loaded up to 5mA .
Figure 3 and 4 show the typical be havior of the Vref pin.
6
4
Vcp ( CHARGE PUMP ).
Tj = 25°C
2
This is the internal oscillator output pin for the charge pump.
The oscillator supplied by the 10V Voltage Reference
switches from GND to 10V with a typical frequency of
2/14
0
01020304050
Vs [V
AN1088 APPLICATION NOTE
1.2MHz (see fig 4). When the oscillator output is at ground , C3 is charged by Vs through D1. When it
rises to 10V, D1 is reverse biased and the charge flows from C3 to C4 through D2, so the Vboot pin after a few cycles reaches the maximum voltage of Vs + 10V - VD1- VD2.
Vboot ( BOOTSTRAP).
This is the input bootstrap pin which gives the overvoltage nec essary to dr iv e all the upper DMOS of the
three half bridges (see fig 5).
Figure 5. Charge Pump Circuit.
Vs
C1
C2
100µF
0.1µF
Vs
Vs-VD1
Vs+Vref-VD1
f=1.2 MHz
VCP
D1
1N4148
C3
10nF
Vref
D2
1N4148
Vs+Vref-VD1-VD2
C4
0.22µF
VBOOT
CHARGE
PUMP
f=1.2 MHz
Vref
10V
HIGH
SIDE
DRIVER
OUT
SENSE
LOGIC INPUTS PINS.
EN1, EN2, EN3 (ENABLES).
These pins are TTL/CMOS and µP compatible. Each half bridge can be enabled by its own dedicated
pin with a logic HIGH. The logic LOW on these pins switches off the related half bridge (see Fig. 6). The
maximum switching frequency is 50kHz.
Figure 6. Control logic for each half bridge.
INPUT
ENABLE
UPPER
DMOS
LOWER
DMOS
low level
high level
DMOS OFF
DMOS ON
high level
high level
DMOS ON
DMOS OFF
low level
low level
DMOS OFF
DMOS OFF
high level
low level
DMOS OFF
DMOS OFF
time
time
time
time
Figure 7. Cross Conduction Protection.
DMOS ON
tdelay
DMOS OFF
high level
low level
tdelay
300ns
DMOS OFF
DMOS ON
INPUT
PIN
UPPER
DMOS
LOWER
DMOS
low level
DMOS OFF
300ns
DMOS ON
time
time
time
IN1, IN2, IN3 (INPUTS).
These pins are TTL/CMOS and µP compatible. They allow switching on the upper DMOS ( INPUT at
high logic level) or the lower Dmos (INPUT at low logic level) in each half bridge (see Fig. 6).
3/14
AN1088 APPLICATION NOTE
Cross conduction protection (see Fig. 7) avoids simultaneously turning on both the upper and lower
DMOS of each half bridge. There is a fixed delay time of 300ns between the turn on and the turn off of
the two DMOS switches in each half bridge. The switching operating frequency is up 50kHz. High commutation frequency permits the r eduction of ripple of the output current but increa ses the device’s power
dissipation, however low commutation frequency causes high ripple of the output current. The switching
frequency should be higher than 16kHz to avoid acoustic noises.
The sink current at the INPUTS and ENABLES pins is approximately 30µA if the voltage to these pins is
at least 1V less than the Vref voltage (see Fig. 3 and Fig. 4). To avoid overload of the logic INPUTS and
ENABLES , voltage should be applied to Vs prior to the logic signal inputs.
POWER DISSIPATION
An evaluation of the power dissipation of the I C driving a three phase motor in a chopping current control application follows.
With a simplified approach it can be distinguished three periods (see Fig. 8) :
Figure 8.
Rise Time, Tr, period.
This is the rise time period, Tr, in which the current switches from one winding to another. In this
Tchop
Ipk
Iload
Ival
time a DMOS is switched on and the current increases up to the peak value Ipk with the law i(t)
= (Ipk/Tr) t. T he energy lost for t he rise time in
the period T is :
Erise =
Tr
Rdson ⋅ i
∫
0
2
dt = Rdson ⋅ I
(t)
2
pk ⋅
Tr
3
Fall Time,Tf, period.
Trise
Tload
Tfall
When the current switches from one winding to
another, there is a fall time in which the current
that flows in the intrisic diode of the DMOS decreases from Ipk to zer o. If VD is t he voltage fall
of the diode, the energy lost is :
tf
Efall =
VD(t) ⋅ i(t)dt
∫
0
Tload
During this time the current that flows in the winding is limited by the chopping current control. The energy dissipated due to the ON resistance of the DMOS is :
Eload = Rdson ⋅ (I
rms
2
⋅ Tload
)
In the formula, Irms is the RMS load current, given by :
Irms =
Iload
(
2
+
)
√
I
pk
2
3
√
− Ival
and Iload is the average load current.
When the switch is ON, the energy dissipated due to the commutation of the chopping current control in
the DMOS can be assumed to be:
Eon = Vs ⋅ Ival ⋅
tcom
2
where tcom is the commutation time of the DMOS switch.
4/14
AN1088 APPLICATION NOTE
When the switch is OFF :
Eoff = Vs ⋅ Ipk ⋅
tcom
2
The energy lost by commutation in a chopping period, given by Eon + Eoff, is :
Ecom = Vs ⋅ Iload ⋅ tcom
The energy lost by commutation during the Tload time is given by :
Ecom = Vs ⋅ Iload ⋅ tcom ⋅ Tload ⋅ fchop
Quiescent Power Dissipation, Pq.
The power dissipation due to the quiescent current is Pq = Vs ⋅ Iq , in which Iq is the quiescent current
at the chopping frequency, fchop = 1/Tchop.
Total Power Dissipation
.
Let’s evaluate the power dissipation of the device driving a three phase brushless motor in chopping current control. In the driving sequence only one upper DMOS and a lower one are on at the same time
(see fig. 9 and 10). The total power dissipation is given by :
2 ⋅ (Erise + Efall + Eload + Ecom
Ptot =
T
)
+ Pq
Figure 11 shows the total power dissi pation, Pd, of the L6234 driving a three phase brushless motor in
input chopping current control at different chopping frequency.
EVALUATION BOARD.
The L6234 Power SO20 board has been realized to evaluate the device driving, in closed loop control, a
three phase brushless motor with open collector Hall effect sensors.
Figure 9. In put chopping curren t cir c ulation.
_
PHASE 12
CHOPPING INPUT
Vs
ILOAD
ILOAD
I1B
IOFF
half bri dge 2
I2B
OFF
ON
I2B
I1B
I1A
half bri dge 1
I1A
ON/OFF
OUT1OUT2
OFF/ON
5/14
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