ST AN1059 Application note

AN1059

®

APPLICATION NOTE

DESIGN EQUATIONS OF HIGH-POWER-FACTOR

FLYBACK CONVERTERS BASED ON THE L6561

by Claudio Adragna

Despite specific for Power Factor Correction circuits using boos t topology, the L6561 can be s uc­cessfully used to control flyback converters. Among the various configurations that an L6561-based
flyback converter can assume, the high-PF one is particularly interesting because of both its peculiar­ity and the advantages it is able to offer. AC-DC adapters for mobile or office equipment, off-line bat­tery chargers and low-power SMPS are the most noticeable examples of application that this configu­ration can fit.

This paper describes the equations governing such a kind of flyback converter with the aim of provid­ing a number of relationships useful to the system designer.

INTRODUCTION

Three different configurations that an L6561-based
flyback converter can assume have been identified.
They are illustrated in fig. 1.

Configurations a) and b) are basically conventional
flyback converters. The former works in TM (Transi­tion Mode, i.e. on the boundary between continuous
and discontinuous inductor current mode), therefore
at a frequency depending on both input v oltage and
output current. The latter works at a fixed frequency,
imposed by the synchronisation signal, and is ther e­fore completely equivalent to a flyback converter
based on a standard PWM controller.

Configuration c), which most exploits the aptitude of
the L6561 for performing power factor correction,
works in TM too but quit e differently: the input ca­pacitance is so small that the input voltage is very close to a rectified sinusoid. Besides, the control loop
has a narrow bandwidth so as to be little sensitive to the twice mains frequency ripple appearing at the
output.

Figure 1a. TM Flyback Configurati on

Vac

DISABLE

VCCZCD

L6561

GD

C

BULK

OPTO

+

TL431

Vout

Figure 1b. Synchronis ed Fly ba ck C onfiguration

OPTO

+

TL431

Vout

Vac

SYNCH

DISABLE

L6561

September 2003

BULK

C

VCCZCD

GD

Figure 1c. High-PF Flyback Configuration

DISABLE

Vac

COMP

MULT

L6561

INV

VCCZCD

GD

C

IN

(B

W

Vout

OPTO

+

TL431

<100 Hz)

1/20

AN1059 APPLICATION NOTE

Actually, the high power factor (PF) exhibited by this topology can be considered just as an additional
benefit but not the main reason that makes this solution attractive. In fact, despite a PF greater than 0.9
can be easily achieved, it is a real challenge to comply with EMC norms regarding the THD of line cur­rent, especially in universal mains applications.

There are, however, several applications in the low-power range (to which EMC norms do not apply) that
can benefit from the advantages offered by a high-PF flyback converter. These advantages can be sum­marised as follows:

for a given power rating, the input capacitance can be 200 times less, thus the bulky and costly high

●

voltage electrolytic capacitor after the rectifier bridge will be replaced by a small-size, cheaper film ca­pacitor.

efficiency is high at heavy load, more than 90% is achievable: TM operation ensures low turn-on

●

losses in the MOSFET and the high PF reduces dissipation in the rectifier bridge. This, in turn, mini­mises requirements on heatsinks;

low parts count, which helps reduce encumbrance and assembly cost.

●

In addition, the unique features of the L6561 offer remarkable advantages in numerous applications:

efficiency is high even at very light load: the low current consumption of the L6561 minimises the

●

power dissipated by both the start-up resistor and the self-supply circuit. An L6561-based high-PF fly­back converter can easily meet Blue Angel regulations;

additional functions available: the L6561 provides overvolt age protection as well as the possibility to

●

enable/disable the converter by means of its ZCD pin.

There are, on the other hand, some drawbacks, inherent in high-PF topologies, limiting the applications
that such a converter can fit (AC-DC adaptors, battery chargers, low-power SMPS, etc.) and which one
has to be aware of:

twice-mains-frequency ripple on the output: unavoidable if a high PF is desired. A large output ca-

●

pacitance will reduce its amount. Speeding up the control loop may lead to a compromise between a
reasonably low output ripple and a PF still reasonably high;

poor transient response: as to this point too, speeding up the control loop may lead to a compromise

●

between an acceptable transient response and a reasonably high PF;

Figure 2. Internal Block Diagram of the L6561.

1

INV

V

VOLTAGE

REGULATOR

8

CC

20V

R2

6

2.1V

1.6V

GND

INTERNAL

SUPPLY 7V

R1

V

REF2

+

-

-

2.5V
+

OVER-VOLTAGE

DETECTION

UVLO

ZERO CURRENT

+

-

5

ZCD

DETECTOR

COMP MULT CS
23 4

MULTIPLIER

+-

RSQ

DISABLE

40K

5pF

DRIVER

STARTER

D97IN547D

V

CC

7

GD

2/20

AN1059 APPLICATION NOTE

large output capacitance (in the thousand µF, depending on the output power) is required: however,

●

cheap standard capacitors and not costly high-quality parts are needed. In fact, a low ESR and an
adequate AC current capability are automatically achieved. Besides, in c onventional flyback convert­ers there is usually plenty of output capacitance too, thus this is not so dramatic as it may seem at
first sight;

secondary post-regulation will be required where t ight specifications on the output ripple and/o r on

●

the transient behaviour are given. However, this is true also for a standard flyback;
the system is unable to cope with line missing cycles at heavy load unless an exceedingly high output

●

capacitance is used.

In the following, the operation of a high-PF flyback converter will be discussed in details and numerous
relationships, useful for its design, will be established.

Preliminary statements

In order to generate the equations governing the operation of a high-PF flyback converter working in TM,
refer also to the internal block diagram of the L6561(see fig. 2). For details concerning the operation of
the L6561, please refer to Ref. [1].

The following assumptions will be made:

1. the line voltage is perfectly sinusoidal and the rectifier bridge is ideal, thus the voltage downstream
the bridge, sensed by the input of the L6561’s multiplier (MULT, pin 3) is a rectified sinusoid:

V

(t) = VPK ⋅ |sin (2

in

⋅ π ⋅

fL ⋅ t)|

where V

is equal to the RMS line voltage, V

PK

, times the square root of 2, and fL is the line fre-

RMS

quency (usually 50 or 60 Hz).

2. the output of L6561’s Error Amplifier (V

) is constant for a given line half-cycle;

COMP

3. transformer’s efficiency is 1 and its windings are perfectly coupled.

4. ZCD circuit’s delay is negligible thus the converter works exactly on the boundary between continuous
and discontinuous current conduction mode (TM operation).

As a result of the first two assumptions, the peak primary current is enveloped by a rectified sinusoid:

I

pkp

(t) = I

⋅ |sin (2 ⋅ π ⋅ fL ⋅ t)| (1)

PKp

One consequence of assumption 3 is t hat the peak secondary current is proportional to the primary one,
depending on transformer’s primary-to-secondary turns ratio n:

I

To simplify the notation, in the following the phase angle θ = 2

(t) = n ⋅ I

pks

pkp

(t)

f

⋅ t of the sinusoidal quantities will

⋅ π ⋅

L

be indicated and all the quantities depending on the instantaneous line voltage will be considered as a
function of θ, instead of time.

Timing relationships

The ON-time of the power switch is expressed by:

L

⋅ I

p

T

=

ON

pkp

V

(θ)

in

(θ)

=

L

⋅ I

p

PKp

(2),

V

PK

where L

is the inductance of transformer’s primary winding. Eqn. (2) shows that TON is constant over a

p

line half-cycle, exactly like in boost topology. The OFF-time is instead variable:

L

p

T

OFF

=

⋅ n ⋅ I

L

⋅ I

(θ)

s

pks

V

+ V

(

out

2

n

=

V

(

)

f

out

pkp

+ V

(θ)
)

f

=

L

⋅ I

p

n ⋅ (V

PKp

⋅ |sin

+V

out

f

(θ)
)

|

(3),

3/20

AN1059 APPLICATION NOTE

where Ls is the inductance of the secondary winding, I
voltage of the converter (supposed to be a regulated DC value) and V

(θ) the peak secondary current, V

pks

the forward drop on the output

f

the output

out

catch diode.
Since the system works in TM, the sum of the ON and the OFF times equals the switching period:

⋅ I

where V

= n ⋅ (V

R

+ Vf ) is the so-called reflected voltage.

out

The switching frequency f

T = T

= T

sw

L

p

+ T

ON

-1

, therefore, varies with the instantaneous line voltage:

=

OFF

f

=

sw

Lp ⋅ I

PKp

V

PK

V

PK

⋅

PKp

1 +

V





1 +

V

PK

R

⋅ |sin

⋅

(θ)



|

(4)




1

V

PK

V

R

⋅ |sin

(θ)

|

and reaches its minimum value on the peak of the sinusoid (sin (θ)=1):

f

sw min

=

V

Lp ⋅ I

PK

PKp

⋅

1 +

1

V

PK

V

(5)

R

This value, calculated at the minimum line voltage, must be greater than the maximum one of the inter­nal starter of the L6561 (≈14 kHz ), in order to ensure a correct TM operation. To accomplish with this
requirement, the primary inductance L

will be properly selected (not exceeding an upper limit). Actually,

p

to minimise the size of the transformer, the minimum frequency will usually be selected quite higher than
15 kHz, say 25-30 kHz or more, so the value of L

needs not have a tight tolerance.

p

The duty cycle, that is the r atio between the ON-time and t he switching period, will vary with the instan­taneous line voltage as well (because of the variation of T

), as it is possible to find by dividing eqn.(2)

OFF

by (4):

T

ON

Equations (2) and (4) show that T

D =

and T, respectively, can be short at will if I

ON

=

T

1 +

zero, especially at high input voltage. In the real-world operation, it must be c onsidered that T

1

V

PK

⋅ |sin

V

R

(θ)

(5’)

|

(i.e. the load) tends to

PKp

ON

cannot

go below a minimum amount and so will do the switching period as well. This minimum (typically, 0.4-

0.5µs) is imposed by the internal delay of the L6561 and by the turn-off delay of the MOSFET.

When this minimum is reached, the energy drawn each cycle exceeds the short-term demand from the
load, thus the control loop causes some cycles to be skipped so as to maintain the long-term energy bal­ance. When the load is so low that many cycles need to be skipped, the amplitude of the drain voltage
ringing becomes so small that it can no longer trigger the ZCD Block of the L6561. In that case the inter­nal starter of the IC will start a new switching cycles sequence.

Something similar applies to t he duty cycle as well, which eqn. (5’) predicts to be unity when θ = 0, that
is at the zero-crossings of the mains voltage. In reality, a number of parasitic effects cause T

ON

and T

OFF

not to follow the ideal relationships (2) and (3). The effect of that on the overall operation is however
negligible because the energy processed near a zero-crossing is very little.

In the following, the ratio bet ween the line peak voltage V

and the reflected voltage VR will be indi-

PK

cated with Kv:

V

PK

K

=

v

V

R

Energetic relationships

Apart from the duty cycle, all the quantities expressed in the timing relationships depend on the through­put power, which is represented in the above equations by I

, the peak primary current oc curring at

PKp

4/20

the peak of the sinusoid of the primary voltage.
The following relationships relate I

to the input power Pin and allow both to explicate the timing rela-

PKp

tionships and to calculate all the currents circulating in the circuit.

Figure 3. High-PF Flyback current waveforms

Secondary current

peak envelope

Primary current

peak envelope

AN1059 APPLICATION NOTE

Average

primary current

ON

OFF

The primary current I

SWITCH

(t) is triangular-shaped and flows only during the switch ON-time, as illustrated by

p

the shaded triangles shown in fig. 3. As earlier stated by equation (1), during each half-cycle the height
of these triangles varies with the instantaneous line voltage:

I

pkp

(θ) = I

⋅ |sin (θ)|,

PKp

their width is constant but they are spaced out by a variable amount given by (3).
Looking at the primary on a "f

" time scale, the current Iin(θ) downstream the bridge rectifier is the aver-

L

age value of each triangle over a switching cycle (the thick black curve of fig. 3):

|sin

|

0.5

1

0

0.5

(θ)

⋅ |sin

v

(θ)

Kv=0.5

|

Kv=1

Kv=2

Kv=4

1

(θ) =

⋅ I

(θ) ⋅

pkp

2

I

in

Figure 4a. Primary Current (@ fL time scale)

1

0.75

Iin(θ)

after the

bridge

Kv=0.5

0.5

0.25

Kv=1

Kv=2

Kv=4

D =

1

⋅ I

⋅

PKp

2

1 + K

Figure 4b. Line Current (@ fL time scale)

Iin(θ)

before

the

bridge

0

0 1.57 3.14 4.71 6.28

θ

1

0 1.57 3.14 4.71 6.28

θ

5/20

AN1059 APPLICATION NOTE

This function, shown in fig. 4a for different values of Kv, is a periodic even function, at twice line fre­quency, not negative because of the bridge rectifier. Conversely, the current drawn from the mains will
be the "odd counterpart" of (6), at line frequency, as shown in fig. 4b).

Actually, it is realistic to think that a filtering action eliminates the switching frequency component of the
current upstream the rectifier bridge, so that the mains "can see" only the average value. This current
would be sinusoidal for K
Since K

cannot be zero (which would require the reflected voltage to tend to infinity), flyback topology

v

does not permit unity power factor even in the ideal case, unlike boost topology.
In order to simplify the following calculations, it is possible to eliminate the absolute value from | sin (θ)|

by considering θ ∈ [0 , π] and assuming the various functions to be either even or odd by definition, de­pending on their physical role.

The input power P

will be calculated by averaging the product Vin(θ) • Iin(θ) over a line half-cycle:

in

It is now advantageous to introduce the following function:

whose diagram as a function of the variable x is shown in fig. 5.

= 0 but will be distorted from an ideal sinusoid so much as Kv increases.

v

1 + K

sin2

sin

(θ)

2

⋅ sin

v

(θ)

(θ)

(θ)

dθ (8),

(7).

____________

P

= Vin

in

F2(x) =

Iin

(θ) ⋅

sin

1 + x ⋅ sin

(θ)

2

=

(θ)

1

⋅ VPK ⋅ I

2

=

(θ)

1

⋅ ∫

π

⋅

PKp

π

1 + x ⋅ sin

o

Figure 5. High-PF Flyback characteristic

functions : F 2(x ) dia g ra m

0.5

0.4

0.3

F2( )x

0.2

0.1
0

0123456789

x

Although a closed form exists for the integral in (8),
it is not so handy, thus for practical use it is more
convenient to provide a "best fit" approximation:

3

−

F2(x) ≈

0.5 + 1.4 ⋅ 10
1 + 0.815 ⋅ x

⋅ x

From (7), taking (8) into account, it is possible to
calculate I

10

PKp

:

2 ⋅ P

I

PKp

=

VPK ⋅ F2(K

in

,

)

v

which will assume its maximum value at minimum

.

mains voltage.

The total RMS value of the primary current, useful for power loss estimate on the primary side, is calcu­lated considering the RMS value of each triangle of I

1

2

I

RMSp

√

=

⋅ I

pkp

3

(θ) ⋅

D = I

√

⋅

PKp

(t) and averaging over a line half-cycle:

p

1
3

⋅

sin

1 + K

2

⋅ sin

v

(θ)

(θ)

= I

PKp

√

⋅

F2 (K

3

)

v

(9).

The DC component of the primary current, useful to discriminate DC and AC losses in the transformer, is
the average value of I

(θ) over a line half-cycle:

in

_____

I

DCp

= I

=

(θ)

in

sin

1

⋅ I

⋅

PKp

2

1 + K

(θ)

⋅ sin

v

(10).

(θ)

Considering the following function:

F1(x) =

6/20

sin

(θ)

1 + x ⋅ sin

(θ)

=

1

π

⋅ ∫

π

sin

1 + x ⋅ sin

o

(θ)

(θ)

dθ,