ST AN1059 Application note

INTRODUCTION

Three different configurations that an L6561-based

flyback converter can assume have been identified.

They are illustrated in fig. 1.

Configurations a) and b) are basically conventional

flyback converters. The former works in TM (Transi-

tion Mode, i.e. on the boundary between continuous

and discontinuous inductor current mode), therefore

at a frequency depending on both input v oltage and

output current. The latter works at a fixed frequency,

imposed by the synchronisation signal, and is ther e-

fore completely equivalent to a flyback converter

based on a standard PWM controller.

Configuration c), which most exploits the aptitude of

the L6561 for performing power factor correction,

works in TM too but quit e differently: the input ca-

pacitance is so small that the input voltage is very close to a rectified sinusoid. Besides, the control loop

has a narrow bandwidth so as to be little sensitive to the twice mains frequency ripple appearing at the

output.

September 2003

AN1059

APPLICATION NOTE

DESIGN EQUATIONS OF HIGH-POWER-FACTOR

FLYBACK CONVERTERS BASED ON THE L6561

by Claudio Adragna

Despite specific for Power Factor Correction circuits using boos t topology, the L6561 can be s uc-

cessfully used to control flyback converters. Among the various configurations that an L6561-based

flyback converter can assume, the high-PF one is particularly interesting because of both its peculiar-

ity and the advantages it is able to offer. AC-DC adapters for mobile or office equipment, off-line bat-

tery chargers and low-power SMPS are the most noticeable examples of application that this configu-

ration can fit.

This paper describes the equations governing such a kind of flyback converter with the aim of provid-

ing a number of relationships useful to the system designer.

VCCZCD

L6561

Vac

BULK

OPTO

TL431

Vout

DISABLE

Figure 1a. TM Flyback Configurati on

VCCZCD

L6561

Vac

BULK

OPTO

TL431

SYNCH

Vout

DISABLE

Figure 1b. Synchronis ed Fly ba ck C onfiguration

VCCZCD

L6561

Vac

INV

OPTO

TL431

<100 Hz)

Vout

COMP

DISABLE

MULT

Figure 1c. High-PF Flyback Configuration

1/20

Actually, the high power factor (PF) exhibited by this topology can be considered just as an additional

benefit but not the main reason that makes this solution attractive. In fact, despite a PF greater than 0.9

can be easily achieved, it is a real challenge to comply with EMC norms regarding the THD of line cur-

rent, especially in universal mains applications.

There are, however, several applications in the low-power range (to which EMC norms do not apply) that

can benefit from the advantages offered by a high-PF flyback converter. These advantages can be sum-

marised as follows:

●

for a given power rating, the input capacitance can be 200 times less, thus the bulky and costly high

voltage electrolytic capacitor after the rectifier bridge will be replaced by a small-size, cheaper film ca-

pacitor.

●

efficiency is high at heavy load, more than 90% is achievable: TM operation ensures low turn-on

losses in the MOSFET and the high PF reduces dissipation in the rectifier bridge. This, in turn, mini-

mises requirements on heatsinks;

●

low parts count, which helps reduce encumbrance and assembly cost.

In addition, the unique features of the L6561 offer remarkable advantages in numerous applications:

●

efficiency is high even at very light load: the low current consumption of the L6561 minimises the

power dissipated by both the start-up resistor and the self-supply circuit. An L6561-based high-PF fly-

back converter can easily meet Blue Angel regulations;

●

additional functions available: the L6561 provides overvolt age protection as well as the possibility to

enable/disable the converter by means of its ZCD pin.

There are, on the other hand, some drawbacks, inherent in high-PF topologies, limiting the applications

that such a converter can fit (AC-DC adaptors, battery chargers, low-power SMPS, etc.) and which one

has to be aware of:

●

twice-mains-frequency ripple on the output: unavoidable if a high PF is desired. A large output ca-

pacitance will reduce its amount. Speeding up the control loop may lead to a compromise between a

reasonably low output ripple and a PF still reasonably high;

●

poor transient response: as to this point too, speeding up the control loop may lead to a compromise

between an acceptable transient response and a reasonably high PF;

MULTIPLIER

REF2

OVER-VOLTAGE

DETECTION

VOLTAGE

REGULATOR

UVLO

INTERNAL

SUPPLY 7V

2.5V

DRIVER

STARTER

ZERO CURRENT

DETECTOR

DISABLE

2.1V

1.6V

23 4

ZCD

INV

COMP MULT CS

GND

D97IN547D

20V

40K

5pF

Figure 2. Internal Block Diagram of the L6561.

AN1059 APPLICATION NOTE

2/20

●

large output capacitance (in the thousand

F, depending on the output power) is required: however,

cheap standard capacitors and not costly high-quality parts are needed. In fact, a low ESR and an

adequate AC current capability are automatically achieved. Besides, in c onventional flyback convert-

ers there is usually plenty of output capacitance too, thus this is not so dramatic as it may seem at

first sight;

●

secondary post-regulation will be required where t ight specifications on the output ripple and/o r on

the transient behaviour are given. However, this is true also for a standard flyback;

●

the system is unable to cope with line missing cycles at heavy load unless an exceedingly high output

capacitance is used.

In the following, the operation of a high-PF flyback converter will be discussed in details and numerous

relationships, useful for its design, will be established.

Preliminary statements

In order to generate the equations governing the operation of a high-PF flyback converter working in TM,

refer also to the internal block diagram of the L6561(see fig. 2). For details concerning the operation of

the L6561, please refer to Ref. [1].

The following assumptions will be made:

1. the line voltage is perfectly sinusoidal and the rectifier bridge is ideal, thus the voltage downstream

the bridge, sensed by the input of the L6561’s multiplier (MULT, pin 3) is a rectified sinusoid:

(t) = V

⋅

|sin (2

⋅ π ⋅

⋅

t)|

where V

is equal to the RMS line voltage, V

RMS

, times the square root of 2, and f

is the line fre-

quency (usually 50 or 60 Hz).

2. the output of L6561’s Error Amplifier (V

COMP

) is constant for a given line half-cycle;

3. transformer’s efficiency is 1 and its windings are perfectly coupled.

4. ZCD circuit’s delay is negligible thus the converter works exactly on the boundary between continuous

and discontinuous current conduction mode (TM operation).

As a result of the first two assumptions, the peak primary current is enveloped by a rectified sinusoid:

pkp

(t) = I

PKp

⋅

|sin (2

⋅

t)| (1)

One consequence of assumption 3 is t hat the peak secondary current is proportional to the primary one,

depending on transformer’s primary-to-secondary turns ratio n:

pks

(t) = n

⋅

pkp

(t)

To simplify the notation, in the following the phase angle

= 2

⋅ π ⋅

⋅

t of the sinusoidal quantities will

be indicated and all the quantities depending on the instantaneous line voltage will be considered as a

function of

, instead of time.

Timing relationships

The ON-time of the power switch is expressed by:

⋅

pkp

(θ)

⋅

PKp

(2),

where L

is the inductance of transformer’s primary winding. Eqn. (2) shows that T

is constant over a

line half-cycle, exactly like in boost topology. The OFF-time is instead variable:

OFF

⋅

pks

(θ)

(

out

)

⋅

pkp

(θ)

(

out

)

⋅

PKp

⋅

|sin

(θ)

⋅

(

out

)

(3),

AN1059 APPLICATION NOTE

3/20

where L

is the inductance of the secondary winding, I

pks

(

) the peak secondary current, V

out

the output

voltage of the converter (supposed to be a regulated DC value) and V

the forward drop on the output

catch diode.

Since the system works in TM, the sum of the ON and the OFF times equals the switching period:

OFF

⋅

PKp

⋅







⋅

|sin

(θ)







(4)

where V

= n

⋅

out

+ V

) is the so-called reflected voltage.

The switching frequency f

= T

-1

, therefore, varies with the instantaneous line voltage:

⋅

PKp

⋅

|sin

(θ)

and reaches its minimum value on the peak of the sinusoid (sin (

)=1):

sw min

⋅

PKp

⋅

(5)

This value, calculated at the minimum line voltage, must be greater than the maximum one of the inter-

nal starter of the L6561 (

≈

14 kHz ), in order to ensure a correct TM operation. To accomplish with this

requirement, the primary inductance L

will be properly selected (not exceeding an upper limit). Actually,

to minimise the size of the transformer, the minimum frequency will usually be selected quite higher than

15 kHz, say 25-30 kHz or more, so the value of L

needs not have a tight tolerance.

The duty cycle, that is the r atio between the ON-time and t he switching period, will vary with the instan-

taneous line voltage as well (because of the variation of T

OFF

), as it is possible to find by dividing eqn.(2)

by (4):

⋅

|sin

(θ)

(5’)

Equations (2) and (4) show that T

and T, respectively, can be short at will if I

PKp

(i.e. the load) tends to

zero, especially at high input voltage. In the real-world operation, it must be c onsidered that T

cannot

go below a minimum amount and so will do the switching period as well. This minimum (typically, 0.4-

0.5

s) is imposed by the internal delay of the L6561 and by the turn-off delay of the MOSFET.

When this minimum is reached, the energy drawn each cycle exceeds the short-term demand from the

load, thus the control loop causes some cycles to be skipped so as to maintain the long-term energy bal-

ance. When the load is so low that many cycles need to be skipped, the amplitude of the drain voltage

ringing becomes so small that it can no longer trigger the ZCD Block of the L6561. In that case the inter-

nal starter of the IC will start a new switching cycles sequence.

Something similar applies to t he duty cycle as well, which eqn. (5’) predicts to be unity when

= 0, that

is at the zero-crossings of the mains voltage. In reality, a number of parasitic effects cause T

and T

OFF

not to follow the ideal relationships (2) and (3). The effect of that on the overall operation is however

negligible because the energy processed near a zero-crossing is very little.

In the following, the ratio bet ween the line peak voltage V

and the reflected voltage V

will be indi-

cated with K

Energetic relationships

Apart from the duty cycle, all the quantities expressed in the timing relationships depend on the through-

put power, which is represented in the above equations by I

PKp

, the peak primary current oc curring at

AN1059 APPLICATION NOTE

4/20

the peak of the sinusoid of the primary voltage.

The following relationships relate I

PKp

to the input power P

and allow both to explicate the timing rela-

tionships and to calculate all the currents circulating in the circuit.

The primary current I

(t) is triangular-shaped and flows only during the switch ON-time, as illustrated by

the shaded triangles shown in fig. 3. As earlier stated by equation (1), during each half-cycle the height

of these triangles varies with the instantaneous line voltage:

pkp

(

) = I

PKp

⋅

|sin (

)|,

their width is constant but they are spaced out by a variable amount given by (3).

Looking at the primary on a "f

" time scale, the current I

(

) downstream the bridge rectifier is the aver-

age value of each triangle over a switching cycle (the thick black curve of fig. 3):

(θ)

⋅

pkp

(θ)

⋅

PKp

⋅

|sin

(θ)

⋅

|sin

(θ)

Primary current

peak envelope

Secondary current

peak envelope

Average

primary current

OFF

SWITCH

Figure 3. High-PF Flyback current waveforms

Iin(

)

after the

bridge

Kv=4

Kv=2

Kv=1

Kv=0.5

0 1.57 3.14 4.71 6.28

0.25

0.5

0.75

Figure 4a. Primary Current (@ f

time scale)

Iin(

)

before

the

bridge

Kv=0.5

Kv=1

Kv=2

Kv=4

0 1.57 3.14 4.71 6.28

0.5

Figure 4b. Line Current (@ f

time scale)

AN1059 APPLICATION NOTE

5/20

This function, shown in fig. 4a for different values of K

, is a periodic even function, at twice line fre-

quency, not negative because of the bridge rectifier. Conversely, the current drawn from the mains will

be the "odd counterpart" of (6), at line frequency, as shown in fig. 4b).

Actually, it is realistic to think that a filtering action eliminates the switching frequency component of the

current upstream the rectifier bridge, so that the mains "can see" only the average value. This current

would be sinusoidal for K

= 0 but will be distorted from an ideal sinusoid so much as K

increases.

Since K

cannot be zero (which would require the reflected voltage to tend to infinity), flyback topology

does not permit unity power factor even in the ideal case, unlike boost topology.

In order to simplify the following calculations, it is possible to eliminate the absolute value from | sin (

by considering

∈

[0 ,

] and assuming the various functions to be either even or odd by definition, de-

pending on their physical role.

The input power P

will be calculated by averaging the product V

(

)

•

(

) over a line half-cycle:

(θ)

⋅

(θ)

____________

⋅

PKp

⋅

sin

(θ)

⋅

sin

(θ)

(7).

It is now advantageous to introduce the following function:

(

)

sin

(θ)

⋅

sin

(θ)

⋅

∫

sin

(θ)

⋅

sin

(θ)

(8),

whose diagram as a function of the variable x is shown in fig. 5.

Although a closed form exists for the integral in (8),

it is not so handy, thus for practical use it is more

convenient to provide a "best fit" approximation:

(

)

≈

0.5

1.4

⋅

−

⋅

0.815

⋅

From (7), taking (8) into account, it is possible to

calculate I

PKp

⋅

(

)

which will assume its maximum value at minimum

mains voltage.

The total RMS value of the primary current, useful for power loss estimate on the primary side, is calcu-

lated considering the RMS value of each triangle of I

(t) and averaging over a line half-cycle:

RMSp

√

⋅

pkp

(θ)

⋅

PKp

⋅

√

⋅

sin

(θ)

⋅

sin

(θ)

PKp

⋅

√

(

)

(9).

The DC component of the primary current, useful to discriminate DC and AC losses in the transformer, is

the average value of I

(

) over a line half-cycle:

DCp

(θ)

_____

⋅

PKp

⋅

sin

(θ)

⋅

sin

(θ)

(10).

Considering the following function:

(

)

sin

(θ)

⋅

sin

(θ)

⋅

∫

sin

(θ)

⋅

sin

(θ)

0123456789

0.1

0.2

0.3

0.4

0.5

F2( )x

Figure 5. High-PF Flyback characteristic

functions : F 2(x ) dia g ra m

AN1059 APPLICATION NOTE

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