ST AN1042 APPLICATION NOTE
AN1042
APPLICATION NOTE
ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT
by Microcontroller Division Application Team
INTRODUCTION
The goal of this appli cation note is to pres ent a usefu l example of com municati on using the
I2C peripheral of the ST7. The ST7 microcontroller is used as a slave an d can com municate
with any master. This slave, through the I2C interface, receives data bytes from the master implement ing er ror ma nage ment and re turns the m. This app licatio n has been r ealiz ed wi th a
ST72264,7-bit, general call and 10-bit addressing mode.
1 ST7 I2C INT ERFACE
The ST7 I2C peripheral allows multi master and slave communication with bus error management. In this application, only the single slave mode is used (with error management).
The I2C synchronous communication needs only two signals: SCL (Serial clock line) and SDA
(Serial data line). The corresponding por t pins have to be configured as floating inputs ( here
PA4 and PA6).
Please refer to the ST7 datasheet for more details.
1.1 COMMUNICATION SPEED
The ST7 I2 C peripher al allows to communi cate at diff erent spe eds. It is able to work in
standard and fast I2C modes up to 400kHz.
It’s the master which imposes the communication speed. For more details, please refer to the
AN971.
1.2 START, STOP CONDITION AND ACKNOWLEDGE GENERATION
The Start and Stop conditions are sent by the master.
An Acknowledge is sent after an address or a data byte is received when the ACK bit is set in
the Control register (CR).
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ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT
1.3 TRANSFER SEQUENCING Figure 1. I2C Slave Transfer Sequencing Diagram
7-bit Slave receiver:
S Address A Data1 A Data2 A
EV1 EV2 EV2 EV2 EV4
7-bit Slave transmitter:
S Address A Data1 A Data2 A
EV1 EV3 EV3 EV3 EV3-1 EV4
S
10-bit Slave receiver:
S HeaderAAddress A Data1 A
EV1 EV2 EV2 EV4
10-bit Slave transmitter:
SrHeader A Data1 A
EV1 EV3 EV3 EV3-1 EV4
.....
DataN A P
.....
DataN NA P
.....
DataN A P
DataN AP
....
.
Legend:S=Start, P=Stop, A=Acknowledge, NA=Non-Acknowledg e, EVx=Even t (with interruptif ITE=1).
EV1: EVF=1, ADSL=1, cleared by rea ding SR1 r egister.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3_1: EVF=1, AF=1, cleared by reading SR1 register.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
In blue are events sent by the master whereas blank ones are events sent by the slave.
These frames are sequential and as the SDA l ine is bidirectional, this line is held sometimes
by the master and sometimes by the slave.
1.4 SLAVE EVENT FLAGS AND INTERRUPT GENERATION Figure 2. Slave Interrupt Events Diagram
BTF
AF
ADSL
STOPF
BERR
*
*
EVF can also be set by EV6 or an error fro m the SR2 regis ter.
ITE
INTERRUPT
EVF
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ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT
2 ST7 I2C COMMUNICATION APPLICATIO N
2.1 HARDWARE CONFIGURATION
The ST7 I2C communication application hardware is composed by a ST72264 microcontroller
used as a slave which communicates with any master through an I2C bus interface.
Figure 3. ST7 I2C Communication Application
5V
SCL
SDA
Vdd
2x100Ω
2x27KΩ
master
SCL
SDA
Vdd
ST72F264
I2C
Vss
Vss
2.2 ST7 I2C PERIPHERAL BASIC DRIVERS
In this chapter all registers refer to the ST7 I2C peripheral ones (otherwise specified).
2.2.1 Initialize the I2C peripheral
In this application the initialization of the ST7 I2C peripheral is done completely by software.
First the Control register (CR) is cleared and the Data (DR) and Status (SR1,SR 2) registers
are touched to clear all possible pending event.
Then, the peripheral is enabled thr ough the C ontrol register (CR ). This action ne eds to wr ite
twice in the register due to the fact that the Control r egister (CR) bits can be set onl y when the
PE enab le bi t is alre ady set. To allow the pe riph eral to ack nowl edge th e re ceive d dat a the
ACK bit of the Control register (CR) is set.
2.2.2 Slave Communication on the I2C Bu s
First the interface frequency must be configured using the FRi bits in the OAR2 register.For
10 bit addressing mode, user must configure the slave address using the ADD9 and ADD8
bits of the OAR2 register.
To initiate a I2C com mu nication, fir st a start c onditi on has to be ge nerated an d then the se lected slave address has to be sent, both by the mas ter. As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface (OAR1) or the General Call address (if selected by software). If the GCAL option is to be implemented, user must enable it by selecting the
GCAL_Add in user customizable part of the code.
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