The purpose of this document is to explain the different low power modesavailable on ST7 devices and the ways to minimise power consumption. Many applications will have strict power
requirements, and there are several me thods of lowering the rate of po wer consumpti on
without sacrificing perform ance. Calculati ng the predicted power use is imp ortant to characterize the system ’s power supp ly requirem ents. T he ST7 can be put into one of se veral low
power modes by setting some bits in some registers. The utility of these low power modes depends on the specific application.
The basic explanation of this note is based on ST72F324, but is applicable to all ST7 general
purpose devices. P lease refer s ec tion “Ex amples” to s ee more i nformat ion on additio nal devices (ST7FLITE0).
2 POWER CONSUMPTION FACTO RS
CMOS digital logic device power consumption is affected by supply voltage and clock frequency. These parameters can be adjusted to realize power savings, and are readily controlled by the designer. In CMOS digital logic devices, powe r consumption is directly proportional to clock frequency and power supply squared.
power = CV2f
where: C is CMOS load capacitance, V is supply voltage, and f is clock frequency.
The amount of current used in CMOS logic is directly proportional to the voltage of the power
supply. Thus, power consumption may be reduced by lowering the supply voltage to the device. Power consu mption depends on the num ber of active peripherals. The greater the
number of active peripherals, the more power will be consumed. Power consumption also depends on, whether the oscillator is On or Off and whether the CPU is On or Off. It also depends
on PLL On/Off, CSS enabled/disabled and LVD On/Off.
Power Consumption is based on which mode a particular application is running. For example,
in ST7, “HALT” mode is the lowest power consumption mode without availability of Real Time
Clock and “ACTIVE-HALT” mode is the low est power consumption mode with Real Time
Clock available. To reducethe power consumption, clock frequency can be reduced whenever
fast processing is not required by the application.
This mode is the normal operation of any MCU, where
f
CPU
= f
OSC2
f
OSC2
= f
= f
/2 (when PLL is disabled by OPTION BYTE ).
OSC
*2 (when PLL is enabled by OPTION BYTE).
OSC
So, the consumption varies depending on whether the PLL is disabled or enabled.
3.2 SLOW MODE
This mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f
In this mode, the master clock frequency (f
The CPU and peripherals are clocked at this lower frequency (f
) can be divided by 2, 4, 8 or 16.
OSC2
CPU
). The c onf igura tion f or
CPU
).
clock frequency is:
f
CPU
= f
= f
/ 2, 4, 8, 16
OSC2
/ 4, 8, 16 or 32 (when PLL is disabled by OPTION BYTE).
OSC
Uses:
- To reduce the power consumption by decreasing the internal clock in the device.
- To adapt the internal clock frequency to the available supply voltage.
3.3 WAIT MODE
In this mode, the CPU is stopped and the peripherals are still running at standard f
CPU
. It is se-
lected by calling the ‘WFI’ instruction. All peripherals remain active.
During WAIT mode, the I[1:0] bits in the CC register are forced to ‘10’, to enable all interrupts.
All other registers and memory remain unchanged. The MCU re m ains in WAIT mode until an
interrupt or RESET occurs, whereupon the Program Counter branches to the star ting address
of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or
an Interrupt occurs, causing it to wake up.
Uses:
- To place the MCU in low power consumption mode by stopping the CPU.
- External interrupt capability with all peripherals remaining active
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1
3.4 SLOW WAIT MODE
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
In this mode, the CPU is stopped and the peripherals are still runni ng at t he f
CPU
defined
for SLOW mode . It is ac tivated when en tering WAIT mo de while the d evice is alrea dy in
SLOW mode.
Uses:
- To place the MCU simultaneou sly in Slow mode and Wait mod e to reduce the power con-
sumption.
3.5 ACTIVE-HALT MODE
In this mode, the C PU and the peripherals are stopped, but the os cillator is still running. Pe ripherals clocked with an external clock source can still be active.
It is selected by calling the “HALT” instruction when the MCCSR - OIE bit is set. “HALT” forces
the I[1:0 ] bits in th e CC r egis ter to ‘10’ to ena ble int errupts . The C PU c lock is stopped till a
Reset or MCC/RTC or CSS or other specific interrupt occurs.
To wake-up from ACTIVE-HALT, a Reset or MCC/RTC or CSS or other specific interrupt must
occur. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in
the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. The safeguard against staying locked in ACTIVE-HALT
mode is provided by the oscillator interrupt.
As soon as the interrupt capability of one of the oscillators is selected (MCCSR .OIE bit set),
entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. Because the watchdog remains active, this means that the MCU cannot spend more than a defined delay in ACTIVE-HALT mode.
Uses:
- To place the MCU in the lowest power consumption mode with Real Time Clock available.
- The CPU and Peripherals (Peripheral clocked with external clock source can still be active)
are OFF.
- To keep a wake-up time base, the Real Time Clock Main Clock Controller is running.
3.6 HALT MODE
In this mode, the oscillator is turned off. Peripheral s clocked with an ex ternal clock source can
still be active. Halt mode is selected by calling a “HALT” Instruction while the MCCSR - OIE bit
is cleared. “HALT” forces the I[1:0] bits in the CC register to ‘10’ to enable interrupts.
The CPU clock is stopped till a Reset or a specific interrupt (with “exit from Halt” capability) occurs. To wake-up the MCU from Halt mode (when the Watchdog is active or when the
5/25
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
Watchdog is inactive and the WDGHALT option bit is disabled.), a Reset or specific interrupt
must occur. B efore se rvicing a n inte rrupt , the C C regi ster is p ush ed on the sta ck. The I[1 :0]
bits in the CC register are set to the current softw are priority level of the interrupt routine and
recovered when the CC register is popped. When the Watchdog is active and the WDGHALT
option bit is enabled, a Watchdog reset is generated.
Uses:
– To place the MCU in the lowest power consumption mode without Real Time Clock.
– The CPU and Peripherals (Peripheral clocked with external clock source can still be active)
are OFF.
3.7 SUMMARY
Table 1. Summary Table
Oscilla tor /CPU/Peripheral Stat us
ST7 Modes
RunOnOnOnAvailableXReset
SlowOnOnOnAvailableXSet
WaitOnOffOnAvailableXReset
Slow-WaitOnOffOnAvailableXSet
Active-HaltOnOffOffAvailableSetX
HaltOffOffOffNot AvailableResetX
OscillatorCPUPeripheralsRTC
MCCSR-OIE
Bit
MCCSR-
SMS Bit
4 EXAMPLES
This section provides standard methods to achieve minimum power consumption in a particular ST7 application for following different microcontrollers, which can be used as a reference
during application development. For user reference it also provides data values measured in
lab for described appl ications presented as ex amples for di fferent devices. CLICK on requi red
device to see more information on
- Appendix A: ST72F324 Sta ndard Exam ples
- Appendix B: ST7FLITE0 Standard ExamplesNote : The v alues provided in this application note are typical only, measured on a small
number of devices.
5 POWER MANAGEMENT TIPS
– If you are not using the ADC, SPI, SCI or timers in the application, switch them off.
– All the port pins should be push pull output at low level.
– All I/O ports should be connected to an external pull-up or pull-down to avoid leakage due to
floating inputs.
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HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
– Use Wait mode if you need external interrupt capability in low power mode and if peripherals
are to be remain active.
– Use the appropriate V
because higher the V
value. The VDD value must not be greater than the required value
DD
value, the more power will be consumed.
DD
– Configure the OSCRANGE[2:0] option bits for the minimum frequency range. For example,
if you use 8 MHz oscillator frequency, you must select the OSCRANGE[2:0] option bits for
medium speed resonator 4/8 MHz, not for high speed resonator 8/16 MHz.
6 APPENDIX A: ST72F324 STANDA RD EXAMPLES
This section provides examples of how to minimise the consumption in a particular ST7 application for device ST72F324.( Use ST72F324 datasheet for a reference)
6.1 EXAMPLE 1: STATIC MEASUREMENT
This example provides a static method of measuring the current consumed by the microcontroller in different modes and without any I/O activity. The measurement is done using the following configuration.
6.1.1 Measurement Configuration
– All ports have been set as Push-Pull Outputs at low level.
– All other peripherals are in reset configuration.
– After this, MCU is put into different modes by calling different instructions and by setting
some bits (in the MCCSR register).
– In Option Byte, PLL*2 is disabled, CSS is also disabled and LVD is Off.
Figure 1. Hardware Setup
V
DD
Vpp/ICCSEL
V
DD
mA
ST72324
V
SS
6.1.2 Consumption
The consumption mainly depends on the mode selected and the CPU frequency.
7/25
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
6.1.2.1 Run Mode
Methodology:
A resonator oscillator is used with f
at 4 / 8 MHz. PLL*2 is disabled (So, f
osc
osc2
is f
osc
/2). All
peripherals are in reset configuration except the ports. So, the SMS bit in the MCCSR is reset
to 0. The CP1 and CP0 bits in the MCCSR are also reset to 0 and hence f
CPU
is f
. All ports
osc2
are set as Push-Pull Outputs with low level.
Measurements:
Table 2. Consumption I
f
(MHz)f
OSC
42 3.90 mA4.38 mA4.91 mA
84 5.88 mA6.67 mA7.42 mA
(MHz)IDD at V
CPU
(RUN Mode) at TA = + 25 °C
DD
= 4.5 VIDD at V
DD
= 5 VIDD at V
DD
DD
= 5.5 V
6.1.2.2 Slow Mode
Methodology: A resonator oscillator is used with f
is f
/2. All peripherals are in reset configuration except the ports and the SMS bit in the
osc
at 4 / 8 MHz. PLL*2 is disabled. So, f
osc
osc2
MCCS R is s et to 1. The CP1 a nd CP 0 bi ts in th e MC CSR are set to an ap prop riate value .
Hence f
CPU
is f
osc
/4, f
osc
/8, f
osc
/16, f
/32. Al l po rts a re set as Pus h-P ull Ou tput s w ith low
osc
level.
Measurements:
Table 3. Consumption I
(MHz)f
f
OSC
40.1251.33 mA1.51 mA1.70 mA
4 / 80.251.67 mA1.93 mA2.18 mA
4 / 80.52.25 mA2.54 mA2.88 mA
4 / 812.87 mA3.25 mA3.64 mA
823.88 mA4.46 mA4.95 mA
(MHz)IDD at V
CPU
(SLOW Mode) at TA = + 25 °C
DD
= 4.5 VIDD at V
DD
= 5 VIDD at V
DD
DD
= 5.5 V
6.1.2.3 Wait Mode
Methodology: A resonator oscillator is used with f
is f
/2. All peripherals are in reset configuration except the ports. So, the SMS bit in the
osc
at 4 / 8 MHz. PLL*2 is disabled. So, f
osc
MCCSR is reset to 0. The CP1 and CP0 bits in the MCCSR are also reset to 0 and hence f
is f
8/25
. All ports are set as Push-Pull Outputs with low level.
osc2
osc2
CPU
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