ST AN1009 Application note

AN1009

APPLICATION NOTE

“Negative Undershoot” NVRAM Data Corruption

Miniaturisation in microelectronics has led, inevitably, to the inadvertent appearance of parasitic devices.
Adjacent conducting paths end up being separated by a gap that is so narrow that it ceases to isolate them
properly from each ot her. Parasitic tunnelling devices, bipolar t ransistors, and thyristors end up be ing
formed, with each one causing its own distinctive misbehaviour.

The occurrence of parasitic SCRs (silicon controlled rectifiers) causes the well-studied problem of latch­up. The occurrence of parasitic bipolar transistors, such as t he one shown in Figure 1, is normally less
serious, but leads to a particular type o f problem in battery-powe red circuits . It is this probl em th at is ad­dressed in this document.

The problem manifests itself in battery-powered memory as data corruption: the unintentional flipping from
1 to 0, or from 0 to 1, of bits of data in the memory array. It is caused when a negative pulse is inadvertently
applied to the emitter of an inadvertently formed parasitic bipolar transistor, causing it to go into conduction
mode, and to connect two otherwise isolated signal lines.

ANATOMY OF A PARASITIC BIPOLAR TRANSISTOR

Figure 1 shows the cross sec tion o f a CM OS gate, with one MOS FET formed directly in the N-type sub­strate, and the other in a P-well. Under certain cond itions, the P-wel l can s tart to beh ave as the bas e re­gion of a parasitic bipolar NPN transistor, with the N-type sub strate as its collector region, and the N+
diffusion contact of the MOSFET as its emitter region.

Figure 1. Cross-Section of an NPN Parasitic Bipolar Transistor

GROUNDED
P-WELL

N-SUBSTRATE

VCC

GATE

PAD

(NEGATIVE PULSE)

P+ N+P+N+

VSS

GATE

P+N+

GROUNDED P-WELL

INTERNAL POWER

SUBSTRATE

VCC

N+

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AN1009 - APPLICATION NOTE

The P-well is held at groun d, so t he p aras itic NPN t ransistor should nev er turn on. If, though, a negative
pulse is applied to the pad, a nd hence to the emitter of t he p aras itic NPN t ransisto r, the transistor wo uld
be put into its conducting mode. Once the pad is taken to -V
and pulls current from the substrate.

When the memory device is being powered by the external power source, the effect of this extra parasitic
current will be neglig ible, and will b e com pensated fo r by the ex ternal power sour ce. Whe n the me mory
device is being powered from the internal battery, though, the battery is unable to compensate for the extra
current, and so the supply voltage will fall. As soon as the supply voltage falls below a crit ical value, SRAM
cells in the memory array will cease to hold their stored data reliably.

The parasitic bipolar transistor starts to turn on when the pad is taken to about -0.6 V. In battery mode, the
impact on the substrate will start to be felt once the current drain through the bipolar transistor is approx­imately -0.6 mA. The substrat e will be pulled to approximately 1.0 V once the current through the bipolar
transistor reaches -1.5 mA. As the magnitude of the negative current increases, it directly reduces the lev­el of internal V

(the substrate voltage). A current drain of approximately -2.0 mA will bring internal V

CC

to ground, thus leaving the SRAM array completely unpowered.

, the parasitic bipolar transistor turns on,

be

CC

Figure 2. Substrate V

versus Negative Undershoots

CC

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4V

Substrate V

not

trig'd

M

C1

-1V

-420ns 3.85µs

Negative Undershoot

CC

-1.2 volts for 100ns

-1.2 volts for 500ns

-1.2 volts for 1µs

400ns

500mV

Figure 2 superimposes three pa irs of curves : three negat ive und ersh oot pulses of 100, 500 and 1000 ns
duration; and the corresponding effects that are felt by the V

substrate voltage.

CC

Thus, we see that the effect on the substrate voltage is proportional to the duration of the negative under­shoot pulse. It is also proportional to its magnitude (its amplitude). It is also proportional to the number of
pins that receive the negative undershoot pulse (t he example, above, is the effect of just one pin on the
chip going negative).

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