ST A7985A User Manual

2 A step-down switching regulator for automotive applications

Features

■ 2 A DC output current

■ Qualified following AEC-Q100 requirements

(see PPAP for more details)

■ 4.5 V to 38 V input voltage

■ Output voltage adjustable from 0.6 V

■ 250 kHz switching frequency, programmable

up to 1 MHz

■ Internal soft-start and enable

■ Low dropout operation: 100% duty cycle

■ Voltage feed-forward

■ Zero load current operation

■ Overcurrent and thermal protection

■ HSOP8 package

Applications

■ Dedicated to automotive applications

■ Automotive LED driving

A7985A

Datasheet − preliminary data

HSOP8 exposed pad

Description

The A7985A is a step-down switching regulator
with a 2.5 A (minimum) current limited embedded
power MOSFET, so it is able to deliver up to 2 A
current to the load depending on the application
conditions.

The input voltage can range from 4.5 V to 38 V,
while the output voltage can be set starting from

0.6 V to V

Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.

.

IN

The HSOP package with exposed pad allows the
reduction of R

down to 40 °C/W.

thJA

Figure 1. Application circuit

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April 2012 Doc ID 023128 Rev 1 1/45

This is preliminar y information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

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45

Contents A7985A

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2/45 Doc ID 023128 Rev 1

A7985A Contents

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Doc ID 023128 Rev 1 3/45

List of tables A7985A

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Input MLCC capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. HSOP8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 11. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4/45 Doc ID 023128 Rev 1

A7985A List of figures

List of figures

Figure 1. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization . . . . . . . . . . . . . 12

Figure 6. Oscillator frequency versus the FSW pin resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. Soft-start scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. The error amplifier, the PWM modulator and the LC output filter . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Type III compensation network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. Open loop gain Bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . 25

Figure 13. Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14. Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor . . . . . . . . . . . . . 29

Figure 16. Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 18. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 19. PCB layout: A7985A (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 20. PCB layout: A7985A (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 21. PCB layout: A7985A (front side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 22. Junction temperature vs. output current @ V
Figure 23. Junction temperature vs. output current @ V
Figure 24. Junction temperature vs. output current @ V
Figure 25. Efficiency vs. output current @ V
Figure 26. Efficiency vs. output current@ V
Figure 27. Efficiency vs. output current@ V

= 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

o

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

o

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

o

Figure 28. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 29. Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 30. Load transient: from 0.4 A to 2 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 31. Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 32. Short-circuit behavior @ VIN=12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 33. Short-circuit behavior @ VIN=24 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 34. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 35. Maximum output current according to max. DC switch current (2.0 A): VO=12 V . . . . . . . 38

Figure 36. Inverting buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 37. Maximum output current according to switch max. peak current (2.0 A): VO=-5 V . . . . . . 40

Figure 38. Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

= 24 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

IN

= 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

IN

= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

IN

Doc ID 023128 Rev 1 5/45

Pin settings A7985A

1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

1.2 Pin description

Table 1. Pin description

N. Type Description

1 OUT Regulator output

Master/slave synchronization. When it is left floating, a signal with a
phase shift of half a period in respect to the power turn-on is present at
the pin. When connected to an external signal at a frequency higher than

2 SYNCH

3EN

4 COMP Error amplifier output to be used for loop frequency compensation

5FB

6FSW

7 GND Ground

8V

CC

the internal one, the device is synchronized by the external signal, with
zero phase shift.

Connecting together the SYNCH pins of two devices, the one with the
higher frequency works as master and the other as slave; so the two
power turn-ons have a phase shift of half a period.

A logical signal (active high) enables the device. With EN higher than

1.2 V the device is ON and with EN lower than 0.63 V the device is OFF.

Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from Vout to the FB pin.

The switching frequency can be increased connecting an external
resistor from the FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 KHz.

Unregulated DC input voltage

6/45 Doc ID 023128 Rev 1

A7985A Maximum ratings

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

Vcc Input voltage 45

OUT Output DC voltage -0.3 to V

FSW, COMP, SYNCH Analog pin -0.3 to 4

EN Enable pin -0.3 to V

FB Feedback voltage -0.3 to 1.5

P

TOT

T

J

T

stg

3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

R

thJA

1. Package mounted on demonstration board.

Maximum thermal resistance
junction-ambient

CC

V

CC

Power dissipation

< 60 °C

at T

A

HSOP 2 W

Junction temperature range -40 to 150 °C

Storage temperature range -55 to 150 °C

(1)

HSOP8 40 °C/W

Doc ID 023128 Rev 1 7/45

Electrical characteristics A7985A

4 Electrical characteristics

TJ=-40 °C to 125 °C, VCC=12 V, unless otherwise specified.

Table 4. Electrical characteristics

Values

Symbol Parameter Test condition

Min. Typ. Max.

Unit

V

V

CCON

V

CCHYS

R

DSON

I

LIM

CC

Operating input voltage
range

4.5 38

Tur n - on VCC threshold 4.5

VCC UVLO hysteresis 0.1 0.4

MOSFET ON­resistance

Maximum limiting
current

2.5 3.5 A

200 400 mΩ

Oscillator

Switching frequency 210 250 275 kHz

FSW pin voltage 1.254 V

V

F

FSW

SW

D Duty cycle 0 100 %

F

ADJ

Adjustable switching
frequency

R

= 33 kΩ 1000 kHz

FSW

Dynamic characteristics

V

FB

Feedback voltage 4.5 V < V

< 38 V 0.582 0.6 0.618 V

CC

DC characteristics

I

Q

I

QST-BY

Quiescent current Duty cycle = 0, V

Total standby quiescent
current

= 0.8 V 2.4 mA

FB

20 30 µA

V

Enable

Device OFF level 0.3

V

EN

I

EN

EN threshold voltage

Device ON level 1.2

EN current EN = V

CC

Soft-start

FSW pin floating 7.3 8.2 9.8

T

SS

Soft-start duration

F
R

SW

FSW

=1 MHz,

= 33 kΩ

Error amplifier

8/45 Doc ID 023128 Rev 1

V

7.5 10 µA

ms

2

A7985A Electrical characteristics

Table 4. Electrical characteristics (continued)

Values

Symbol Parameter Test condition

Min. Typ. Max.

Unit

V

CH

V

CL

I

O SOURCE

I

O SINK

G

High level output
voltage

Low level output voltage V

Source COMP pin V

Sink COMP pin V

Open loop voltage gain

V

Synchronization function

V

S_IN,HI

V

S_IN,LO

t

S_IN_PW

I

SYNCH,LO

V

S_OUT,HI

t

S_OUT_PW

High input voltage 2 3.3

Low input voltage 1

Input pulse width

Slave sink current V

Master output amplitude I

Output pulse width SYNCH floating 110 ns

Protection

Thermal shutdown 150

T

SHDN

Hysteresis 30

< 0.6 V 3

V

FB

> 0.6 V 0.1

FB

= 0.5 V, V

FB

= 0.7 V, V

FB

(1)

V

S_IN,HI

V

S_IN,HI

SYNCH

SOURCE

= 3 V, V

= 2 V, V

= 2.9 V 0.7 1 mA

= 4.5 mA 2 V

= 1 V 19 mA

COMP

= 0.75 V 30 mA

COMP

100 dB

= 0 V 100

S_IN,LO

= 1 V 300

S_IN,LO

V

V

ns

°C

1. Guaranteed by design.

Doc ID 023128 Rev 1 9/45

Functional description A7985A

5 Functional description

The A7985A is based on a “voltage mode”, constant frequency control. The output voltage

is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing

V

OUT

an error signal that, compared to a fixed frequency sawtooth, controls the ON and OFF time
of the power switch.

The main internal blocks are shown in the block diagram in Figure 3. They are:

● A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the

synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed-forward are implemented

● Soft-start circuitry to limit inrush current during the startup phase

● Voltage mode error amplifier

● Pulse width modulator and the relative logic circuitry necessary to drive the internal

power switch

● High-side driver for embedded P-channel power MOSFET switch

● Peak current limit sensing block, to handle overload and short-circuit conditions

● A voltage regulator and internal reference. It supplies internal circuitry and provides a

fixed internal reference

● A voltage monitor circuitry (UVLO) that checks the input and internal voltages

● A thermal shutdown block, to prevent thermal run-away.

Figure 3. Block diagram

TRIMMING UVLO

TRIMMING UVLOUVLO

EN

EN

COMP

COMP

0.6V

0.6V

SOFT-

SOFT-

START

START

EN

EN

FB

FB

REGULATOR

REGULATOR

REGULATOR

&

&

&

BANDGAP

BANDGAP

BANDGAP

1.254V 3.3V

1.254V 3.3V

THERMAL

THERMAL

SHUTDOWN

SHUTDOWN

E/A

E/A

OSCILLATOR

OSCILLATOR

FSW

FSW

PWM

PWM

GND

GND

PEAK

PEAK

CURRENT

CURRENT

LIMIT

LIMIT

SRQ

SRQ

SYNCH

SYNCH

&

&

PHASE SHIFT

PHASE SHIFT

SYNCH

SYNCH

DRIVER

DRIVER

VCC

VCC

OUT

OUT

10/45 Doc ID 023128 Rev 1

A7985A Functional description

5.1 Oscillator and synchronization

Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a

constant frequency clock. Its frequency depends on the resistor externally connected to the
FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as
shown in Figure 6 by an external resistor connected to ground.

To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).

The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way, a frequency feed-forward is implemented (Figure 5.b) in order
to keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM
gain expression).

On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with the
higher oscillator frequency works as master, so the slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor (see the L5988D datasheet).

Figure 4. Oscillator circuit block diagram

Clock

ClockClock

FSW

FSW

The device can be synchronized to work at a higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This change must be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free-running frequency should be set (with a
resistor on the FSW pin) only slightly lower than the external clock frequency. This pre­adjusting of the frequency changes the sawtooth slope in order to render negligible the
truncation of sawtooth, due to the external synchronization.

Clock

Clock

Generator

Generator

Synchronization

Synchronization

Ramp

Ramp

Generator

Generator

SYNCH

SYNCH

Sawtooth

Sawtooth

Doc ID 023128 Rev 1 11/45

Functional description A7985A

Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization

Figure 6. Oscillator frequency versus the FSW pin resistor

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12/45 Doc ID 023128 Rev 1

;K/HMS=

A7985A Functional description

where:

3

⋅–=

desired switching frequency.

F

SW

R

FSW

250 103⋅–

F

SW

28.5 109⋅

--------------------------------------------- 3.23 10

5.2 Soft-start

Soft-start is essential to assure the correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monothonically.

The soft-start is performed by a staircase ramp on the non-inverting input (V

) of the error

REF

amplifier. So the output voltage slew rate is:

Equation 1

VREF

⎛⎞

1

------- -+

⋅=

⎝⎠

R2

where SR

OUT

SR

SR

is the slew rate of the non-inverting input, while R1and R2 is the resistor

VREF

R1

divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64
steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So
the soft-start time and then the output voltage slew rate depend on the switching frequency.

Figure 7. Soft-start scheme

Soft-start time results:

Equation 2

SS

TIME

32 64⋅

--------------------=

Fsw

For example, with a switching frequency of 250 kHz, the SS

Doc ID 023128 Rev 1 13/45

TIME

is 8 ms.

Functional description A7985A

5.3 Error amplifier and compensation

The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier, so with high DC gain and low output impedance.

The uncompensated error amplifier characteristics are shown in Ta bl e 5 .

Table 5. Uncompensated error amplifier characteristics

Parameter Value

Low frequency gain 100 dB

GBWP 4.5 MHz

Slew rate 7 V/µs

Output voltage swing 0 to 3.3 V

Maximum source/sink current 17 mA/25 mA

In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter, a Type II compensation network can be used. Otherwise, a Type
III compensation network must be used (see Section 6.4 for details of the compensation
network selection).

The methodology to compensate the loop is to introduce zeroes to obtain a safe phase
margin.

5.4 Overcurrent protection

The A7985A implements the overcurrent protection sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.

If the overcurrent limit is reached, the power MOSFET is turned off, implementing the pulse­by-pulse overcurrent protection. Under an overcurrent condition, the device can skip turn-on
pulses in order to keep the output current constant and equal to the current limit. If, at the
end of the “masking time”, the current is higher than the overcurrent threshold, the power
MOSFET is turned off and one pulse is skipped. If, at the following switching-on, when the
“masking time” ends, the current is still higher than the overcurrent threshold, the device
skips two pulses. This mechanism is repeated and the device can skip up to seven pulses.
While, if at the end of the “masking time” the current is lower than the over current threshold,
the number of skipped cycles is decreased by one unit (see Figure 8).

So the overcurrent/short-circuit protection acts by switching off the power MOSFET and
reducing the switching frequency down to one eighth of the default switching frequency, in
order to keep constant the output current around the current limit.

14/45 Doc ID 023128 Rev 1

A7985A Functional description

This kind of overcurrent protection is effective if the output current is limited. To prevent the
current from diverging, the current ripple in the inductor during the ON-time must not be
higher than the current ripple during the OFF-time. That is:

Equation 3

VINV–

----------------------------------------------------------- ------------------------------------------------------------- -

If the output voltage is shorted, V

OUT

R

⋅ DCR I

DSONIOUT

LF

⋅

SW

⋅––

OUT

OUT

D⋅

≅ 0, I

V

OUTVFRDSONIOUT

------------------------------------------------------------- ----------------------------------------------------------

OUT=ILIM

, D/FSW=T

⋅ DCR I

⋅

LF

SW

ON_MIN

, (1-D)/FSW≅ 1/FSW. So

⋅++ +

OUT

1D–()⋅=

from the above equation the maximum switching frequency that guarantees to limit the
current results:

Equation 4

VFDCR I⋅+

With R

*

F

SW

=300 mΩ, DRC=0.08 Ω, the worst condition is with VIN=38 V, I

DS(on)

()

--------------------------------------------------------------- ----------------------

V

INRDSON

LIM

DCR+()I

⋅–()

LIM

------------------------ -

⋅=

T

ON_MIN

1

=2.5 A; the

LIM

maximum frequency to keep the output current limited during the short-circuit results
74 kHz.

Based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one
eighth, the maximum F

, adjusted by the FSW pin, that assures a full effective output

SW

current limitation is 74 kHz*8 = 592 kHz.

If, with V

=38 V, the switching frequency is set higher than 592 kHz, during short-circuit

IN

condition the system finds a different equilibrium with higher current. For example, with
F

=700 kHz and the output shorted to ground, the output current is limited around:

SW

Equation 5

where F

SW

VINF

I

OUT

--------------------------------------------------------- ------------------------------------------------------------------ 3.68A==

DRC T

⋅ VFT

⁄()R

ON_MIN

* is 700 kHz divided by eight.

Doc ID 023128 Rev 1 15/45

*

SW

⁄–

DSON

ON_MIN

DCR+()F

*

⋅+

SW

Functional description A7985A

Figure 8. Overcurrent protection

5.5 Enable function

The enable feature allows the device to be put into stand-by mode. With the EN pin lower
than 0.3 V, the device is disabled and the power consumption is reduced to less than 30 µA.
With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an
internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also V

compatible.

CC

5.6 Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.

16/45 Doc ID 023128 Rev 1

A7985A Application information

6 Application information

6.1 Input capacitor selection

The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.

So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 6

2

2D

I

RMSIO

⋅

D

----------------- -–

where Io is the maximum DC output current, D is the duty cycle, η is the efficiency.
Considering η=1, this function has a maximum at D=0.5 and it is equal to Io/2.

2

D

------ -+⋅=

2

η

η

In a specific application the range of possible duty cycles must be considered in order to find
out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:

Equation 7

V

+

OUTVF

MAX

---------------------------------------=
–

V

INMINVSW

D

and

Equation 8

V

+

OUTVF

-----------------------------------------=

V

–

INMAXVSW

where V

D

MIN

is the forward voltage on the freewheeling diode and VSW is voltage drop across

F

the internal PDMOS.

The peak-to-peak voltage across the input capacitor can be calculated as:

Equation 9

V

PP

I

O

------------------------------

CINFSW⋅

D

⎛⎞

--- -–

1

⎝⎠

η

D

--- -

D

1D–()⋅+⋅ ESR I

η

⋅+⋅=

O

where ESR is the equivalent series resistance of the capacitor.

Doc ID 023128 Rev 1 17/45

Application information A7985A

Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic/tantalum types. In this
case, the equation of C

as a function of the target VPP can be written as follows:

IN

Equation 10

C

IN

I

O

-------------------------------

V

⋅

PPFSW

D

⎛⎞

--- -–

1

⎝⎠

η

D

--- -

D

1D–()⋅+⋅⋅=

η

neglecting the small ESR of ceramic capacitors.
Considering η=1, this function has its maximum in D=0.5, therefore, given the maximum

peak-to-peak input voltage (V

PP_MAX

), the minimum input capacitor (C

IN_MIN

) value is:

Equation 11

I

O

PP_MAXFSW

Ty p i ca l l y, C
of V

INMAX

C

IN_MIN

is dimensioned to keep the maximum peak-to-peak voltage in the order of 1%

IN

-------------------------------------------------------- -=

2V

⋅⋅

.

In Figure 6, some multi-layer ceramic capacitors suitable for this device are reported.

Table 6. Input MLCC capacitors

Manufacturer Series Cap value (µF) Rated voltage (V)

Taiyo Yuden

UMK325BJ106MM-T 10 50

GMK325BJ106MN-T 10 35

muRata GRM32ER71H475K 4.7 50

A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that
additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability
on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.

6.2 Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple must be selected.
The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.

In continuous current mode (CCM), the inductance value can be calculated by the following
equation:

18/45 Doc ID 023128 Rev 1

A7985A Application information

Equation 12

VINV

∆I

L

–

OUT

------------------------------- -

L

⋅

T

ON

+

V

OUTVF

-----------------------------

L

⋅==

T

OFF

where T
time of the external diode (in CCM, F
fixed V
section to calculate minimum duty). So by fixing ∆I

is the conduction time of the internal high-side switch and T

ON

, is obtained at maximum T

OUT

=1/(TON + T

SW

, that is at minimum duty cycle (see previous

OFF

)). The maximum current ripple, at

OFF

=20% to 30% of the maximum output

L

current, the minimum inductance value can be calculated:

Equation 13

1D

+

------------------------

⋅=

OFF

–

MIN

F

SW

).

where F

is the switching frequency, 1/(TON + T

SW

For example, for V
value to have ∆I

L

V

OUTVF

MIN

-----------------------------

∆I

MAX

L

=5 V, VIN=24 V, IO=2 A and FSW=250 kHz, the minimum inductance

OUT

=30% of IO is about 28 µH.

The peak current through the inductor is given by:

Equation 14

∆I

L

I

I

LPK,

--------+=

O

2

is the conduction

OFF

So if the inductor value decreases, then the peak current (that must be lower than the
minimum current limit of the device) increases. According to the maximum DC output
current for this product family (2 A), the higher the inductor value, the higher the average
output current that can be delivered, without triggering the overcurrent protection.

In Ta ble 7 below, some inductor part numbers are listed.

Table 7. Inductors

Manufacturer Series Inductor value (µH) Saturation current (A)

Coilcraft

Wurth

SUMIDA

MSS1038 3.8 to 10 3.9 to 6.5

MSS1048 12 to 22 3.84 to 5.34

PD Type L 8.2 to 15 3.75 to 6.25

PD Type M 2.2 to 4.7 4 to 6

CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2

CDR10D48MN 6.6 to 12 4.1 to 5.7

Doc ID 023128 Rev 1 19/45

Application information A7985A

6.3 Output capacitor selection

The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.

The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.

Equation 15

∆I

∆V

OUT

ESR ∆I

⋅

MAX

Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR
value.

The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Section 6.4, how to consider its effect in the system stability is
illustrated.

MAX

---------------------------------------------+=

8C

⋅⋅

OUTfSW

For example, with V
to have a ∆V

OUT

=0.01·V

=5 V, VIN=24 V, ∆IL=0.9 A (resulting by the inductor value), in order

OUT

, if the multi-layer ceramic capacitors are adopted, 10 µF are

OUT

needed and the ESR effect on the output voltage ripple can be neglected. In case of not­negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value. So, in the case of 330 µF with ESR=70 mΩ, the resistive component
of the drop dominates and the voltage ripple is 43 mV.

The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application, the output capacitor and system bandwidth
must be chosen in order to sustain the load transient.

In Ta ble 8 below some capacitor series are listed.

Table 8. Output capacitors

Manufacturer Series Cap value (µF) Rated voltage (V) ESR (mΩ)

muRata

PANASONIC

SANYO TPA/B/C 100 to 470 4 to 16 40 to 80

TDK C3225 22 to 100 6.3 < 5

GRM32 22 to 100 6.3 to 25 < 5

GRM31 10 to 47 6.3 to 25 < 5

ECJ 10 to 22 6.3 < 5

EEFCD 10 to 68 6.3 15 to 55

20/45 Doc ID 023128 Rev 1

A7985A Application information

6.4 Compensation network

The compensation network must assure stability and good dynamic performance. The loop
of the A7985A is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So by selecting the compensation network the
E/A is considered as ideal, that is, its bandwidth is much larger than the system one.

The transfer functions of the PWM modulator and the output LC filter are studied (see

Figure 10). The transfer function of the PWM modulator, from the error amplifier output

(COMP pin) to the OUT pin, results:

Equation 16

V

G

PW0

IN

---------=

V

s

where V

is the sawtooth amplitude. As seen in Section 5.1, the voltage feed-forward

S

generates a sawtooth amplitude directly proportional to the input voltage, that is:

Equation 17

V

KV

⋅=

S

IN

In this way the PWM modulator gain results constant and equal to:

Equation 18

V

1

IN

G

PW0

---------

V

s

--- - 18===
K

The synchronization of the device with an external clock provided through the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).

Figure 9. The error amplifier, the PWM modulator and the LC output filter

V

V

CC

CC

V

V

FB

FB

REF

REF

E/A

E/A

V

V

S

S

COMP

COMP

PWM

PWM

L

OUT

OUT

G

G

PW0

PW0

Doc ID 023128 Rev 1 21/45

L

ESR

ESR

G

G

LC

LC

C

C

OUT

OUT

Application information A7985A

The transfer function on the LC filter is given by:

Equation 19

GLCs()

1

-------------------------------------------------------------- ---------------------=

++

1

---------------------------------- -

2π Qf⋅

⋅

s

s

------------------------------+

2π f

⋅

zESR

⎛⎞

---------------------- -

⎝⎠

2π f

LC

2

s

⋅

LC

where:

Equation 20

------------------------------------------------------- --------------------------- -= f

f

LC

2π LC

1

⋅ 1

OUT

ESR

----------------+⋅⋅

R

OUT

zESR

---------------------------------------------------=,

2π ESR C

1

⋅⋅

OUT

Equation 21

R

-------------------------------------------------------- ---------------------------------------------- -

Q

OUT

LC

LC

OUTROUT

OUTROUT

ESR+()⋅⋅ ⋅

ESR⋅⋅+

R

OUT

V

--------------- -=,=

I

OUT

OUT

As seen in Section 5.3, two different kinds of network can compensate the loop. In the two
following paragraphs the guidelines to select the Type II and Type III compensation network
are illustrated.

6.4.1 Type III compensation network

The methodology to stabilize the loop consists in placing two zeroes to compensate the
effect of the LC double pole, thereby increasing phase margin; then to place one pole in the
origin to minimize the DC error on the regulated output voltage; finally to place other poles
far from the zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the Type III
compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (<1 mΩ), with very high frequency zero, so a Type III network is adopted to compensate
the loop.

In Figure 10, the Type III compensation network is shown. This network introduces two
zeroes (f

Equation 22

22/45 Doc ID 023128 Rev 1

, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:

Z1

f

-------------------------------------------------------= f

Z1

2π C

1

+()⋅⋅

3R1R3

Z2

------------------------------------=,

2π R

⋅⋅

1

4C4

A7985A Application information

Equation 23

fP00= f

1

------------------------------------= f

P1

⋅⋅

2π R

3C3

---------------------------------------------------=,,

P2

2π R

1

C4C5⋅

--------------------- -

⋅⋅

4

C

+

4C5

Figure 10. Type III compensation network

In Figure 11 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G

LOOP

(f)=G

· GLC(f) · G

PW0

(f)) are drawn.

TYPEIII

PW0

· GLC(f))

Figure 11. Open loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:

1. Choose a value for R

2. Choose a gain (R

, usually between 1 kΩ and 5 kΩ.

1

) in order to have the required bandwidth (BW), that means:

4/R1

Doc ID 023128 Rev 1 23/45

Application information A7985A

Equation 24

BW

--------- -

R

4

f

LC

⋅⋅=

KR

1

where K is the feed-forward constant and 1/K is equal to 18.

3. Calculate C

by placing the zero at 50% of the output filter double pole frequency (fLC):

4

Equation 25

1

--------------------------------- -=

π R

⋅⋅

4fLC

4. Calculate C

C

4

by placing the second pole at four times the system bandwidth (BW):

5

Equation 26

C

--------------------------------------------------------------- ----------=

C

5

2π R4C44BW⋅ 1–⋅⋅⋅

4

5. Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:

Equation 27

R

R

3

1

------------------------------= C
4BW⋅

-------------------- 1–
f

LC

3

-------------------------------------------------=,

2π R

3

1

4BW⋅⋅⋅

The suggested maximum system bandwidth is equal to the switching frequency divided by

3.5 (F

For example, with V

/3.5), so lower than 100 kHz if the FSW is set higher than 500 kHz.

SW

=5 V, VIN=24 V, IO=2 A, L=22 µH, C

OUT

=22 µF, and ESR<1 mΩ, the

OUT

Type III compensation network is:

Equation 28

4.99k Ω= R2680Ω= R3270Ω= R41.1k Ω= C34.7nF= C447nF= C51pF=,,,, ,,

R

1

In Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about
32 kHz and the phase margin is 51°.

24/45 Doc ID 023128 Rev 1

A7985A Application information

Figure 12. Open loop gain Bode diagram with ceramic output capacitor

Doc ID 023128 Rev 1 25/45

Application information A7985A

6.4.2 Type II compensation network

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency lower than the desired bandwidth (that is: 2π∗ESR∗COUT>1/BW), this zero helps
stabilize the loop. Electrolytic capacitors show not-negligible ESR (>30 mΩ), so with this kind
of output capacitor the Type II network combined with the zero of the ESR allows the
stabilizing of the loop.

In Figure 13 the Type II network is shown.

Figure 13. Type II compensation network

The singularities of the network are:

------------------------------------= f

f

Z1

2π R

⋅⋅

1

4C4

P0

0= f

P1

---------------------------------------------------=,,

2π R

1

C4C5⋅

--------------------- -

⋅⋅

4

C

+

4C5

In Figure 14 the Bode diagram of the PWM and LC filter transfer function (G
and the open loop gain (G

LOOP

(f)=G

· GLC(f) · G

PW0

(f)) are drawn.

TYPEII

PW0

· GLC(f))

26/45 Doc ID 023128 Rev 1

A7985A Application information

Figure 14. Open loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:

1. Choose a value for R

, usually between 1 kΩ and 5 kΩ, in order to have values of C4

1

and C5 not comparable with parasitic capacitance of the board.

2. Choose a gain (R

) in order to have the required bandwidth (BW), that means:

4/R1

Equation 29

where f

is the ESR zero:

ESR

R

4

2

f

⎛⎞

ESR

-------------

⎜⎟
⎝⎠

⋅⋅⋅=

f

LC

BW

-------------

f

ESR

V

---------

V

S

R

1

IN

Equation 30

f

ESR

---------------------------------------------------=

2π ESR C

1

⋅⋅

OUT

and Vs is the sawtooth amplitude. The voltage feed-forward keeps the ratio V

3. Calculate C

by placing the zero one decade below the output filter double pole:

4

Equation 31

10

-------------------------------------=

C

4

2π R

⋅⋅

4fLC

4. Then calculate C

in order to place the second pole at four times the system bandwidth

3

(BW):

S/VIN

constant.

Doc ID 023128 Rev 1 27/45

Application information A7985A

Equation 32

C

--------------------------------------------------------------- ----------=

C

5

2π R4C44BW⋅ 1–⋅⋅⋅

4

For example, with V

=5 V, VIN=24 V, IO=2 A, L=22 µH, C

OUT

=330 µF, and ESR=70 mΩ,

OUT

the Type II compensation network is:

Equation 33

R

1.1kΩ= R2150Ω= R44.99k Ω= C4180nF= C5180pF=,, , ,

1

In Figure 15 the module and phase of the open loop gain is shown. The bandwidth is about
36 kHz and the phase margin is 53°.

28/45 Doc ID 023128 Rev 1

A7985A Application information

Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor

Doc ID 023128 Rev 1 29/45

Application information A7985A

6.5 Thermal considerations

The thermal design is important to prevent the thermal shutdown of the device if the junction
temperature goes above 150 °C. The three different sources of losses within the device are:

a) conduction losses due to the not-negligible R

equal to:

Equation 34

of the power switch; these are

DS(on)

P

ONRDSONIOUT

where D is the duty cycle of the application and the maximum R
220 mΩ. Note that the duty cycle is theoretically given by the ratio between V

()2D⋅⋅=

overtemperature is

DS(on)

OUT

and VIN,
but actually it is quite higher to compensate the losses of the regulator. So the conduction
losses increase compared with the ideal case.

b) switching losses due to power MOSFET turn-on and turn-off; these can be

calculated as:

Equation 35

T

+()

RISETFALL

where T

RISE

P

SWVINIOUT

and T

FALL

----------------------------------------------

2

Fsw⋅⋅ ⋅ V

are the overlap times of the voltage across the power switch (VDS)

⋅⋅⋅==

INIOUTTSWFSW

and the current flowing into it during turn-on and turn-off phases, as shown in Figure 16.
T

is the equivalent switching time. For this device the typical value for the equivalent

SW

switching time is 40 ns.

c) Quiescent current losses, calculated as:

Equation 36

P

QVINIQ

where I

The junction temperature T

is the quiescent current (IQ=2.4 mA).

Q

can be calculated as:

J

Equation 37

T

JTA

where T

R

thJA

is the ambient temperature and P

A

is the equivalent thermal resistance junction to ambient of the device; it can be

RthJAP

is the sum of the power losses just seen.

TOT

calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount

30/45 Doc ID 023128 Rev 1

⋅=

⋅+=

TOT

A7985A Application information

of heat. The RthJA measured on the demonstration board described in the following
paragraph is about 40 °C/W for the HSOP package.

Figure 16. Switching losses

6.6 Layout considerations

The PC board layout of the switching DC/DC regulator is very important to minimize the
noise injected in high impedance nodes and interference generated by the high switching
current loops.

In a step-down converter, the input loop (including the input capacitor, the power MOSFET
and the freewheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as
short as possible.

The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so the interference can be minimized by placing the routing of the feedback node as far as
possible from the high current paths. To reduce the pick-up noise, the resistor divider must
be placed very close to the device.

To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as
close as possible to the input voltage pin of the device.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.

In Figure 17 a layout example is shown.

Doc ID 023128 Rev 1 31/45

Application information A7985A

Figure 17. Layout example

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A7985A Application information

6.7 Application circuit

In Figure 18 the demonstration board application circuit is shown.

Figure 18. Demonstration board application circuit

Table 9. Component list

Reference Part number Description Manufacturer

C1 UMK325BJ106MM-T 10 µF, 50 V Taiyo Yuden

C2 GRM32ER61E226KE15 22 µF, 25 V muRata

C3 3.3 nF, 50 V

C4 33 nF, 50 V

C5 100 pF, 50 V

C6 470 nF, 50 V

R1 4.99 kΩ, 1%, 0.1 W 0603

R2 1.1 kΩ, 1%, 0.1 W 0603

R3 330 Ω, 1%, 0.1 W 0603

R4 1.5 kΩ, 1%, 0.1 W 0603

R5 150 kΩ, 1%, 0.1 W 0603

D1 STPS3L40 3 A DC, 40 V STMicroelectronics

L1 MSS1038-103NL

10 µH, 30%, 3.9 A,

DCR

MAX

=35 mΩ

Coilcraft

Doc ID 023128 Rev 1 33/45

Application information A7985A

Figure 19. PCB layout: A7985A (component side)

Figure 20. PCB layout: A7985A (bottom side)

Figure 21. PCB layout: A7985A (front side)

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A7985A Application information

Figure 22. Junction temperature vs. output

current @ V

V

=5V

OUT

V

=3.3V

OUT

V

=1.8V

OUT

HSOPVQFN

= 24 V

IN

VIN=24V

=250KHz

F

SW

T

=25 C

AMB

Figure 24. Junction temperature vs. output

V

=3.3V

OUT

V

=1.8V

OUT

V

=1.2V

OUT

VIN=5V

=250KHz

F

SW

T

AMB

=25 C

current @ V

HSOPVQFN

= 5 V

IN

Figure 23. Junction temperature vs. output

current @ VIN= 12 V

HSOPVQFN

V

=5V

OUT

V

=3.3V

OUT

V

=1.8V

OUT

VIN=12V
F

=250KHz

SW

=25 C

T

AMB

Figure 25. Efficiency vs. output current @

Vo= 1.8 V

85

80

75

70

65

60

Eff [%]

55

50

45

40

0.100 0.600 1.100 1.600 2.100

Io [A]

Vo=1.8V
FSW=250k Hz

Vin=5V

Vin=12V

Vin=24V

Figure 26. Efficiency vs. output current@

V

=5 V

95

90

85

80

Eff [%]

75

70

65

60

0.100 0.600 1.100 1.600 2.100

o

Vo=5.0V
FSW=250kHz

Vin=12V

Vin=18V

Vin=24V

Io [A]

Doc ID 023128 Rev 1 35/45

Figure 27. Efficiency vs. output current@

Vo= 3.3 V

95

90

85

80

75

70

Eff [%]

65

60

55

50

0.100 0.600 1.100 1.600 2.100

Io [A]

Vo=3.3V
FSW=250kHz

Vin=5V

Vin=12V

Vin=24V

Application information A7985A

Figure 28. Load regulation Figure 29. Line regulation

3.345

3.340

3.335

3.330

[V]

OUT

V

3.325

3.320

3.315

3.310

Figure 30. Load transient: from 0.4 A to 2 A Figure 31. Soft-start

V

V

OUT

OUT

100mV/div

100mV/div
AC coupled

AC coupled

Vin=5V

Vin=12V

Vin=24V

0.00 0.50 1.00 1.50 2.00

Io [A]

3.3500

3.3450

3.3400

[V]

3.3350

OUT

V

3.3300

3.3250

3.3200

5.0 10. 0 15.0 20.0 25.0 30.0 35. 0 40.0

I

L

500mA/div

VIN[V]

Io= 1A

Io= 2A

V

OUT

500mV/div

V

V

=24V

=24V

IN

IN

=3.3V

=3.3V

V

V

OUT

I

I

500mA/div

500mA/div

L

L

OUT

=47uF

=47uF

C

C

OUT

OUT

L=10uH

L=10uH

=520k

=520k

F

F

SW

SW

V

FB

200mV/div

Time base 1ms/div

Time base 100us/div

Time base 100us/div

Figure 32. Short-circuit behavior @ VIN=12 V Figure 33. Short-circuit behavior @ VIN=24 V

SYNCH

5V/div

OUT

5V/div

V

OUT

1V/div

I

L

1A/div

SYNCH

5V/div

OUT

5V/div

V

OUT

1V/div

I

L

0.5A/div

Timebase 10us/div

Timebase 10us/div

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A7985A Application ideas

7 Application ideas

7.1 Positive buck-boost

The A7985A can implement the step-up/down converter with a positive output voltage.

Figure 34 shows the schematic: one power MOSFET and one Schottky diode are added to

the standard buck topology to provide a 12 V output voltage with input voltage from 4.5 V to
38 V.

Figure 34. Positive buck-boost regulator

The relationship between input and output voltage is:

Equation 38

D

-------------

V

OUTVIN

⋅=

1D–

so the duty cycle is:

Equation 39

V

D

OUT

--------------------------------=

V

+

OUTVIN

The output voltage isn’t limited by the maximum operating voltage of the device (38 V),
because the output voltage is sensed only through the resistor divider. The external power
MOSFET maximum drain to source voltage, must be higher than output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 34, if V

IN

is

higher than 16 V, the gate must be protected through a Zener diode and resistor).

The current flowing through the internal power MOSFET is transferred to the load only
during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum
output current for the buck boost topology can be calculated from the following equation.

Doc ID 023128 Rev 1 37/45

Application ideas A7985A

Equation 40

I

OUT

-------------

1D–

2 A<=

I

SW

where I

is the average current in the embedded power MOSFET in the ON time.

SW

To chose the right value of the inductor and to manage transient output current, which, for a
short time, can exceed the maximum output current calculated by Equation 40, also the
peak current in the power MOSFET must be calculated. The peak current, shown in

Equation 41, must be lower than the minimum current limit (2.5 A).

Equation 41

I

SW,PK

--------------------------------------------

r

I

OUT

OUT

-------------

1D–

V

OUT

LF

⋅⋅

1

SW

r

-- -+ 3.7A<⋅=
2

⋅=

1D–()

2

I

where r is defined as the ratio between the inductor current ripple and the inductor DC
current.

Therefore, in the buck boost topology the maximum output current depends on the
application conditions (firstly input and output voltage, secondly switching frequency and
inductor value).

In Figure 35 the maximum output current for the above configuration is depicted, varying the
input voltage from 4.5 V to 38 V.

The dashed line considers a more accurate estimation of the duty cycles given by Equation

42, where power losses across diodes, the external power MOSFET, and the internal power

MOSFET are taken into account.

Figure 35. Maximum output current according to max. DC switch current (2.0 A):

V

=12 V

O

38/45 Doc ID 023128 Rev 1

A7985A Application ideas

Equation 42

V

2V

D

-------------------------------------------------------------- -------------------------------------=

V

INVSWVSWEVOUT

OUT

⋅+

D

++––

2V⋅

D

where V

is the voltage drop across the diodes, VSW and V

D

external power MOSFET.

7.2 Inverting buck-boost

The A7985A can implement the step-up/down converter with a negative output voltage.

Figure 34 shows the schematic to regulate -5 V: no further external components are added

to the standard buck topology.

The relationship between input and output voltage is:

Equation 43

so the duty cycle is:

Equation 44

V

OUT

D

VIN–

V

OUT

------------------------------- -=

V

OUTVIN

across the internal and

SWE

D

-------------

⋅=

1D–

–

As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (2.0 A), the maximum output current can be calculated from Equation 40,
where the duty cycle is given by Equation 44.

Figure 36. Inverting buck-boost regulator

Doc ID 023128 Rev 1 39/45

Application ideas A7985A

The GND pin of the device is connected to the output voltage so, given the output voltage,
the input voltage range is limited by the maximum voltage the device can withstand across
VCC and GND (38 V). Therefore, if the output is -5 V, the input voltage can range from 4.5 V
to 33 V.

As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 37. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 45, where power losses across diodes and the internal
power MOSFET are taken into account.

Equation 45

V

–

------------------------------------------------------ --------------=

D

OUTVD

V–

INVSWVOUTVD

–+–

Figure 37. Maximum output current according to switch max. peak current (2.0 A):

V

=-5 V

O

40/45 Doc ID 023128 Rev 1

A7985A Package mechanical data

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Table 10. HSOP8 mechanical data

mm inch

Dim

Min. Typ. Max. Min. Typ. Max.

A 1.70 0.0669

A1 0.00 0.150 0.00 0.0059

A2 1.25 0.0492

b 0.31 0.51 0.0122 0.0201

c 0.17 0.25 0.0067 0.0098

D 4.80 4.90 5.00 0.1890 0.1929 0.1969

E 5.80 6.00 6.20 0.2283 0.2362 0.2441

E1 3.80 3.90 4.00 0.1496 0.1535 0.1575

e 1.27 0.0500

h 0.25 0.50 0.0098 0.0197

L 0.40 1.27 0.0157 0.0500

k 0.00 8.00 0.3150

ccc 0.10 0.0039

Doc ID 023128 Rev 1 41/45

Package mechanical data A7985A

Figure 38. Package dimensions

$MM4YP
%MM4YP

!-V

42/45 Doc ID 023128 Rev 1

A7985A Order codes

9 Order codes

Table 11. Order codes

Order codes Package Packaging

A7985A HSOP8 Tube

A7985ATR HSOP8 Tape and reel

Doc ID 023128 Rev 1 43/45

Revision history A7985A

10 Revision history

Table 12. Document revision history

Date Revision Changes

19-Apr-2012 1 Initial release.

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A7985A

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