74VHCT574A
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING
■HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 5V
■LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C
■COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX)
■POWER DOWN PROTECTION ON INPUTS & OUTPUTS
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574
■IMPROVED LATCH-UP IMMUNITY
■LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTION
The 74VHCT574A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q outputs will be set to the logic states that were setup at the D inputs.
SOP |
TSSOP |
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Table 1: Order Codes |
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PACKAGE |
T & R |
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SOP |
74VHCT574AMTR |
TSSOP |
74VHCT574ATTR |
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When the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and when (OE) is high, the outputs will be in a high impedance state.
The Output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off.
Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
December 2004 |
Rev. 4 |
1/13 |
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74VHCT574A
Figure 2: Input Equivalent Circuit |
Table 2: Pin Description |
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PIN N° |
SYMBOL |
NAME AND FUNCTION |
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1 |
OE |
3-State Output Enable |
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Input (Active LOW) |
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2, 3, 4, 5, 6, |
D0 to D7 |
Data Inputs |
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7, 8, 9 |
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12, 13, 14, |
Q0 to Q7 |
3-State Outputs |
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15, 16, 17, |
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18, 19 |
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11 |
CK |
Clock Input (LOW-to-HIGH |
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Edge Triggered) |
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10 |
GND |
Ground (0V) |
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20 |
VCC |
Positive Supply Voltage |
Table 3: Truth Table |
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INPUTS |
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OUTPUT |
OE |
CK |
D |
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Q |
H |
X |
X |
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Z |
L |
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X |
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NO CHANGE |
L |
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L |
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L |
L |
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H |
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H |
X : Don’t Care
Z : High Impedance
2/13
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74VHCT574A |
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Table 4: Absolute Maximum Ratings |
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Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7.0 |
V |
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VI |
DC Input Voltage |
-0.5 to +7.0 |
V |
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VO |
DC Output Voltage (see note 1) |
-0.5 to +7.0 |
V |
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VO |
DC Output Voltage (see note 2) |
-0.5 to VCC + 0.5 |
V |
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IIK |
DC Input Diode Current |
- 20 |
mA |
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IOK |
DC Output Diode Current |
± |
20 |
mA |
IO |
DC Output Current |
± |
25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± |
50 |
mA |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
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TL |
Lead Temperature (10 sec) |
300 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
1)Output in OFF State
2)High or Low State
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
4.5 to 5.5 |
V |
VI |
Input Voltage |
0 to 5.5 |
V |
VO |
Output Voltage (see note 1) |
0 to 5.5 |
V |
VO |
Output Voltage (see note 2) |
0 to VCC |
V |
Top |
Operating Temperature |
-55 to 125 |
°C |
dt/dv |
Input Rise and Fall Time (see note 3) (VCC = 5.0 ± 0.5V) |
0 to 20 |
ns/V |
1)Output in OFF State
2)High or Low State
3)VIN from 0.8V to 2V
3/13
74VHCT574A
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
4.5 to |
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2 |
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2 |
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2 |
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V |
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Voltage |
5.5 |
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VIL |
Low Level Input |
4.5 to |
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0.8 |
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0.8 |
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0.8 |
V |
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Voltage |
5.5 |
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VOH |
High Level Output |
4.5 |
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IO=-50 A |
4.4 |
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4.5 |
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4.4 |
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4.4 |
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V |
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Voltage |
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4.5 |
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IO=-8 mA |
3.94 |
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3.8 |
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3.7 |
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VOL |
Low Level Output |
4.5 |
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IO=50 A |
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0.0 |
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0.1 |
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0.1 |
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0.1 |
V |
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Voltage |
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4.5 |
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IO=8 mA |
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0.36 |
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0.44 |
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0.55 |
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IOZ |
High Impedance |
4.5 to |
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VI = VIH or VIL |
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± |
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± |
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± |
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A |
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Output Leakage |
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0.25 |
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2.5 |
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2.5 |
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Current |
5.5 |
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VO = 0V to 5.5V |
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II |
Input Leakage |
0 to |
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VI = 5.5V or GND |
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± 0.1 |
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± |
1.0 |
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1.0 |
A |
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Current |
5.5 |
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ICC |
Quiescent Supply |
5.5 |
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VI = VCC or GND |
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4 |
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40 |
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40 |
A |
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Current |
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+ICC |
Additional Worst |
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One Input at 3.4V, |
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Case Supply |
5.5 |
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other input at VCC |
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1.35 |
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1.5 |
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1.5 |
mA |
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Current |
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or GND |
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IOPD |
Output Leakage |
0 |
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VOUT = 5.5V |
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0.5 |
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5.0 |
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5.0 |
A |
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Current |
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Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) |
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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CL |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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(pF) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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tPLH |
Propagation Delay |
5.0(*) |
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15 |
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5.5 |
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8.6 |
1.0 |
10.0 |
1.0 |
10.0 |
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tPHL |
Time CK to Q |
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5.0(*) |
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50 |
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7.0 |
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10.6 |
1.0 |
12.0 |
1.0 |
12.0 |
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tPZL |
Output Enable |
5.0(*) |
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15 |
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RL = 1KΩ |
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5.0 |
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9.0 |
1.0 |
10.5 |
1.0 |
10.5 |
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tPZH |
Time |
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5.0(*) |
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50 |
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6.0 |
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11.0 |
1.0 |
12.5 |
1.0 |
12.5 |
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tPLZ |
Output Disable |
5.0(*) |
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50 |
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RL = 1KΩ |
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7.0 |
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10.1 |
1.0 |
11.5 |
1.0 |
11.5 |
ns |
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tPHZ |
Time |
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fMAX |
Maximum Clock |
5.0(*) |
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15 |
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90 |
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140 |
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80 |
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80 |
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MHz |
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Frequency |
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5.0(*) |
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50 |
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85 |
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130 |
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tOSLH |
Output to Output |
5.0(*) |
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50 |
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1.5 |
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1.5 |
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1.5 |
ns |
tOSHL |
Skew time (note 1) |
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(*) Voltage range is 5.0V ± 0.5V
Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
4/13