The 74VHCT541A is an advanced high-speed
CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
The 3 STATE control gate opera tes as two input
AND such that if either G1
and G2 are high, all
eight outputs are in the high impedance state.
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74VHCT541AMTR
TSSOP74VHCT541ATTR
In order to enhance PC board layout, the
74VHCT541 offers a pinout having inputs and
outputs on opposite sides of the package.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used t o interf ace 5V to 3V s ince al l
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) Output in OFF State
2) High or Low State
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage (see note 1)
O
DC Output Voltage (see note 2)-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7.0V
-0.5 to +7.0V
-0.5 to +7.0V
V
- 20mA
± 20mA
± 25mA
± 50mA
-65 to +150°C
300°C
2/12
74VHCT541A
Table 5: Recommended Operating Conditions
SymbolParameterValueUnit
V
V
V
V
T
dt/dv
1) Output in OFF State
2) High or Low State
3) VIN from 0. 8V to 2V
Table 6: DC Specifications
SymbolParameter
V
IH
V
IL
V
OH
V
OL
I
OZ
I
I
I
CC
+I
CC
I
OPD
Supply Voltage
CC
Input Voltage
I
Output Voltage (see note 1)
O
Output Voltage (see note 2)0 to V
O
Operating Temperature
op
Input Rise and Fall Time (see note 3) (V
= 5.0 ± 0.5V)
CC
Test ConditionValue
= 25°C
T
A
Min.Typ. Max.Min.Max. Min. Max.
222V
0.80.80.8V
4.44.54.44.4
3.943.83.7
0.00.10.10.1
0.360.440.55
±0.25± 2.5± 2.5µA
± 0.1± 1.0± 1.0µA
44040µA
1.351.51.5mA
0.5 5.0 5.0µA
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
High Impedance
Output Leakage
Current
Input Leakage
Current
Quiescent Supply
Current
Additional Worst
Case Supply
Current
Output Leakage
Current
V
CC
(V)
4.5 to
5.5
4.5 to
5.5
4.5
4.5
4.5
4.5
4.5 to
5.5
0 to
5.5
5.5
5.5
0
=-50 µA
I
O
=-8 mA
I
O
IO=50 µA
I
=8 mA
O
= VIH or V
V
I
IL
VO = 0V to 5.5V
V
= 5.5V or GND
I
= VCC or GND
V
I
One Input at 3.4V,
other input at V
CC
or GND
= 5.5V
V
OUT
4.5 to 5.5V
0 to 5.5V
0 to 5.5V
CC
-55 to 125°C
0 to 20ns/V
-40 to 85°C -55 to 125°C
V
Unit
V
V
Table 7: AC Electrical Characteristics (Input t
Test ConditionValue
SymbolParameter
t
Propagation Delay
PLH
PHL
PZL
PZH
PLZ
PHZ
Time
Output Disable
Time
Output Enable
Time
t
t
t
t
t
(*) Voltage range is 5.0V ± 0.5V
V
(*)
(V)
C
(pF)
L
CC
5.0154.16.01.06.51.06.5
5.0506.28.51.09.51.09.5
5.015
5.0507.510.01.012.01.012.0
RL = 1K
5.050RL = 1K
= tf = 3ns)
r
= 25°C
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
Ω
Ω7.010.01.012.01.012.0ns
5.07.01.08.01.08.0
Unit
ns
ns
3/12
74VHCT541A
Table 8: Capacitive Characteristics
Test ConditionValue
= 25°C
SymbolParameter
T
A
Min.Typ. Max.Min.Max. Min. Max.
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance
Power Dissipation
PD
Capacitance
6101010pF
8pF
16pF
(note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Table 9: Dynamic Switching Characteristics
Test ConditionValue
= 25°C
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
Dynamic High
V
IHD
Voltage Input
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
(note 1, 3)
V
CC
(V)
5.0
= 50 pF
5.02.0
C
L
5.00.8
T
A
Min.Typ. Max.Min.Max. Min. Max.
0.91.1
-1.1-0.9
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per c ircuit )
CC(opr)
-40 to 85°C -55 to 125°C
Unit
Unit
V
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 3.0V, (n-1) outputs switc hi ng and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V
(V
), f=1MHz.
IHD
ILD
), 0V to thresho l d
4/12
Figure 3: Test Circuit
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
74VHCT541A
TESTSWITCH
Open
V
CC
GND
CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)
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