ST 74VHCT138A User Manual

74VHCT138A

3 TO 8 LINE DECODER (INVERTING)

■ HIGH SPEED: t

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ COMPATIBLE WITH TTL OUTP U TS:

V

= 2V (M IN.), V

IH

■ POWER DOWN PROTECTION ON INPUTS

= 7.6 ns (TYP.) at VCC = 5V

PD

= 0.8V (MAX)

IL

& OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 8 mA (MIN)

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

PHL

■ OPERATING VOLTAGE RANGE:

V

(OPR) = 4.5V to 5.5V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: V

= 0.8V (MAX.)

OLP

DESCRIPTION

The 74VHCT138A is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C

2

MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. When enable input G1 is held low or either G2A

or G2B is held high, the d ec oding fun ction is

inhibited and all the 8 outputs go to high.

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74VHCT138AMTR

TSSOP 74VHCT138ATTR

The three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used t o interf ace 5V to 3V s ince al l inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static disc harge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 3

1/12December 2004

74VHCT138A

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

1, 2, 3 A, B, C Address Inputs

4, 5 G2A

6 G1 Enable Input

15, 14, 13,

12, 1 1, 10, 9,

7 8 GND Ground (0V)

16 V

Table 3: Truth Table

, G2B Enable Inputs

to Y7 Outputs

Y0

CC

Positive Supply Voltage

INPUTS

ENABLE SELECT

G2B

X : Don’t Care

G2A G1CBAY0Y1 Y2 Y3 Y4 Y5 Y6 Y7

XXLXXXHHHHHHHH XHXXXXHHHHHHHH HXXXXXHHHHHHHH LLHLLLLHHHHHHH LLHLLHHLHHHHHH LLHLHLHHLHHHHH LLHLHHHHHLHHHH LLHHLLHHHHLHHH LLHHLHHHHHHLHH LLHHHLHHHHHHLH LLHHHHHHHHHHHL

OUTPUTS

Figure 3: Logic Diagram

This logi c di agram has not be used to est i m ate propaga tion delays

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74VHCT138A

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

V V V

I

OK

I

or I

I

CC

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

1) V

CC

2) High or Low State

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V V T

dt/dv

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage (see note 1)

O

DC Output Voltage (see note 2) -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

= 0V

Supply Voltage

CC

Input Voltage

I

Output Voltage (see note 1)

O

Output Voltage (see note 2) 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (see note 3) (V

= 5.0 ± 0.5V)

CC

-0.5 to +7.0 V

- 20 mA

± 20 mA ± 25 mA ± 50 mA

-65 to +150 °C 300 °C

4.5 to 5.5 V 0 to 5.5 V 0 to 5.5 V

CC

-55 to 125 °C 0 to 20 ns/V

V

1) V

= 0V

CC

2) High or Low State

3) V

from 0.8V to 2V

IN

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74VHCT138A

Table 6: DC Specifications

Symbol Parameter

V

+I

I

High Level Input

IH

Voltage Low Level Input

V

IL

Voltage High Level Output

OH

Voltage Low Level Output

OL

Voltage

I

Input Leakage

I

Current

I

Quiescent Supply

CC

Current Additional Worst

CC

Case Supply Current

Output Leakage

OPD

Current

Test Condition Value

= 25°C

T

V

CC

(V)

4.5 to

5.5

A

Min. Typ. Max. Min. Max. Min. Max.

222V

4.5 to

5.5

4.5

0 to

VI = 5.5V or GND

5.5 V

5.5

I

O

=-8 mA

I

O

=50 µA

I

O

=8 mA

I

O

= VCC or GND

I

4.4 4.5 4.4 4.4

3.94 3.8 3.7

0.0 0.1 0.1 0.1

=-50 µA

One Input at 3.4V, other input at V

5.5

CC

or GND

= 5.5V

0

V

OUT

-40 to 85°C -55 to 125°C

Unit

0.8 0.8 0.8 V

V

0.36 0.44 0.55

V

± 0.1 ± 1.0 ± 1.0 µA

44040µA

1.35 1.5 1.5 mA

0.5 5.0 5.0 µA

Table 7: AC Electrical Characteristics (Input t

Test Condition Value

Symbol Parameter

t

Propagation Delay

PLH

t t

t

(*) Voltage range is 5.0V ± 0.5V

Time

PHL

A, B, C, to Y Propagation Delay

PLH

Time

PHL

G1 to Y Propagation Delay

PLH

Time

PHL

G2A

, G2B to Y

V

(V)

5.0

C

CC

L

(pF)

(*)

15 7.6 10.4 1.0 12.0 1.0 12.0

(*)

50 8.1 11.4 1.0 13.0 1.0 13.0

(*)

15 6.6 9.1 1.0 10.5 1.0 10.5

(*)

50 7.1 10.1 1.0 11.5 1.0 11.5

(*)

15 7.0 9.6 1.0 11.0 1.0 11.0

(*)

50 7.5 10.6 1.0 12.0 1.0 12.0

Table 8: Capacitive Characteristics

Test Condition Value

Symbol Parameter

C

Input Capacitance

IN

Power Dissipation

PD

Capacitance (note 1)

= tf = 3ns)

r

= 25°C

T

A

-40 to 85°C -55 to 125°C

Min. Typ. Max. Min. Max. Min. Max.

= 25°C

T

A

-40 to 85°C -55 to 125°C

Min. Typ. Max. Min. Max. Min. Max.

610 10 10pF

36 pF

Unit

ns

Unit

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I

= CPD x VCC x fIN + I

CC(opr)

CC

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