ST 74VHC74 User Manual

74VHC74

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

■HIGH SPEED:

fMAX = 170 MHz (TYP.) at VCC = 5V

■LOW POWER DISSIPATION:

ICC = 2 A (MAX.) at TA=25°C

■HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)

■POWER DOWN PROTECTION ON INPUTS

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74

■IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHC74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUTS during the positive going transition of the clock pulse.

SOP TSSOP

Table 1: Order Codes

PACKAGE	T & R
SOP	74VHC74MTR
TSSOP	74VHC74TTR

CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004	Rev. 4
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74VHC74

	Figure 2: Input Equivalent Circuit				Table 2: Pin Description
					PIN N°	SYMBOL	NAME AND FUNCTION
					1, 13	1CLR, 2CLR	Asynchronous Reset -
							Direct Input
					2, 12	1D, 2D	Data Inputs
					3, 11	1CK, 2CK	Clock Input
							(LOW to HIGH, Edge
							Triggered)
					4, 10	1PR, 2PR	Asynchronous Set - Direct
							Input
					5, 9	1Q, 2Q	True Flip-Flop Outputs
					6, 8	1Q, 2Q	Complement Flip-Flop
							Outputs
					7	GND	Ground (0V)
					14	VCC	Positive Supply Voltage
	Table 3: Truth Table
			INPUTS		OUTPUTS		FUNCTION
	CLR	PR	D	CK	Q	Q
	L	H	X	X	L	H	CLEAR
	H	L	X	X	H	L	PRESET
	L	L	X	X	H	H
	H	H	L		L	H
	H	H	H		H	L
	H	H	X		Qn	Qn	NO CHANGE

X : Don’t Care

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

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				74VHC74
Table 4: Absolute Maximum Ratings
Symbol	Parameter	Value			Unit
VCC	Supply Voltage	-0.5 to +7.0			V
VI	DC Input Voltage	-0.5 to +7.0			V
VO	DC Output Voltage	-0.5 to VCC + 0.5			V
IIK	DC Input Diode Current	- 20			mA
IOK	DC Output Diode Current	±	20		mA
IO	DC Output Current	±	25		mA
ICC or IGND	DC VCC or Ground Current	±	50		mA
Tstg	Storage Temperature	-65 to +150			°C
TL	Lead Temperature (10 sec)	300			°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

Table 5: Recommended Operating Conditions

	Symbol	Parameter		Value	Unit
	VCC	Supply Voltage		2 to 5.5	V
	VI	Input Voltage		0 to 5.5	V
	VO	Output Voltage		0 to VCC	V
	Top	Operating Temperature		-55 to 125	°C
	dt/dv	Input Rise and Fall Time (note 1) (VCC = 3.3 ±	0.3V)	0 to 100	ns/V
		(VCC = 5.0 ±	0.5V)	0 to 20

1) VIN from 30% to 70% of VCC

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74VHC74

Table 6: DC Specifications

			Test Condition							Value
Symbol	Parameter	VCC				TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
		(V)			Min.		Typ.	Max.		Min.	Max.	Min.	Max.
VIH	High Level Input	2.0			1.5					1.5		1.5
	Voltage	3.0 to			0.7VCC					0.7VCC		0.7VCC		V
		5.5
VIL	Low Level Input	2.0							0.5		0.5		0.5
	Voltage	3.0 to						0.3VCC			0.3VCC		0.3VCC	V
		5.5
VOH	High Level Output	2.0		IO=-50 A	1.9		2.0			1.9		1.9
	Voltage
		3.0		IO=-50 A	2.9		3.0			2.9		2.9
		4.5		IO=-50 A	4.4		4.5			4.4		4.4		V
		3.0		IO=-4 mA	2.58					2.48		2.4
		4.5		IO=-8 mA	3.94					3.8		3.7
VOL	Low Level Output	2.0		IO=50 A			0.0		0.1		0.1		0.1
	Voltage
		3.0		IO=50 A			0.0		0.1		0.1		0.1
		4.5		IO=50 A			0.0		0.1		0.1		0.1	V
		3.0		IO=4 mA				0.36			0.44		0.55
		4.5		IO=8 mA				0.36			0.44		0.55
II	Input Leakage	0 to		VI = 5.5V or GND				±	0.1		± 1		± 1	A
	Current	5.5
ICC	Quiescent Supply	5.5		VI = VCC or GND					2		20		20	A
	Current

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74VHC74

Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)

							Test Condition								Value
Symbol			Parameter				VCC	CL			TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
							(V)	(pF)		Min.		Typ.	Max.		Min.	Max.	Min.	Max.
tPLH		Propagation Delay					3.3(*)	15				6.7		11.9	1.0	14.0	1.0	14.0
tPHL		Time CK to Q or Q
							3.3(*)	50				9.2		15.4	1.0	17.5	1.0	17.5	ns
							5.0(**)	15				4.6		7.3	1.0	8.5	1.0	8.5
							5.0(**)	50				6.1		9.3	1.0	10.5	1.0	10.5
tPLH		Propagation Delay					3.3(*)	15				7.6		12.3	1.0	14.5	1.0	14.5
tPHL		Time PR or CLR to
							3.3(*)	50				10.1		15.8	1.0	18.0	1.0	18.0
		Q or Q																	ns
							5.0(**)	15				4.8		7.7	1.0	9.0	1.0	9.0
							5.0(**)	50				6.3		9.7	1.0	11.0	1.0	11.0
tW		CK Pulse Width					3.3(*)							6.0		7.0		7.0	ns
		HIGH or LOW
							5.0(**)							5.0		5.0		5.0
tW		PR or CLR Pulse					3.3(*)							6.0		7.0		7.0	ns
		Width LOW					5.0(**)							5.0		5.0		5.0
ts		Setup Time D to CK					3.3(*)							6.0		7.0		7.0	ns
		HIGH or LOW
							5.0(**)							5.0		5.0		5.0
th		Hold Time D to CK					3.3(*)							0.5		0.5		0.5	ns
		HIGH or LOW
							5.0(**)							0.5		0.5		0.5
tREM		Removal Time					3.3(*)							5.0		5.0		5.0	ns
		PR or CLR to CK
							5.0(**)							3.0		3.0		3.0
fMAX		Maximum Clock					3.3(*)	15		80		125			70		70
		Frequency
							3.3(*)	50		50		75			45		45		MHz
							5.0(**)	15		130		170			110		110
							5.0(**)	50		90		115			75		75
(*) Voltage range is 3.3V ±						0.3V
(**) Voltage range is 5.0V ±						0.5V
Table 8: Capacitive Characteristics
							Test Condition								Value
Symbol			Parameter				VCC				TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
							(V)			Min.		Typ.	Max.		Min.	Max.	Min.	Max.
CIN		Input Capacitance					5.0					7		10		10		10	pF
CPD		Power Dissipation						fIN = 10MHz				25							pF
		Capacitance					5.0
		(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per flip-flop)

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