ST 74VHC541 User Manual

74VHC541

OCTAL BUS BUFFER

WITH 3 STATE OUTPUTS (NON INVERTED)

■ HIGH SPEED: t

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ HIGH NOISE IMMUNITY:

V

= V

NIH

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

OH

■ BALANCED PROPAGATION DELAYS:

t

PLH

■ OPERATING VOLTAGE RANGE:

V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

NIL

| = IOL = 8 mA (MIN)

≅ t

PHL

(OPR) = 2V to 5.5V

= 3.5 ns (TYP.) at VCC = 5V

PD

= 28% VCC (MIN.)

74 SERIES 541

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: V

= 0.9V (MAX.)

OLP

DESCRIPTION

The 74VHC541 is an advanced high-speed
CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C

2

MOS technology.
The 3 STATE control gate opera tes as two input
AND such that if either G1

or G2 are high, all eight

outputs are in the high impedance state.

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74VHC541MTR

TSSOP 74VHC541TTR

In order to enhance PC board layout, the
74VHC541 offers a pinout having inputs and
outputs on opposite sides of the package.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 4

1/12November 2004

74VHC541

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

1, 19 G1

2, 3, 4, 5, 6,

7, 8, 9

18, 17, 16,
15, 14, 13,

12, 11

10 GND Ground (0V)
20 V

Table 3: Truth Table

INPUT OUTPUT

, G2 Output Enable Inputs

A1 to A8 Data Inputs

Y1 to Y8 Data Outputs

CC

Positive Supply Voltage

G1

G2 An Yn

HXXZ
XHXZ

LLHH
LLLL

X : Don’t ca re
Z : High impedance

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

or I

I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current
DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

-0.5 to +7.0 V

-0.5 to +7.0 V
V

- 20 mA

± 20 mA
± 25 mA
± 75 mA

-65 to +150 °C

300 °C

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V
V
T

dt/dv

1) VIN from 30 % t o 70% of V

Supply Voltage

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (note 1) (V
(V

CC

= 3.3 ± 0.3V)

CC

= 5.0 ± 0.5V)

CC

2 to 5.5 V
0 to 5.5 V

CC

-55 to 125 °C
0 to 100

0 to 20

2/12

V

ns/V

Table 6: DC Specifications

Symbol Parameter

V

V

V

High Level Input

IH

Voltage

V

Low Level Input

IL

Voltage

High Level Output

OH

Voltage

Low Level Output

OL

Voltage

I

High Impedance

OZ

Output Leakage
Current

Input Leakage

I

I

Current

I

Quiescent Supply

CC

Current

3.0 to

3.0 to

74VHC541

Test Condition Value

= 25°C

T

V

CC

(V)

A

Min. Typ. Max. Min. Max. Min. Max.

2.0 1.5 1.5 1.5

0.7V

5.5

CC

2.0 0.5 0.5 0.5

5.5

2.0

3.0

4.5

3.0

4.5

2.0

3.0

4.5

3.0

4.5

5.5
VO = VCC or GND

0 to

V

5.5

V

5.5

IO=-50 µA
I

=-50 µA

O

=-50 µA

I

O

=-4 mA

I

O

=-8 mA

I

O

IO=50 µA

=50 µA

I

O

=50 µA

I

O

=4 mA

I

O

=8 mA

I

O

= VIH or V

V

I

= 5.5V or GND

I

= VCC or GND

I

IL

1.9 2.0 1.9 1.9

2.9 3.0 2.9 2.9

4.4 4.5 4.4 4.4

2.58 2.48 2.4

3.94 3.8 3.7

0.3V

0.0 0.1 0.1 0.1

0.0 0.1 0.1 0.1

0.0 0.1 0.1 0.1

±0.25 ± 2.5 ± 2.5 µA

-40 to 85°C -55 to 125°C

CC

0.7V

CC

0.3V

CC

0.7V

CC

0.3V

0.36 0.44 0.55

0.36 0.44 0.55

± 0.1 ± 1 ± 1 µA

44040µA

CC

Unit

V

V

V

V

3/12

74VHC541

Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)

Test Condition Value

= 25°C

Symbol Parameter

t

Propagation Delay

PLH

t

t
t

t
t

t

OSLH

t

OSHL

Time

PHL

Output Enable

PZL

Time

PZH

Output Disable

PLZ

Time

PHZ

Output to Output
Skew time (note 1)

V

3.3

3.3

5.0

5.0

3.3

3.3

5.0

5.0

3.3

5.0

3.3

5.0

C

CC

(V)

L

(pF)

(*)

15 5.0 7.0 1.0 8.5 1.0 8.5

(*)

50 7.5 10.5 1.0 12.0 1.0 12.0

(**)

15 3.5 5.0 1.0 6.0 1.0 6.0

(**)

50 5.0 7.0 1.0 8.0 1.0 8.0

(*)

15

(*)

50

(**)

15

(**)

50

(*)

50

(**)

50

(*)

50 1.5 1.5 1.5

(**)

50 1.0 1.0 1.0

R

L

R

L

R

L

R

L

R

L

R

L

= 1KΩ
= 1KΩ
= 1KΩ
= 1KΩ
= 1KΩ
= 1KΩ

T

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

6.8 10.5 1.0 12.5 1.0 12.5

9.3 14.0 1.0 16.0 1.0 16.0

4.7 7.2 1.0 8.5 1.0 8.5

6.2 9.2 1.0 10.5 1.0 10.5

11.2 15.4 1.0 17.5 1.0 17.5

6.0 8.8 1.0 10.0 1.0 10.0

Unit

ns

ns

ns

ns

(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ±
Note 1: Parameter guaranteed by design. t

0.5V

soLH

= |t

pLHm

- t

pLHn

|, t

soHL

= |t

pHLm

- t

pHLn

|

Table 8: Capacitive Characteristics

Test Condition Value

T

Symbol Parameter

C

C

C

Input Capacitance

IN

Output

OUT

Capacitance
Power Dissipation

PD

Capacitance
(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I
Circuit)

= 25°C

A

-40 to 85°C -55 to 125°C

Min. Typ. Max. Min. Max. Min. Max.

710 10 10pF
9pF

18 pF

= CPD x VCC x fIN + ICC/8 (per

CC(opr)

Unit

4/12