ST 74VHC374 User Manual

74VHC374

OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING

■HIGH SPEED:

fMAX = 270 MHz (TYP.) at VCC = 5V

■LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C

■HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)

■POWER DOWN PROTECTION ON INPUTS

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374

■IMPROVED LATCH-UP IMMUNITY

■LOW NOISE: VOLP = 0.9V (MAX.)

DESCRIPTION

The 74VHC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE).

On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs.

SOP TSSOP

Table 1: Order Codes

PACKAGE	T & R
SOP	74VHC374MTR
TSSOP	74VHC374TTR

While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.

The Output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004	Rev. 4
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74VHC374

Figure 2: Input Equivalent Circuit		Table 2: Pin Description
		PIN N°	SYMBOL	NAME AND FUNCTION
		1	OE	3 State Output Enable
				Input (Active LOW)
		2, 5, 6, 9, 12,	Q0 to Q7	3-State Outputs
		15, 16,19
		3, 4, 7, 8, 13,	D0 to D7	Data Inputs
		14, 17, 18
		11	CK	Clock
		10	GND	Ground (0V)
		20	VCC	Positive Supply Voltage
Table 3: Truth Table
	INPUTS			OUTPUT
OE	CK	D		Q
H	X	X		Z
L		X		NO CHANGE
L		L		L
L		H		H

X : Don’t Care

Z : High Impedance

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

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				74VHC374
Table 4: Absolute Maximum Ratings
Symbol	Parameter	Value			Unit
VCC	Supply Voltage	-0.5 to +7.0			V
VI	DC Input Voltage	-0.5 to +7.0			V
VO	DC Output Voltage	-0.5 to VCC + 0.5			V
IIK	DC Input Diode Current	- 20			mA
IOK	DC Output Diode Current	±	20		mA
IO	DC Output Current	±	25		mA
ICC or IGND	DC VCC or Ground Current	±	75		mA
Tstg	Storage Temperature	-65 to +150			°C
TL	Lead Temperature (10 sec)	300			°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

Table 5: Recommended Operating Conditions

	Symbol	Parameter		Value	Unit
	VCC	Supply Voltage		2 to 5.5	V
	VI	Input Voltage		0 to 5.5	V
	VO	Output Voltage		0 to VCC	V
	Top	Operating Temperature		-55 to 125	°C
	dt/dv	Input Rise and Fall Time (note 1) (VCC = 3.3 ±	0.3V)	0 to 100	ns/V
		(VCC = 5.0 ±	0.5V)	0 to 20

1) VIN from 30% to 70% of VCC

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74VHC374

Table 6: DC Specifications

			Test Condition							Value
Symbol	Parameter	VCC				TA = 25°C				-40 to 85°C			-55 to 125°C			Unit
		(V)			Min.		Typ.	Max.		Min.	Max.		Min.	Max.
VIH	High Level Input	2.0			1.5					1.5			1.5
	Voltage	3.0 to			0.7VCC					0.7VCC			0.7VCC			V
		5.5
VIL	Low Level Input	2.0							0.5		0.5			0.5
	Voltage	3.0 to						0.3VCC			0.3VCC			0.3VCC		V
		5.5
VOH	High Level Output	2.0		IO=-50 A	1.9		2.0			1.9			1.9
	Voltage
		3.0		IO=-50 A	2.9		3.0			2.9			2.9
		4.5		IO=-50 A	4.4		4.5			4.4			4.4			V
		3.0		IO=-4 mA	2.58					2.48			2.4
		4.5		IO=-8 mA	3.94					3.8			3.7
VOL	Low Level Output	2.0		IO=50 A			0.0		0.1		0.1			0.1
	Voltage
		3.0		IO=50 A			0.0		0.1		0.1			0.1
		4.5		IO=50 A			0.0		0.1		0.1			0.1		V
		3.0		IO=4 mA				0.36			0.44			0.55
		4.5		IO=8 mA				0.36			0.44			0.55
IOZ	High Impedance	5.5		VI = VIH or VIL				±	0.25		±	2.5		±	2.5	A
	Output Leakage			VO = VCC or GND
	Current
II	Input Leakage	0 to		VI = 5.5V or GND				±	0.1		±	1		±	1	A
	Current	5.5
ICC	Quiescent Supply	5.5		VI = VCC or GND					4		40			40		A
	Current

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74VHC374

Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)

			Test Condition								Value
Symbol	Parameter		VCC	CL			TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
			(V)	(pF)		Min.		Typ.	Max.		Min.	Max.	Min.	Max.
tPLH	Propagation Delay		3.3(*)	15				8.1		12.7	1.0	15.0	1.0	15.0
tPHL	Time
			3.3(*)	50				10.6		16.2	1.0	18.5	1.0	18.5
	CK to Q														ns
			5.0(**)	15				5.4		8.1	1.0	9.5	1.0	9.5
			5.0(**)	50				6.9		10.1	1.0	11.5	1.0	11.5
tPZL	Output Enable		3.3(*)	15	RL = 1KΩ			7.1		11.0	1.0	13.0	1.0	13.0
tPZH	Time
			3.3(*)	50	RL = 1KΩ			9.6		14.5	1.0	16.5	1.0	16.5	ns
			5.0(**)	15	RL = 1KΩ			5.1		7.6	1.0	9.0	1.0	9.0
			5.0(**)	50	RL = 1KΩ			6.6		9.6	1.0	11.0	1.0	11.0
tPLZ	Output Disable		3.3(*)	15	RL = 1KΩ			10.2		14.0	1.0	16.0	1.0	16.0	ns
tPHZ	Time
			3.3(*)	50	RL = 1KΩ			6.1		8.8	1.0	10.0	1.0	10.0
tw	Clock Pulse Width		3.3(*)							5.0		5.5		5.5	ns
	HIGH or LOW
			5.0(**)							5.0		5.0		5.0
ts	Setup Time D to CK		3.3(*)							4.5		4.5		4.5	ns
	HIGH or LOW
			5.0(**)							3.0		3.0		3.0
th	Hold Time D to CK		3.3(*)							2.0		2.0		2.0	ns
	HIGH or LOW
			5.0(**)							2.0		2.0		2.0
fMAX	Maximum Clock		3.3(*)			60		250			60		60		MHz
	Frequency
			5.0(**)			100		270			100		100
tOSLH	Output to Output		3.3(*)	50						1.5		1.5		1.5	ns
tOSHL	Skew time (note 1)
			5.0(**)	50						1.0		1.0		1.0
(*) Voltage range is 3.3V ±		0.3V
(**) Voltage range is 5.0V ±		0.5V
Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
Table 8: Capacitive Characteristics
			Test Condition								Value
Symbol	Parameter						TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
						Min.		Typ.	Max.		Min.	Max.	Min.	Max.
CIN	Input Capacitance							7		10		10		10	pF
COUT	Output							9							pF
	Capacitance
CPD	Power Dissipation							32							pF
	Capacitance
	(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop)

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