74VHC273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
■HIGH SPEED:
fMAX = 165 MHz (TYP.) at VCC = 5V
■LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C
■HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
■POWER DOWN PROTECTION ON INPUTS
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273
■IMPROVED LATCH-UP IMMUNITY
■LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTION
The 74VHC273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.
SOP TSSOP
PACKAGE |
T & R |
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SOP |
74VHC273MTR |
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TSSOP |
74VHC273TTR |
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When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
November 2004 |
Rev. 5 |
1/14 |
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74VHC273
Figure 2: Input Equivalent Circuit |
Table 2: Pin Description |
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PIN N° |
SYMBOL |
NAME AND FUNCTION |
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1 |
CLEAR |
Asynchronous Master |
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Reset (Active LOW) |
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2, 5, 6, 9, 12, |
Q0 to Q7 |
Flip-Flop Outputs |
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15, 16,19 |
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3, 4, 7, 8, 13, |
D0 to D7 |
Data Inputs |
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14, 17, 18 |
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11 |
CLOCK |
Clock Input (LOW-to-HIGH |
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Edge Triggered) |
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10 |
GND |
Ground (0V) |
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20 |
VCC |
Positive Supply Voltage |
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Table 3: Truth Table |
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INPUTS |
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OUTPUT |
FUNCTION |
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CLEAR |
D |
B |
Q |
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L |
X |
X |
L |
CLEAR |
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H |
L |
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L |
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H |
H |
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H |
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H |
X |
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Qn |
NO CHANGE |
X : Don’t Care
This logic diagram has not be used to estimate propagation delays
2/14
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74VHC273 |
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Table 4: Absolute Maximum Ratings |
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Symbol |
Parameter |
Value |
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Unit |
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VCC |
Supply Voltage |
-0.5 to +7.0 |
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V |
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VI |
DC Input Voltage |
-0.5 to +7.0 |
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V |
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VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
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V |
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IIK |
DC Input Diode Current |
- 20 |
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mA |
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IOK |
DC Output Diode Current |
± |
20 |
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mA |
IO |
DC Output Current |
± |
25 |
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mA |
ICC or IGND |
DC VCC or Ground Current |
± |
75 |
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mA |
Tstg |
Storage Temperature |
-65 to +150 |
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°C |
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TL |
Lead Temperature (10 sec) |
300 |
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°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
2 to 5.5 |
V |
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VI |
Input Voltage |
0 to 5.5 |
V |
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VO |
Output Voltage |
0 to VCC |
V |
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Top |
Operating Temperature |
-55 to 125 |
°C |
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dt/dv |
Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) |
0 to 100 |
ns/V |
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(VCC = 5.0 ± 0.5V) |
0 to 20 |
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1) VIN from 30% to 70% of VCC
3/14
74VHC273
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
2.0 |
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1.5 |
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1.5 |
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1.5 |
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Voltage |
3.0 to |
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0.7VCC |
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0.7VCC |
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0.7VCC |
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V |
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5.5 |
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VIL |
Low Level Input |
2.0 |
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0.5 |
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0.5 |
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0.5 |
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Voltage |
3.0 to |
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0.3VCC |
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0.3VCC |
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0.3VCC |
V |
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5.5 |
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VOH |
High Level Output |
2.0 |
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IO=-50 A |
1.9 |
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2.0 |
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1.9 |
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1.9 |
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Voltage |
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3.0 |
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IO=-50 A |
2.9 |
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3.0 |
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2.9 |
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2.9 |
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4.5 |
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IO=-50 A |
4.4 |
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4.5 |
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4.4 |
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4.4 |
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V |
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3.0 |
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IO=-4 mA |
2.58 |
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2.48 |
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2.4 |
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4.5 |
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IO=-8 mA |
3.94 |
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3.8 |
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3.7 |
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VOL |
Low Level Output |
2.0 |
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IO=50 A |
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0.0 |
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0.1 |
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0.1 |
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0.1 |
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Voltage |
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3.0 |
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IO=50 A |
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0.0 |
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0.1 |
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0.1 |
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0.1 |
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4.5 |
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IO=50 A |
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0.0 |
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0.1 |
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0.1 |
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0.1 |
V |
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3.0 |
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IO=4 mA |
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0.36 |
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0.44 |
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0.55 |
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4.5 |
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IO=8 mA |
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0.36 |
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0.44 |
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0.55 |
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II |
Input Leakage |
0 to |
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VI = 5.5V or GND |
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± |
0.1 |
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± 1 |
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± 1 |
A |
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Current |
5.5 |
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ICC |
Quiescent Supply |
5.5 |
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VI = VCC or GND |
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4 |
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40 |
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40 |
A |
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Current |
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4/14
74VHC273
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Test Condition |
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Value |
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Symbol |
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Parameter |
VCC |
CL |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
(pF) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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tPLH |
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Propagation Delay |
3.3(*) |
15 |
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8.7 |
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13.6 |
1.0 |
16.0 |
1.0 |
16.0 |
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tPHL |
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Time |
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3.3(*) |
50 |
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11.2 |
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17.1 |
1.0 |
19.5 |
1.0 |
19.5 |
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CLOCK to Q |
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ns |
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5.0(**) |
15 |
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5.8 |
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9.0 |
1.0 |
10.5 |
1.0 |
10.5 |
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5.0(**) |
50 |
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7.3 |
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11.0 |
1.0 |
12.5 |
1.0 |
12.5 |
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tPHL |
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Propagation Delay |
3.3(*) |
15 |
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8.9 |
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13.6 |
1.0 |
16.0 |
1.0 |
16.0 |
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Time |
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3.3(*) |
50 |
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11.4 |
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17.1 |
1.0 |
19.5 |
1.0 |
19.5 |
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CLEAR to Q |
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ns |
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5.0(**) |
15 |
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5.2 |
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8.5 |
1.0 |
10.0 |
1.0 |
10.0 |
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5.0(**) |
50 |
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6.7 |
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10.5 |
1.0 |
12.0 |
1.0 |
12.0 |
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tW |
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CLEAR |
Pulse |
3.3(*) |
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5.0 |
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6.0 |
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6.0 |
ns |
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Width LOW |
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5.0(**) |
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5.0 |
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5.0 |
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5.0 |
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tW |
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CLOCK Pulse |
3.3(*) |
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5.5 |
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6.5 |
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6.5 |
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Width HIGH or |
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ns |
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5.0(**) |
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5.0 |
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5.0 |
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5.0 |
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LOW |
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ts |
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Setup Time D to |
3.3(*) |
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5.5 |
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6.5 |
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6.5 |
ns |
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CLOCK, HIGH or |
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5.0(**) |
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4.5 |
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4.5 |
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4.5 |
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LOW |
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th |
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Hold Time D to |
3.3(*) |
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1.0 |
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1.0 |
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1.0 |
ns |
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CLOCK, HIGH or |
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5.0(**) |
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1.0 |
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1.0 |
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1.0 |
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LOW |
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tREM |
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Removal Time |
3.3(*) |
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2.5 |
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2.5 |
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2.5 |
ns |
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CLEAR to CLOCK |
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5.0(**) |
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2.0 |
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2.0 |
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2.0 |
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fMAX |
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Maximum Clock |
3.3(*) |
15 |
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75 |
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120 |
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65 |
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65 |
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Frequency |
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3.3(*) |
50 |
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50 |
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75 |
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45 |
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45 |
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MHz |
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5.0(**) |
15 |
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120 |
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165 |
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100 |
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100 |
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5.0(**) |
50 |
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80 |
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110 |
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70 |
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70 |
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tOSLH |
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Output to Output |
3.3(*) |
50 |
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1.5 |
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1.5 |
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1.5 |
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tOSHL |
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Skew time (note 1) |
5.0(**) |
50 |
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1.0 |
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1.0 |
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1.0 |
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(*) Voltage range is 3.3V ± |
0.3V |
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(**) Voltage range is 5.0V ± |
0.5V |
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Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| |
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Table 8: Capacitive Characteristics |
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Test Condition |
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Value |
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Symbol |
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Parameter |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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CIN |
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Input Capacitance |
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7 |
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10 |
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10 |
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pF |
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CPD |
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Power Dissipation |
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31 |
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pF |
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Capacitance |
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(note 1) |
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1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop)
5/14