ST 74VHC174 User Manual

74VHC174

HEX D-TYPE FLIP FLOP WITH CLEAR

■HIGH SPEED:

fMAX = 175MHz (TYP.) at VCC = 5V

■LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C

■HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)

■POWER DOWN PROTECTION ON INPUTS

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174

■IMPROVED LATCH-UP IMMUNITY

■LOW NOISE: VOLP = 0.8V (MAX.)

DESCRIPTION

The 74VHC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.

SOP TSSOP

Table 1: Order Codes

PACKAGE	T & R
SOP	74VHC174MTR
TSSOP	74VHC174TTR

When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004	Rev. 4
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74VHC174

Figure 2: Input Equivalent Circuit	Table 2: Pin Description
	PIN N°	SYMBOL	NAME AND FUNCTION
	1	CLEAR	Asynchronous Master
			Reset (Active LOW)
	2, 5, 7, 10,	Q0 to Q5	Flip-Flop Outputs
	12, 15
	3, 4, 6, 11,	D0 to D5	Data Inputs
	13, 14
	9	CLOCK	Clock Input (LOW-to-HIGH,
			Edge Triggered)
	8	GND	Ground (0V)
	16	VCC	Positive Supply Voltage

Table 3: Truth Table

			INPUTS					OUTPUTS	FUNCTION
	CLEAR		D	CLOCK				Q
	L		X		X			L	CLEAR
	H		L					L
	H		H					H
	H		X					Qn	NO CHANGE

X : Don’t Care

Figure 3: Logic Diagram

This logic diagram has not to be used to estimate propagation delays

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				74VHC174
Table 4: Absolute Maximum Ratings
Symbol	Parameter	Value			Unit
VCC	Supply Voltage	-0.5 to +7.0			V
VI	DC Input Voltage	-0.5 to +7.0			V
VO	DC Output Voltage	-0.5 to VCC + 0.5			V
IIK	DC Input Diode Current	- 20			mA
IOK	DC Output Diode Current	±	20		mA
IO	DC Output Current	±	25		mA
ICC or IGND	DC VCC or Ground Current	±	50		mA
Tstg	Storage Temperature	-65 to +150			°C
TL	Lead Temperature (10 sec)	300			°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

Table 5: Recommended Operating Conditions

	Symbol	Parameter		Value	Unit
	VCC	Supply Voltage		2 to 5.5	V
	VI	Input Voltage		0 to 5.5	V
	VO	Output Voltage		0 to VCC	V
	Top	Operating Temperature		-55 to 125	°C
	dt/dv	Input Rise and Fall Time (note 1) (VCC = 3.3 ±	0.3V)	0 to 100	ns/V
		(VCC = 5.0 ±	0.5V)	0 to 20

1) VIN from 30% to 70% of VCC

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74VHC174

Table 6: DC Specifications

			Test Condition							Value
Symbol	Parameter	VCC				TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
		(V)			Min.		Typ.	Max.		Min.	Max.	Min.	Max.
VIH	High Level Input	2.0			1.5					1.5		1.5
	Voltage	3.0 to			0.7VCC					0.7VCC		0.7VCC		V
		5.5
VIL	Low Level Input	2.0							0.5		0.5		0.5
	Voltage	3.0 to						0.3VCC			0.3VCC		0.3VCC	V
		5.5
VOH	High Level Output	2.0		IO=-50 A	1.9		2.0			1.9		1.9
	Voltage
		3.0		IO=-50 A	2.9		3.0			2.9		2.9
		4.5		IO=-50 A	4.4		4.5			4.4		4.4		V
		3.0		IO=-4 mA	2.58					2.48		2.4
		4.5		IO=-8 mA	3.94					3.8		3.7
VOL	Low Level Output	2.0		IO=50 A			0.0		0.1		0.1		0.1
	Voltage
		3.0		IO=50 A			0.0		0.1		0.1		0.1
		4.5		IO=50 A			0.0		0.1		0.1		0.1	V
		3.0		IO=4 mA				0.36			0.44		0.55
		4.5		IO=8 mA				0.36			0.44		0.55
II	Input Leakage	0 to		VI = 5.5V or GND				±	0.1		± 1		± 1	A
	Current	5.5
ICC	Quiescent Supply	5.5		VI = VCC or GND					4		40		40	A
	Current

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74VHC174

Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)

					Test Condition								Value
Symbol		Parameter			VCC	CL			TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
					(V)	(pF)		Min.		Typ.	Max.		Min.	Max.	Min.	Max.
tPLH		Propagation Delay			3.3(*)	15				5.8		11.0	1.0	13.0	1.0	13.0
tPHL		Time
					3.3(*)	50				7.5		14.5	1.0	16.5	1.0	16.5
		CLOCK to Q															ns
					5.0(**)	15				4.1		7.2	1.0	8.5	1.0	8.5
					5.0(**)	50				5.5		9.2	1.0	10.5	1.0	10.5
tPHL		Propagation Delay			3.3(*)	15				7.4		11.4	1.0	13.5	1.0	13.5
		Time
					3.3(*)	50				9.9		14.9	1.0	17.0	1.0	17.0
		CLEAR to Q															ns
					5.0(**)	15				5.1		7.6	1.0	9.0	1.0	9.0
					5.0(**)	50				6.6		9.6	1.0	11.0	1.0	11.0
tW		CLEAR	Pulse		3.3(*)							5.0		5.0		5.0	ns
		Width LOW
					5.0(**)							5.0		5.0		5.0
tW		CLEAR Pulse			3.3(*)							5.0		5.0		5.0
		Width HIGH or															ns
					5.0(**)							5.0		5.0		5.0
		LOW
ts		Setup Time D to			3.3(*)							5.0		6.0		6.0	ns
		CLOCK, HIGH or
					5.0(**)							4.5		4.5		4.5
		LOW
th		Hold Time D to			3.3(*)							0.0		0.0		0.0	ns
		CLOCK, HIGH or
					5.0(**)							0.5		0.5		0.5
		LOW
tREM		Recovery Time			3.3(*)							3.0		3.0		3.0	ns
		CLEAR to CLOCK
					5.0(**)							2.5		2.5		2.5
fMAX		Maximum Clock			3.3(*)	15		95		150			80		80
		Frequency
					3.3(*)	50		55		85			50		50		MHz
					5.0(**)	15		130		175			110		110
					5.0(**)	50		90		120			80		80
(*) Voltage range is 3.3V ±				0.3V
(**) Voltage range is 5.0V ±				0.5V
Table 8: Capacitive Characteristics
					Test Condition								Value
Symbol		Parameter							TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
								Min.		Typ.	Max.		Min.	Max.	Min.	Max.
CIN		Input Capacitance								6		10		10		10	pF
CPD		Power Dissipation								15							pF
		Capacitance
		(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/6 (per Flip-Flop)

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