ST 74VHC16373 User Manual

74VHC16373

74VHC16373

16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING

■HIGH SPEED:

tPD = 5.0 ns (TYP.) at VCC = 5V

■LOW POWER DISSIPATION: ICC = 4 μA (MAX.) at TA=25°C

■HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)

■POWER DOWN PROTECTION ON INPUTS

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373

■IMPROVED LATCH-UP IMMUNITY

■LOW NOISE: VOLP = 0.9V (MAX.)

DESCRIPTION

The 74VHC16373 is an advanced high-speed CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(nOE).

While the nLE input is held at a high level, the nQ outputs will follow the data (D) inputs.

When the nLE is taken LOW, the nQ outputs will be latched at the logic level of D data inputs. When the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level); when nOE is at high level ,the outputs will be in a high impedance state.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

TSSOP

ORDER CODES

PACKAGE	TUBE	T & R
TSSOP		74VHC16373TTR

PIN CONNECTION

February 2003

1/11

74VHC16373

INPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION			IEC LOGIC SYMBOLS
PIN No	SYMBOL	NAME AND FUNCTION
1	1OE	3 State Output Enable
		Input (Active LOW)
2, 3, 5, 6, 8, 9,	1Q0 to 1Q7	3-State Outputs
11, 12
13, 14, 16, 17,	2Q0 to 2Q7	3-State Outputs
19, 20, 22, 23
24	2OE	3 State Output Enable
		Input (Active LOW)
25	2LE	Latch Enable Input
36, 35, 33, 32,	2D0 to 2D7	Data Inputs
30, 29, 27, 26
47, 46, 44, 43,	1D0 to 1D7	Data Inputs
41, 40, 38, 37
48	1LE	Latch Enable Input
4, 10, 15, 21,	GND	Ground (0V)
28, 34, 39, 45
7, 18, 31, 42	VCC	Positive Supply Voltage
TRUTH TABLE
	INPUTS		OUTPUT
OE	LE	D	Q
H	X	X	Z
L	L	X	NO CHANGE *
L	H	L	L
L	H	H	H
X : Don‘t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.

2/11

74VHC16373

LOGIC DIAGRAM

This logic diagram has not to be used to estimate propagation delays

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	-0.5 to +7.0	V
VI	DC Input Voltage	-0.5 to +7.0	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	- 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Current	± 25	mA
ICC or IGND	DC VCC or Ground Current	± 75	mA
Tstg	Storage Temperature	-65 to +150	°C
TL	Lead Temperature (10 sec)	300	°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

RECOMMENDED OPERATING CONDITIONS

	Symbol	Parameter	Value	Unit
	VCC	Supply Voltage	2 to 5.5	V
	VI	Input Voltage	0 to 5.5	V
	VO	Output Voltage	0 to VCC	V
	Top	Operating Temperature	-55 to 125	°C
	dt/dv	Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V)	0 to 100	ns/V
		(VCC = 5.0 ± 0.5V)	0 to 20

1) VIN from 30% to 70% of VCC

3/11

74VHC16373

DC SPECIFICATIONS

			Test Condition						Value
Symbol	Parameter	VCC				TA = 25°C			-40 to 85°C		-55 to 125°C		Unit
		(V)			Min.		Typ.	Max.	Min.	Max.	Min.	Max.
VIH	High Level Input	2.0			1.5				1.5		1.5
	Voltage	3.0 to			0.7VCC				0.7VCC		0.7VCC		V
		5.5
VIL	Low Level Input	2.0						0.5		0.5		0.5
	Voltage	3.0 to						0.3VCC		0.3VCC		0.3VCC	V
		5.5
VOH	High Level Output	2.0		IO=-50 μA	1.9		2.0		1.9		1.9
	Voltage
		3.0		IO=-50 μA	2.9		3.0		2.9		2.9
		4.5		IO=-50 μA	4.4		4.5		4.4		4.4		V
		3.0		IO=-4 mA	2.58				2.48		2.4
		4.5		IO=-8 mA	3.94				3.8		3.7
VOL	Low Level Output	2.0		IO=50 μA			0.0	0.1		0.1		0.1
	Voltage
		3.0		IO=50 μA			0.0	0.1		0.1		0.1
		4.5		IO=50 μA			0.0	0.1		0.1		0.1	V
		3.0		IO=4 mA				0.36		0.44		0.55
		4.5		IO=8 mA				0.36		0.44		0.55
IOZ	High Impedance	5.5		VI = VIH or VIL				±0.25		± 2.5		± 5	μA
	Output Leakage			VO = VCC or GND
	Current
II	Input Leakage	0 to		VI = 5.5V or GND				± 0.1		± 1		± 1	μA
	Current	5.5
ICC	Quiescent Supply	5.5		VI = VCC or GND				4		40		40	μA
	Current

4/11