The 74VHC02 is an advanced high-speed CMOS
QUAD 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer ou tput, whi ch provid es hig h no ise
immunity and stable output.
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74VHC02MTR
TSSOP74VHC02TTR
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.
2, 5, 8, 111A to 4AData Inputs
3, 6, 9, 121B to 4BData Inputs
1, 4, 10, 131Y to 4YData Outputs
7GNDGround (0V)
14
Table 3: Truth Table
ABY
LLH
LHL
HLL
HHL
Table 4: Absolute Maximum Ratings
SymbolParameterValueUnit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Table 5: Recommended Operating Conditions
V
CC
Positive Supply Voltage
-0.5 to +7.0V
-0.5 to +7.0V
- 20mA
± 20mA
± 25mA
± 50mA
-65 to +150°C
300°C
V
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) VIN from 30 % t o 70% of V
Supply Voltage
CC
Input Voltage
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 1) (V
(V
CC
= 3.3 ± 0.3V)
CC
= 5.0 ± 0.5V)
CC
2 to 5.5V
0 to 5.5V
CC
-55 to 125°C
0 to 100
0 to 20
2/11
V
ns/V
Table 6: DC Specifications
SymbolParameter
V
V
V
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
I
Quiescent Supply
CC
Current
V
3.0 to
3.0 to
0 to
74VHC02
Test ConditionValue
= 25°C
T
CC
(V)
A
Min.Typ. Max.Min.Max. Min. Max.
2.01.51.51.5
0.7V
5.5
CC
2.00.50.50.5
5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
VI = 5.5V or GND
5.5
V
5.5
IO=-50 µA
I
=-50 µA
O
=-50 µA
I
O
=-4 mA
I
O
=-8 mA
I
O
IO=50 µA
=50 µA
I
O
=50 µA
I
O
=4 mA
I
O
=8 mA
I
O
= VCC or GND
I
1.92.01.91.9
2.93.02.92.9
4.44.54.44.4
2.582.482.4
3.943.83.7
0.3V
0.00.10.10.1
0.00.10.10.1
0.00.10.10.1
-40 to 85°C -55 to 125°C
CC
0.7V
CC
0.3V
CC
0.7V
CC
0.3V
0.360.440.55
0.360.440.55
± 0.1± 1± 1µA
22020µA
CC
Unit
V
V
V
V
Table 7: AC Electrical Characteristics (Input t
Test ConditionValue
SymbolParameter
t
PLH tPHL
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ±
Propagation Delay
Time
0.5V
V
3.3
3.3
5.0
5.0
C
CC
(V)
L
(pF)
(*)
155.67.91.09.51.09.5
(*)
508.111.41.013.01.013.0
(**)
153.65.51.06.51.06.5
(**)
504.57.51.08.51.08.5
= tf = 3ns)
r
= 25°C
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
Unit
ns
3/11
74VHC02
Table 8: Capacitive Characteristics
Test ConditionValue
= 25°C
SymbolParameter
T
A
Min.Typ. Max.Min.Max. Min. Max.
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance
6101010pF
19pF
(note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Table 9: Dynamic Switching Characteristics
Test ConditionValue
= 25°C
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
Dynamic High
V
IHD
Voltage Input
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
(note 1, 3)
V
CC
(V)
5.0
= 50 pF
5.03.5V
C
L
5.01.5V
T
A
Min.Typ. Max.Min.Max. Min. Max.
0.30.8
-0.8-0.3
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/4 (per gate)
CC(opr)
-40 to 85°C -55 to 125°C
Unit
Unit
V
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 5.0V, (n-1) outputs switc hi ng and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
(V
), f=1MHz.
IHD
ILD
Figure 3: Test Circuit
CL =15/ 50pF or e qui valent (includes jig an d probe capacit ance)
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