ST 74V1T80 User Manual
74V1T80
74V1T80
SINGLE POSITIVE EDGE TRIGGERED
D-TYPE FLIP-FLOP
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HIGH SPEED: |
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fMAX = 180MHz (TYP.) at VCC = 5V |
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LOW POWER DISSIPATION: |
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ICC = 1μA(MAX.) at TA=25°C |
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■ COMPATIBLE WITH TTL OUTPUTS: |
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VIH = 2V (MIN), VIL = 0.8V (MAX) |
SOT23-5L |
SOT323-5L |
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POWER DOWN PROTECTION ON INPUTS |
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SYMMETRICAL OUTPUT IMPEDANCE: |
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|IOH| = IOL = 8mA (MIN) at VCC = 4.5V |
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■BALANCED PROPAGATION DELAYS: tPLH tPHL
■OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V
■IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1T80 is an advanced high-speed CMOS SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH INVERTED OUTPUT fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. it is designed to operate from 4.5V to 5.5V, making this device ideal for portable applications.
This D-Type flip-flop is controlled by a clock input (CK). On the positive transition of the clock, the Q output will be set to the logic inverted state that was setup at the D input.
ORDER CODES
PACKAGE |
T & R |
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SOT23-5L |
74V1T80STR |
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SOT323-5L |
74V1T80CTR |
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Following the hold time interval, data at the D input can be changed without affecting the level at the output. Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface 5V to 3V.
It’s available in the commercial temperature range. All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001 |
1/9 |
74V1T80
INPUT EQUIVALENT CIRCUIT |
PIN DESCRIPTION |
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PIN No |
SYMBOL |
NAME AND FUNCTION |
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D |
Data Input |
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2 |
CK |
Clock Input (Positive |
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Edge) |
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4 |
Q |
Inverted Flip-Flop Output |
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3 |
GND |
Ground (0V) |
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5 |
VCC |
Positive Supply Voltage |
TRUTH TABLE
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D |
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CK |
Q |
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L |
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L |
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Qn |
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H |
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Qn |
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ABSOLUTE MAXIMUM RATINGS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7.0 |
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VI |
DC Input Voltage |
-0.5 to +7.0 |
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VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
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IIK |
DC Input Diode Current |
- 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Current |
± 25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
mA |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature (10 sec) |
300 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
4.5 to 5.5 |
V |
VI |
Input Voltage |
0 to 5.5 |
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VO |
Output Voltage |
0 to VCC |
V |
Top |
Operating Temperature |
-55 to 125 |
°C |
dt/dv |
Input Rise and Fall Time (note 1) (VCC = 5.0 ± 0.5V) |
0 to 20 |
ns/V |
1) VIN from 0.8V to 2V
2/9
74V1T80
DC SPECIFICATIONS
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
-40 to 85°C |
-55 to 125°C |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
4.5 to |
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2 |
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2 |
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2 |
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V |
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Voltage |
5.5 |
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VIL |
Low Level Input |
4.5 to |
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0.8 |
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0.8 |
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0.8 |
V |
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Voltage |
5.5 |
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VOH |
High Level Output |
4.5 |
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IO=-50 μA |
4.4 |
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4.5 |
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4.4 |
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4.4 |
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V |
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Voltage |
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4.5 |
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IO=-8 mA |
3.94 |
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3.8 |
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3.7 |
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VOL |
Low Level Output |
4.5 |
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IO=50 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
V |
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Voltage |
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4.5 |
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IO=8 mA |
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0.36 |
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0.44 |
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0.55 |
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II |
Input Leakage |
0 to |
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VI = 5.5V or GND |
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± 0.1 |
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± 1.0 |
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± 1.0 |
μA |
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Current |
5.5 |
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ICC |
Quiescent Supply |
5.5 |
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VI = VCC or GND |
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1 |
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10 |
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20 |
μA |
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Current |
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ICC |
Additional Worst |
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One Input at 3.4V, |
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1.35 |
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1.5 |
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1.5 |
mA |
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Case Supply |
5.5 |
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other input at VCC |
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Current |
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or GND |
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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CL |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
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(V) |
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(pF) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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tPLH tPHL |
Propagation Delay |
5.0 (*) |
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15 |
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4.9 |
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8.4 |
1.0 |
9.8 |
1.0 |
10.8 |
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Time CK to Q |
5.0 (*) |
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50 |
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5.9 |
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12.0 |
1.0 |
14.0 |
1.0 |
15.0 |
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tW |
CK Pulse Width, |
5.0 (*) |
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50 |
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4.0 |
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4.0 |
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4.0 |
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ns |
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HIGH or LOW |
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Setup Time D to |
5.0 (*) |
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50 |
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4.0 |
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4.0 |
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4.0 |
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ns |
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CK, HIGH or LOW |
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Hold Time D to CK, |
5.0 (*) |
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50 |
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1.0 |
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1.0 |
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1.0 |
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ns |
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HIGH or LOW |
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fMAX |
Maximum Clock |
5.0 (*) |
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50 |
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165 |
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180 |
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150 |
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150 |
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MHz |
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Frequency |
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(*) Voltage |
range is 5.0V ± 0.5V |
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CAPACITIVE CHARACTERISTICS |
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Test Condition |
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Value |
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Symbol |
Parameter |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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CIN |
Input Capacitance |
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4 |
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10 |
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10 |
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10 |
pF |
CPD |
Power Dissipation |
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8 |
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pF |
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Capacitance |
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(note 1) |
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1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
3/9
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