74V1G77
74V1G77
SINGLE D-TYPE LATCH
■HIGH SPEED: tPD = 4.4ns (TYP.) at VCC = 5V
■LOW POWER DISSIPATION: ICC = 1μA(MAX.) at TA=25°C
■HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
■POWER DOWN PROTECTION ON INPUTS
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V
■IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
SOT23-5L SOT323-5L
ORDER CODES
PACKAGE |
T & R |
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SOT23-5L |
74V1G77STR |
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SOT323-5L |
74V1G77CTR |
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The 74V1G77 is an advanced high-speed CMOS SINGLE D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is designed to operate from 2V to 5.5V, making this device ideal for portable applications.
The single D-Type latch is controlled by a Latch Enable Input (LE).
While the LE input is held at a high level, the Q output will follow the data input precisely. When
the LE input is taken low the Q output is latched precisely at the logic level of D input data.
Power down protection is provided on inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It’s available in the commercial and extended temperature range.
All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001 |
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74V1G77
INPUT EQUIVALENT CIRCUIT |
PIN DESCRIPTION |
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PIN No |
SYMBOL |
NAME QND FUNCTION |
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1 |
D |
Data Input |
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2 |
LE |
Latch Enable Input |
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4 |
Q |
Data Output |
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3 |
GND |
Ground (0V) |
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5 |
VCC |
Positive Supply Voltage |
TRUTH TABLE |
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D |
LE |
Q |
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L |
L |
No Change * |
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H |
L |
No Change * |
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L |
H |
Qn |
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H |
H |
Qn |
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(*) Q output is latched at the time when the le input is taken low logic |
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level. |
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ABSOLUTE MAXIMUM RATINGS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7.0 |
V |
VI |
DC Input Voltage |
-0.5 to +7.0 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
- 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Current |
± 25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
mA |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature (10 sec) |
260 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
2 to 5.5 |
V |
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VI |
Input Voltage |
0 to 5.5 |
V |
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VO |
Output Voltage |
0 to VCC |
V |
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Top |
Operating Temperature |
-55 to 125 |
°C |
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dt/dv |
Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) |
0 to 100 |
ns/V |
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(VCC = 5.0 ± 0.5V) |
0 to 20 |
ns/V |
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1) VIN from 30% to 70% of VCC
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74V1G77
DC SPECIFICATIONS
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
2.0 |
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1.5 |
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1.5 |
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1.5 |
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Voltage |
3.0 to |
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0.7VCC |
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0.7VCC |
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0.7VCC |
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V |
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5.5 |
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VIL |
Low Level Input |
2.0 |
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0.5 |
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0.5 |
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0.5 |
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Voltage |
3.0 to |
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0.3VCC |
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0.3VCC |
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0.3VCC |
V |
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5.5 |
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VOH |
High Level Output |
2.0 |
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IO=-50 μA |
1.9 |
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2.0 |
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1.9 |
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1.9 |
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Voltage |
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3.0 |
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IO=-50 μA |
2.9 |
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3.0 |
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2.9 |
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2.9 |
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4.5 |
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IO=-50 μA |
4.4 |
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4.5 |
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4.4 |
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4.4 |
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V |
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3.0 |
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IO=-4 mA |
2.58 |
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2.48 |
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2.4 |
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4.5 |
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IO=-8 mA |
3.94 |
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3.8 |
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3.7 |
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VOL |
Low Level Output |
2.0 |
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IO=50 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
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Voltage |
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3.0 |
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IO=50 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
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4.5 |
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IO=50 μA |
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0.0 |
0.1 |
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0.1 |
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0.1 |
V |
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3.0 |
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IO=4 mA |
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0.36 |
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0.44 |
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0.55 |
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4.5 |
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IO=8 mA |
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0.36 |
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0.44 |
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0.55 |
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II |
Input Leakage |
0 to |
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VI = 5.5V or GND |
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± 0.1 |
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± 1 |
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± 1 |
μA |
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Current |
5.5 |
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ICC |
Quiescent Supply |
5.5 |
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VI = VCC or GND |
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1 |
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10 |
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20 |
μA |
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Current |
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
CL |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
(pF) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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tPLH tPHL |
Propagation Delay |
3.3(*) |
15 |
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6.2 |
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9.0 |
1.0 |
10.5 |
1.0 |
11.5 |
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Time LE to Q |
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3.3(*) |
50 |
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6.8 |
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10.0 |
1.0 |
11.5 |
1.0 |
13.0 |
ns |
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5.0(**) |
15 |
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4.4 |
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6.5 |
1.0 |
7.5 |
1.0 |
8.5 |
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5.0(**) |
50 |
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4.8 |
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7.0 |
1.0 |
8.0 |
1.0 |
9.0 |
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tPLH tPHL |
Propagation Delay |
3.3(*) |
15 |
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7.2 |
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10.0 |
1.0 |
11.5 |
1.0 |
13.0 |
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Time D to Q |
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3.3(*) |
50 |
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7.9 |
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11.0 |
1.0 |
12.5 |
1.0 |
14.0 |
ns |
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5.0(**) |
15 |
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4.4 |
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6.5 |
1.0 |
7.5 |
1.0 |
8.5 |
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5.0(**) |
50 |
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4.8 |
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7.0 |
1.0 |
8.0 |
1.0 |
9.0 |
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tW |
LE Pulse Width, |
3.3(*) |
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4.0 |
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4.0 |
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4.0 |
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ns |
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HIGH |
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5.0(**) |
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3.0 |
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3.0 |
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3.0 |
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ts |
Setup Time D to |
3.3(*) |
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3.0 |
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3.0 |
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3.0 |
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ns |
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LE, HIGH or LOW |
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5.0(**) |
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2.0 |
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2.0 |
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2.0 |
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th |
Hold Time D to LE, |
3.3(*) |
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1.0 |
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1.0 |
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1.0 |
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ns |
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HIGH or LOW |
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5.0(**) |
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1.0 |
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1.0 |
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1.0 |
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(*) Voltage |
range is 3.3V ± 0.3V |
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(**) Voltage range is 5.0V ± 0.5V |
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3/10 |
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