ST 74LVX74 User Manual
74LVX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH PRESET AND CLEAR (5V TOLERANT INPUTS)
■ HIGH SPEED:
f
= 145MHz (TYP.) at V
MAX
■ 5V TOLERANT INPUTS
■ INPUT VOLTAGE LEVEL:
V
=0.8V , VIH=2V AT VCC=3V
IL
■ LOW POWER DISSIPATION:
I
= 2 µA (MAX.) at TA=25°C
CC
■ LOW NOISE:
V
= 0.3V (TYP.) at VCC = 3.3V
OLP
■ SYMMETRICAL OUTPUT IMPEDANCE:
| = IOL = 4mA (MIN)
|I
OH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
PHL
■ OPERATING VOLTAGE RAN GE:
(OPR) = 2V to 3.6V (1.2V Data Retention)
V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
CC
= 3.3V
74 SERIES 74
■ IMPROVED LATCH-UP IMMUN ITY
■ POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX74 is a low voltage CMOS DUAL
D-TYPE FLIP-FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
TSSOPSOP
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX74MTR
TSSOP 74LVX74TTR
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse. CLR
and PR are indep endent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are eq uipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Sym bols
Rev. 3
1/13August 2004
74LVX74
Figure 2: Input Equivalent Circuit Table 2: Pin Description
PIN N° SYMBOL NAME AND FUNCTION
Asynchronous Reset Direct Input
(LOW to HIGH, Edge
Triggered)
Input
Outputs
Positive Supply Voltage
Table 3: Truth Table
1, 13 1CLR
, 2CLR
2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK Clock Input
4, 10 1PR
, 2PR Asynchronous Set - Direct
5, 9 1Q, 2Q True Flip-Flop Outputs
6, 8 1Q
, 2Q Complement Flip-Flop
7 GND Ground (0V)
14 V
CC
INPUTS OUTPUTS
FUNCTION
CLR
PR DCKQ Q
LHXXLH CLEAR
H L X X H L PRESET
LLXXHH
HHL LH
HHH HL
HHX
X : Don’t Care
Q
n
Q
n
NO CHANGE
Figure 3: Logic Diagram
This logi c di agram has not be used to est i m ate propagation delays
2/13
74LVX74
Table 4: Absolute Maximum Ratings
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Table 5: Recommended Operating Conditions
Symbol Parameter Value Unit
V
V
V
T
dt/dv
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage (note 1)
CC
Input Voltage
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 2) (V
= 3.3V)
CC
-0.5 to +7.0 V
-0.5 to +7.0 V
- 20 mA
± 20 mA
± 25 mA
± 50 mA
-65 to +150 °C
300 °C
2 to 3.6 V
0 to 5.5 V
CC
-55 to 125 °C
0 to 100 ns/V
V
V
1) Truth T abl e guarante ed: 1.2V to 3.6V
2) V
from 0.8V to 2.0V
IN
Table 6: DC Specifications
Symbol Parameter
V
V
V
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
Input Leakage
I
I
Current
Quiescent Supply
I
CC
Current
Test Condition Value
V
(V)
CC
T
A
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85°C -55 to 125°C
= 25°C
2.0 1.5 1.5 1.5
3.6 2.4 2.4 2.4
2.0 0.5 0.5 0.5
3.6 0.8 0.8 0.8
2.0
3.0
2.0
3.0
3.6
3.6
IO=-50 µA
I
=-50 µA
O
=-4 mA
I
O
=50 µA
I
O
=50 µA
I
O
I
=4 mA
O
= 5V or GND
V
I
= VCC or GND
V
I
1.9 2.0 1.9 1.9
2.9 3.0 2.9 2.9
2.58 2.48 2.4
0.0 0.1 0.1 0.1
0.0 0.1 0.1 0.1
0.36 0.44 0.55
± 0.1 ± 1 ± 1 µA
22020µA
Unit
V3.0 2.0 2.0 2.0
V3.0 0.8 0.8 0.8
V3.0
V3.0
3/13
74LVX74
Table 7: Dynamic Switching Characteristics
Test Condition Value
= 25°C
Symbol Parameter
V
CC
(V)
V
V
V
V
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inp ut s are driven 0V to 3.3V, (n-1) outputs switc hi ng and one out put at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
(V
IHD
Dynamic Low Voltage
OLP
Quiet Output (note 1, 2)
OLV
Dynamic High Voltage
IHD
Input (note 1, 3)
Dynamic Low Voltage
ILD
Input (note 1, 3)
), f=1MHz.
3.3
3.3 2
= 50 pF
C
L
3.3 0.8
T
A
Min. Typ. Max. Min. Max. Min. Max.
0.3 0.5
-0.5 -0.3
Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)
Test Condition Value
= 25°C
Symbol Parameter
t
PLH tPHL
t
PLH tPHL
t
t
REM
f
t
OSLH
t
OSHL
Propagation Delay Time
CK to Q or Q
Propagation Delay Time
PR or CLR to Q or Q
t
Minimum Pulse Width
w
HIGH or LOW, CK
Minimum Pulse Width
w(L)
LOW PR
t
Minimum Setup Time D
s
to CK HIGH or LOW
t
Minimum Hold Time D
h
to CK HIGH or LOW
Minimum Removal Time
or CLR to CK
PR
Maximum Clock
MAX
Frequency
Output To Output Skew
Time (note1, 2)
or CLR
C
V
CC
(V)
L
(pF)
2.7 15 7.3 15.0 1.0 18.5 1.0 18.5
2.7 50 9.8 18.5 1.0 22.0 1.0 22.0
(*)
3.3
3.3
15 5.7 9.7 1.0 11.5 1.0 11.5
(*)
50 8.2 13.2 1.0 15.0 1.0 15.0
2.7 15 8.4 15.6 1.0 18.5 1.0 18.5
2.7 50 10.9 19.1 1.0 22.0 1.0 22.0
(*)
3.3
3.3
15 6.6 10.1 1.0 12.0 1.0 12.0
(*)
50 9.1 13.6 1.0 15.5 1.0 15.5
2.7 50 8.5 10.0 10.0
(*)
3.3
50
2.7 50 8.5 10.0 10.0
(*)
3.3
50
2.7 50 8.0 9.5 9.5
(*)
3.3
50
2.7 50 0.5 0.5 0.5
(*)
3.3
50
2.7 50 6.5 7.5 7.5
(*)
3.3
50
2.7 15 55 135 50 50
2.750 45604040
(*)
3.3
3.3
15 95 145 80 80
(*)
50 60 85 50 50
2.7 50 0.5 1.0 1.5 1.5
(*)
3.3
50
T
A
Min. Typ. Max. Min. Max. Min. Max.
0.5 1.0 1.5 1.5
-40 to 85°C -55 to 125°C
ILD
-40 to 85°C -55 to 125°C
6.0 7.0 7.0
6.0 7.0 7.0
5.5 6.5 6.5
0.5 0.5 0.5
5.0 5.0 5.0
Unit
V
), 0V to thresho l d
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the sa m e di rection, ei ther HIGH or LOW
2) Param eter guaran teed by design
(*) Voltage range is 3.3V ±
0.3V
4/13
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