ST 74LVX273 User Manual

74LVX273

LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP

WITH CLEAR (5V TOLERANT INPUTS)

■ HIGH SPEED:

f

= 150 MHz (TYP.) at VCC = 3.3V

MAX

■ 5V TOLERANT INPUTS

■ POWER-DOWN PROTECTION ON INPUTS

■ INPUT VOLTAGE LEVEL:

V

= 0.8V, VIH = 2V at VCC =3V

IL

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ LOW NOISE:

V

= 0.3V (TYP.) at VCC =3.3V

OLP

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 4 mA (MIN) at VCC =3V

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

PHL

■ OPERATING VOL TAGE R AN GE:

V

(OPR) = 2V to 3.6V (1.2V Data Retention)

CC

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 273

■ IMPROVED LATCH-UP IMMU N ITY

DESCRIPTION

The 74LVX273 is a low voltage CMOS OCTAL D-TYPE FLIP-FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C

2

MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. Information signals applied to D inputs are

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74LVX273MTR

TSSOP 74LVX273TTR

transferred to the Q o utputs on the positive going edge of the clock pulse. When the CLE AR

input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static disc harge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Con nection An d I E C Logic Symb ols

Rev. 3

1/12August 2004

74LVX273

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

Table 3: Truth Tabl e

1CLEAR

2, 5, 6, 9, 12,

15, 16,19

3, 4, 7, 8, 13,

14, 17, 18

1 1 CLOCK Clock Input (LOW-to-HIGH

10 GND Ground (0V) 20 V

Q0 to Q7 Flip-Flop Outputs

D0 to D7 Data Inputs

CC

Asynchronous Master Reset (Active LOW)

Edge Triggered)

Positive Supply Voltage

CLEAR

L X X L CLEAR

HL L HH H HX

X : Don’t Care

Figure 3: Logic Diagram

INPUTS OUTPUT

DBQ

Q

n

FUNCTION

NO CHANGE

This logi c di agram has not be used to est i m ate propagation delays

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74LVX273

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

I

OK

I

or I

I

CC

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V V T

dt/dv

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (note 2) (V

CC

= 3V)

-0.5 to +7.0 V

- 20 mA

± 20 mA ± 25 mA ± 50 mA

-65 to +150 °C 300 °C

2 to 3.6 V 0 to 5.5 V

CC

-55 to 125 °C 0 to 100 ns/V

V

1) Truth T abl e guarante ed: 1.2V to 3.6V from 0.8V to 2.0V

2) V

IN

Table 6: DC Specifications

Symbol Parameter

V

High Level Input

IH

Voltage

V

Low Level Input

IL

Voltage

High Level Output

OH

Voltage

Low Level Output

OL

Voltage

I

Input Leakage

I

Current

I

Quiescent Supply

CC

Current

Test Condition Value

V

(V)

CC

T

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

= 25°C

2.0 1.5 1.5 1.5

2.0 2.0 2.0

3.6

2.4 2.4 2.4

2.0 0.5 0.5 0.5

3.6 0.8 0.8 0.8 =-50 µA

2.0

3.0

2.0

3.0

3.6

I

O

=-50 µA

I

O

I

=-4 mA

O

IO=50 µA

=50 µA

I

O

=4 mA

I

O

= 5V or GND

V

I

= VCC or GND

V

I

1.9 2.0 1.9 1.9

2.9 3.0 2.9 2.9

2.58 2.48 2.4

0.0 0.1 0.1 0.1

0.36 0.44 0.55

± 0.1 ± 1 ± 1 µA

44040µA

Unit

V3.0

V3.0 0.8 0.8 0.8

V3.0

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74LVX273

Table 7: Dynamic Switching Characteristics

Test Condition Value

= 25°C

Symbol Parameter

V

CC

(V)

V V

V

1) Worst case package.

2) Max number of outp ut s defined as (n). Data inp ut s are driven 0V to 3.3V, (n-1) outputs switc hi ng and one out put at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V (V

IHD

Dynamic Low Voltage

OLP

Quiet Output (note 1, 2)

OLV

Dynamic High Voltage

IHD

Input (note 1, 3) Dynamic Low Voltage

ILD

Input (note 1, 3)

), f=1MHz.

3.3

= 50 pF

C

3.3 2.0

L

3.3 0.8

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.8

-0.8 -0.3

Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)

Test Condition Value

= 25°C

Symbol Parameter

t

Propagation Delay

PLH

t

t f

t

OSLH

t

OSHL

Time

PHL

CK to Q

Propagation Delay

PHL

Time CLEAR

CLEAR pulse Width,

W(L)

HIGH CLOCK pulse Width,

t

W

HIGH Setup Time Q to

t

S

CLOCK HIGH or LOW Hold Time Q to

t

h

CLOCK HIGH or LOW Recovery Time

REM

CLEAR Maximum Clock

MAX

Frequency

Output to Output Skew Time (note 1,2)

to Q

C

V

CC

(V)

L

(pF)

2.7 15 9.0 16.9 1.0 20.5 1.0 22.0

2.7 50 11.5 20.4 1.0 24.0 1.0 25.5

(*)

3.3

5.0

3.3

15 7.1 11.0 1.0 13.0 1.0 14.5

(*)

50 9.6 14.5 1.0 16.5 1.0 18.0

(*)

15 9.3 17.6 1.0 20.5 1.0 22.0

(*)

50 11.8 21.1 1.0 24.0 1.0 25.5

(**)

15 7.3 11.5 1.0 13.5 1.0 15.5

(**)

50 9.8 15.0 1.0 17.0 1.0 18.0

2.7 50

(*)

2.7 50

(*)

2.7 50

(*)

2.7 50

(*)

2.7 50

(*)

2.7 15 55 110 55 50

2.750 45604035

(*)

3.3

15 95 150 80 75

(*)

50 60 90 55 50

2.7 50 0.5 1.0 1.5 1.5

(*)

3.3

50 0.5 1.0 1.5 1.5

T

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

ILD

-40 to 85°C -55 to 125°C

5.0 6.0 6.0

5.0 5.0 5.0

5.5 6.5 6.5

5.0 5.0 5.0

5.5 6.5 6.5

4.5 4.5 4.5

1.0 1.0 1.0

2.5 2.5 2.5

2.0 2.0 2.0

Unit

V

), 0V to thresho l d

Unit

ns

MHz

ns

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the sa m e di rection, ei ther HIGH or LOW

2) Param eter guaran teed by design (*) Voltage range is 3.3V ±

0.3V

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