ST 74LVX238 User Manual
1/12August 2004
■ HIGH SPEED:
t
PD
= 5.5ns (TYP.) at V
CC
= 3.3V
■ 5V TOLERANT INPUTS
■ INPUT VOLTAGE LEVEL:
V
IL
=0.8V , V
IH
=2V at V
CC
=3V
■ LOW POWER DISSIPATION:
I
CC
= 2 µA (MAX.) at T
A
=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
■ IMPROVED LATCH-UP IMMUN ITY
■ POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX238 is a low voltage CMOS 3 TO 8
LINE DECODER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
If the device is enabled, 3 binary select (A, B, and
C) determine which one of the outputs will go high.
If enable input G1 is held low or either G2A
or G2B
is held high, the decoding function is inhibited and
all the 8 outputs go low.
Tree enable inpu ts are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX238
LOW VOLTAGE CMOS 3 TO 8 LINE DECODER
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection An d I E C Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX238MTR
TSSOP 74LVX238TTR
TSSOPSOP
Rev. 2
74LVX238
2/12
Figure 2: Input Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table
X : Don’t Care
Figure 3: Logic Diagram
This logi c di agram has not be used to est i m ate propagation delays
PIN N° SYMBOL NAME AND FUNCTION
1, 2, 3 A, B, C Address Inputs
4, 5 G2A
, G2B Enable Inputs
6 G1 Enable Input
15, 14, 13,
12, 1 1, 10, 9,
7
Y0 to Y7 Outputs
8 GND Ground (0V)
16 V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
ENABLE SELECT
G2B
G2A G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXLXXXLLLLLLLL
XHXXXXLLLLLLLL
HXXXXXLLLLLLLL
LLHLLLHLLLLLLL
LLHLLHLHLLLLLL
LLHLHLLLHLLLLL
LLHLHHLLLHLLLL
LLHHLLLLLLHLLL
LLHHLHLLLLLHLL
LLHHHLLLLLLLHL
LLHHHHLLLLLLLH
74LVX238
3/12
Table 4: Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Table 5: Recommended Operating Conditions
1) Truth T abl e guarante ed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
Table 6: DC Specifications
Symbol Parameter Value Unit
V
CC
Supply Voltage
-0.5 to +7.0 V
V
I
DC Input Voltage
-0.5 to +7.0 V
V
O
DC Output Voltage -0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20 mA
I
OK
DC Output Diode Current
± 20 mA
I
O
DC Output Current
± 25 mA
I
CC
or I
GND
DC V
CC
or Ground Current
± 50 mA
T
stg
Storage Temperature
-65 to +150 °C
T
L
Lead Temperature (10 sec)
300 °C
Symbol Parameter Value Unit
V
CC
Supply Voltage (note 1)
2 to 3.6 V
V
I
Input Voltage
0 to 5.5 V
V
O
Output Voltage 0 to V
CC
V
T
op
Operating Temperature
-55 to 125 °C
dt/dv
Input Rise and Fall Time (note 2) (V
CC
= 3.3V)
0 to 100 ns/V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
IH
High Level Input
Voltage
2.0 1.5 1.5 1.5
V3.0 2.0 2.0 2.0
3.6 2.4 2.4 2.4
V
IL
Low Level Input
Voltage
2.0 0.5 0.5 0.5
V3.0 0.8 0.8 0.8
3.6 0.8 0.8 0.8
V
OH
High Level Output
Voltage
2.0
I
O
=-50 µA
1.9 2.0 1.9 1.9
V3.0
I
O
=-50 µA
2.9 3.0 2.9 2.9
3.0
I
O
=-4 mA
2.58 2.48 2.4
V
OL
Low Level Output
Voltage
2.0
I
O
=50 µA
0.0 0.1 0.1 0.1
V3.0
I
O
=50 µA
0.0 0.1 0.1 0.1
3.0
I
O
=4 mA
0.36 0.44 0.55
I
I
Input Leakage
Current
3.6
V
I
= 5V or GND
± 0.1 ± 1 ± 1 µA
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
22020µA
74LVX238
4/12
Table 7: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inp ut s are driven 0V to 3.3V, (n-1) outputs switc hi ng and one out put at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to thresho l d
(V
IHD
), f=1MHz.
Table 8: AC Electrical Characteristics (Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the sa m e di rection, ei ther HIGH or LOW
2) Param eter guaran teed by design
(*) Voltage range is 3.3V ±
0.3V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.3 0.5
V
V
OLV
-0.5 -0.3
V
IHD
Dynamic High
Voltage Input (note
1, 3)
3.3 2
V
ILD
Dynamic Low
Voltage Input (note
1, 3)
3.3 0.8
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
t
PLH
t
PHL
Propagation Delay
Time
A, B, C to Y
2.7 15 7.1 13.8 1.0 16.5 1.0 18.5
ns
2.7 50 9.6 17.3 1.0 20.0 1.0 22.0
3.3
(*)
15 5.5 8.8 1.0 10.5 1.0 11.5
3.3
(*)
50 8.0 12.3 1.0 14.0 1.0 15.0
t
PLH
t
PHL
Propagation Delay
Time
G1 to Y
2.7 15 8.7 16.3 1.0 19.5 1.0 205
ns
2.7 50 11.2 19.8 1.0 23.0 1.0 25.0
3.3
(*)
15 6.8 10.6 1.0 12.5 1.0 13.5
3.3
(*)
50 9.3 14.1 1.0 16.0 1.0 17.0
t
PLH
t
PHL
Propagation Delay
Time
G2A
or G2B to Y
2.7 15 8.8 16.0 1.0 18.5 1.0 19.5
ns
2.7 50 11.3 19.5 1.0 22.0 1.0 23.0
3.3
(*)
15 6.9 10.4 1.0 11.5 1.0 13.5
3.3
(*)
50 9.4 13.9 1.0 15.0 1.0 17.0
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
2.7 50 0.5 1.0 1.5 1.5
ns
3.3
(*)
50
0.5 1.0 1.5 1.5
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