ST 74LVX174 User Manual

74LVX174

LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR WITH 5V TOLERANT INPUTS

■HIGH SPEED:

fMAX = 180MHz (TYP.) at VCC = 3.3V

■5V TOLERANT INPUTS

■INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V at VCC=3V

■LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C

■LOW NOISE:

VOLP = 0.3V (TYP.) at VCC = 3.3V

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174

■IMPROVED LATCH-UP IMMUNITY

■POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX174 is a low voltage CMOS HEX D-TYPE FLIP FLOP WITH CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.

SOP TSSOP

Table 1: Order Codes

PACKAGE	T & R
SOP	74LVX174MTR
TSSOP	74LVX174TTR

Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.

When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.

This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection And IEC Logic Symbols

August 2004	Rev. 3
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74LVX174

Figure 2: Input Equivalent Circuit	Table 2: Pin Description
	PIN N°	SYMBOL	NAME AND FUNCTION
	1	CLEAR	Asynchronous Master
			Reset (Active LOW)
	2, 5, 7, 10,	Q0 to Q5	Flip-Flop Outputs
	12, 15
	3, 4, 6, 11,	D0 to D5	Data Inputs
	13, 14
	9	CLOCK	Clock Input (LOW-to-HIGH,
			Edge Triggered)
	8	GND	Ground (0V)
	16	VCC	Positive Supply Voltage

Table 3: Truth Table

			INPUTS					OUTPUTS	FUNCTION
	CLEAR		D	CLOCK				Q
	L		X		X			L	CLEAR
	H		L					L
	H		H					H
	H		X					Qn	NO CHANGE

X : Don’t Care

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

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				74LVX174
Table 4: Absolute Maximum Ratings
Symbol	Parameter	Value			Unit
VCC	Supply Voltage	-0.5 to +7.0			V
VI	DC Input Voltage	-0.5 to +7.0			V
VO	DC Output Voltage	-0.5 to VCC + 0.5			V
IIK	DC Input Diode Current	- 20			mA
IOK	DC Output Diode Current	±	20		mA
IO	DC Output Current	±	25		mA
ICC or IGND	DC VCC or Ground Current	±	50		mA
Tstg	Storage Temperature	-65 to +150			°C
TL	Lead Temperature (10 sec)	300			°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

Table 5: Recommended Operating Conditions

Symbol	Parameter	Value	Unit
VCC	Supply Voltage (note 1)	2 to 3.6	V
VI	Input Voltage	0 to 5.5	V
VO	Output Voltage	0 to VCC	V
Top	Operating Temperature	-55 to 125	°C
dt/dv	Input Rise and Fall Time (note 2) (VCC = 3.3V)	0 to 100	ns/V

1)Truth Table guaranteed: 1.2V to 3.6V

2)VIN from 0.8V to 2.0V

Table 6: DC Specifications

			Test Condition							Value
Symbol	Parameter	VCC				TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
		(V)			Min.		Typ.	Max.		Min.	Max.	Min.	Max.
VIH	High Level Input	2.0			1.5					1.5		1.5
	Voltage	3.0			2.0					2.0		2.0		V
		3.6			2.4					2.4		2.4
VIL	Low Level Input	2.0							0.5		0.5		0.5
	Voltage	3.0							0.8		0.8		0.8	V
		3.6							0.8		0.8		0.8
VOH	High Level Output	2.0		IO=-50 A	1.9		2.0			1.9		1.9
	Voltage
		3.0		IO=-50 A	2.9		3.0			2.9		2.9		V
		3.0		IO=-4 mA	2.58					2.48		2.4
VOL	Low Level Output	2.0		IO=50 A			0.0		0.1		0.1		0.1
	Voltage
		3.0		IO=50 A			0.0		0.1		0.1		0.1	V
		3.0		IO=4 mA				0.36			0.44		0.55
II	Input Leakage	3.6		VI = 5V or GND				±	0.1		± 1		± 1	A
	Current
ICC	Quiescent Supply	3.6		VI = VCC or GND					4		40		40	A
	Current
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74LVX174

Table 7: Dynamic Switching Characteristics

Test Condition

Value

Symbol

Parameter

VCC

TA = 25°C

-40 to 85°C

-55 to 125°C

Unit

(V)

Min.

Typ.

Max.

Min.

Max.

Min.

Max.

VOLP

Dynamic Low Voltage

3.3

0.3

0.8

Quiet Output (note 1, 2)

VOLV

-0.8

-0.3

VIHD

Dynamic High Voltage

3.3

CL = 50 pF

2

V

Input (note 1, 3)

VILD

Dynamic Low Voltage

3.3

0.8

Input (note 1, 3)

1)Worst case package.

2)Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.

3)Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.

Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)

					Test Condition								Value
Symbol		Parameter		VCC		CL			TA = 25°C				-40 to 85°C		-55 to 125°C		Unit
				(V)		(pF)		Min.		Typ.	Max.		Min.	Max.	Min.	Max.
tPLH tPHL		Propagation Delay		2.7		15				7.6		14.5	1.0	17.5	1.0	18.5
		Time CLOCK to Q		2.7		50				10.1		18.0	1.0	21.0	1.0	22.0	ns
				3.3(*)		15				5.9		9.3	1.0	11.0	1.0	12.0
				3.3(*)		50				8.4		12.8	1.0	14.5	1.0	15.5
tPLH tPHL		Propagation Delay		2.7		15				7.9		15.0	1.0	18.5	1.0	19.5
		Time CLEAR to Q		2.7		50				10.4		18.5	1.0	22.0	1.0	23.0	ns
				3.3(*)		15				6.2		9.7	1.0	11.5	1.0	12.5
				3.3(*)		50				8.7		13.2	1.0	15.0	1.0	16.0
tWL		CLEAR	pulse	2.7						6.5				7.5		7.5	ns
		Width, HIGH
				3.3(*)						5.0				5.0		5.0
tW		CLOCK pulse		2.7						6.5				7.5		7.5	ns
		Width		3.3(*)						5.0				5.0		5.0
tS		Setup Time Q to		2.7						7.5				8.5		8.5
		CLOCK HIGH or		3.3(*)						5.0				6.0		6.0	ns
		LOW
th		Hold Time Q to		2.7						0.0				0.0		0.0
		CLOCK HIGH or		3.3(*)						0.0				0.0		0.0	ns
		LOW
tREM		Recovery Time		2.7						4.5				4.5			ns
		CLEAR to Q		3.3(*)						3.0				3.0
fMAX		Maximum Clock		2.7		15		65		130			55
		Frequency		2.7		50		45		60			40				MHz
				3.3(*)		15		115		180			95
				3.3(*)		50		65		95			55
tOSLH		Output To Output		2.7		50				0.5		1.0		1.5		1.5
tOSHL		Skew Time (note1,		3.3(*)		50				0.5		1.0		1.5		1.5	ns
		2)

1)Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW

2)Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V

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