ST 74LVX138 User Manual

74LVX138

LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.)

WITH 5V TOLERANT INPUTS

■ HIGH SPEED:

t

= 5.5ns (TYP.) at V

PD

■ 5V TOLERANT INPUTS

■ INPUT VOLTAGE LEVEL:

V

=0.8V , VIH=2V at VCC=3V

IL

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ LOW NOISE:

V

= 0.3V (TYP.) at VCC = 3.3V

OLP

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 4mA (MIN)

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERATING VOLTAGE RANGE:

V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

PHL

(OPR) = 2V to 3.6V (1.2V Data Retention)

CC

= 3.3V

74 SERIES 138

■ IMPROVED LATCH-UP IMMUN ITY

■ POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C

2

MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. If the device is enabled, 3 binary select (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A

or G2B

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74LVX138MTR

TSSOP 74LVX138TTR

is held high, the decoding function is inhibited and all the 8 outputs go to high. Tree enable inpu ts are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static disc harge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Connection An d I E C Logic Symbols

Rev. 3

1/12August 2004

74LVX138

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

1, 2, 3 A, B, C Address Inputs

4, 5 G2A

6 G1 Enable Input

15, 14, 13,

12, 1 1, 10, 9,

7 8 GND Ground (0V)

16 V

Table 3: Truth Table

, G2B Enable Inputs

to Y7 Outputs

Y0

CC

Positive Supply Voltage

INPUTS

ENABLE SELECT

G2B

X : Don’t Care

G2A G1CBAY0Y1 Y2 Y3 Y4 Y5 Y6 Y7

XXLXXXHHHHHHHH XHXXXXHHHHHHHH HXXXXXHHHHHHHH LLHLLLLHHHHHHH LLHLLHHLHHHHHH LLHLHLHHLHHHHH LLHLHHHHHLHHHH LLHHLLHHHHLHHH LLHHLHHHHHHLHH LLHHHLHHHHHHLH LLHHHHHHHHHHHL

OUTPUTS

Figure 3: Logic Diagram

This logi c di agram has not be used to est i m ate propagation delays

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74LVX138

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

I

OK

I

or I

I

CC

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V V T

dt/dv

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (note 2) (V

= 3.3V)

CC

-0.5 to +7.0 V

- 20 mA

± 20 mA ± 25 mA ± 50 mA

-65 to +150 °C 300 °C

2 to 3.6 V 0 to 5.5 V

CC

-55 to 125 °C 0 to 100 ns/V

V

1) Truth T abl e guarante ed: 1.2V to 3.6V from 0.8V to 2.0V

2) V

IN

Table 6: DC Specifications

Symbol Parameter

V

High Level Input

IH

Voltage

V

Low Level Input

IL

Voltage

High Level Output

OH

Voltage

Low Level Output

OL

Voltage

Input Leakage

I

Current Quiescent Supply

I

CC

Current

Test Condition Value

V

(V)

CC

T

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

= 25°C

2.0 1.5 1.5 1.5

3.6 2.4 2.4 2.4

2.0 0.5 0.5 0.5

3.6 0.8 0.8 0.8

2.0

3.0

2.0

3.0

3.6

IO=-50 µA

=-50 µA

I

O

=-4 mA

I

O

IO=50 µA

=50 µA

I

O

=4 mA

I

O

V

= 5V or GND

I

= VCC or GND

V

I

1.9 2.0 1.9 1.9

2.9 3.0 2.9 2.9

2.58 2.48 2.4

0.0 0.1 0.1 0.1

0.36 0.44 0.55

± 0.1 ± 1 ± 1 µA

44040µA

Unit

V3.0 2.0 2.0 2.0

V3.0 0.8 0.8 0.8

V3.0

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74LVX138

Table 7: Dynamic Switching Characteristics

Test Condition Value

= 25°C

Symbol Parameter

V V

V

Dynamic Low

OLP

Voltage Quiet

OLV

Output (note 1, 2) Dynamic High

IHD

Voltage Input (note

V

CC

(V)

3.3

3.3 2 = 50 pF

C

L

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.5

-0.5 -0.3

1, 3)

V

Dynamic Low

ILD

Voltage Input (note

3.3 0.8

1, 3)

1) Worst case package.

2) Max number of outp ut s defined as (n). Data inp ut s are driven 0V to 3.3V, (n-1) outputs switc hi ng and one out put at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ), f=1MHz.

(V

IHD

Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)

Test Condition Value

-40 to 85°C -55 to 125°C

ILD

Unit

V

), 0V to thresho l d

= 25°C

Symbol Parameter

t

PLH tPHL

Propagation Delay Time A, B, C to Y

3.3

t

PLH tPHL

Propagation Delay Time G1 to Y

3.3

t

PLH tPHL

Propagation Delay Time

or G2B to Y

G2A

3.3

t

OSLH

t

OSHL

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-

ing in the sa m e di rection, ei ther HIGH or LOW

2) Param eter guaran teed by design

(*) Voltage range is 3.3V ±

Output To Output Skew Time (note1,

2)

0.3V

3.3

C

V

CC

(V)

L

(pF)

2.7 15 7.1 13.8 1.0 16.5 1.0 18.5

2.7 50 9.6 17.3 1.0 20.0 1.0 22.0

(*)

15 5.5 8.8 1.0 10.5 1.0 11.5

(*)

50 8.0 12.3 1.0 14.0 1.0 15.0

2.7 15 8.7 16.3 1.0 19.5 1.0 205

2.7 50 11.2 19.8 1.0 23.0 1.0 25.0

(*)

15 6.8 10.6 1.0 12.5 1.0 13.5

(*)

50 9.3 14.1 1.0 16.0 1.0 17.0

2.7 15 8.8 16.0 1.0 18.5 1.0 19.5

2.7 50 11.3 19.5 1.0 22.0 1.0 23.0

(*)

15 6.9 10.4 1.0 11.5 1.0 13.5

(*)

50 9.4 13.9 1.0 15.0 1.0 17.0

2.7 50 0.5 1.0 1.5 1.5

(*)

50

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.5 1.0 1.5 1.5

-40 to 85°C -55 to 125°C

Unit

ns

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