74LVX08
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE WITH 5V TOLERANT INPUTS
■HIGH SPEED:
tPD = 4.8ns (TYP.) at VCC = 3.3V
■5V TOLERANT INPUTS
■INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V AT VCC=3V
■LOW POWER DISSIPATION: ICC = 2 A (MAX.) at TA=25°C
■LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 08
■IMPROVED LATCH-UP IMMUNITY
■POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX08 is a low voltage CMOS QUAD 2-INPUT AND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.
SOP TSSOP
PACKAGE |
T & R |
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SOP |
74LVX08MTR |
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TSSOP |
74LVX08TTR |
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The internal circuit is composed of 2 stages including buffer output, which provides high noise immunity and stable output.
Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.
This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
August 2004 |
Rev. 4 |
1/11 |
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74LVX08
Figure 2: Input Equivalent Circuit |
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Table 2: Pin Description |
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PIN N° |
SYMBOL |
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NAME AND FUNCTION |
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1, 4, 9, 12 |
1A to 4A |
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Data Inputs |
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2, 5, 10, 13 |
1B to 4B |
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Data Inputs |
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3, 6, 8, 11 |
1Y to 4Y |
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Data Outputs |
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7 |
GND |
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Ground (0V) |
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14 |
VCC |
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Positive Supply Voltage |
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Table 3: Truth Table |
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A |
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B |
Y |
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L |
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L |
L |
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L |
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H |
L |
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H |
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L |
L |
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H |
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H |
H |
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Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7.0 |
V |
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VI |
DC Input Voltage |
-0.5 to +7.0 |
V |
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VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
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IIK |
DC Input Diode Current |
- 20 |
mA |
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IOK |
DC Output Diode Current |
± |
20 |
mA |
IO |
DC Output Current |
± |
25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± |
50 |
mA |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
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TL |
Lead Temperature (10 sec) |
300 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage (note 1) |
2 to 3.6 |
V |
VI |
Input Voltage |
0 to 5.5 |
V |
VO |
Output Voltage |
0 to VCC |
V |
Top |
Operating Temperature |
-55 to 125 |
°C |
dt/dv |
Input Rise and Fall Time (note 2) (VCC = 3.3V) |
0 to 100 |
ns/V |
1)Truth Table guaranteed: 1.2V to 3.6V
2)VIN from 0.8V to 2.0V
2/11
74LVX08
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VIH |
High Level Input |
2.0 |
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1.5 |
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1.5 |
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1.5 |
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Voltage |
3.0 |
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2.0 |
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2.0 |
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2.0 |
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V |
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3.6 |
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2.4 |
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2.4 |
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2.4 |
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VIL |
Low Level Input |
2.0 |
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0.5 |
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0.5 |
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0.5 |
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Voltage |
3.0 |
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0.8 |
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0.8 |
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0.8 |
V |
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3.6 |
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0.8 |
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0.8 |
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0.8 |
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VOH |
High Level Output |
2.0 |
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IO=-50 A |
1.9 |
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2.0 |
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1.9 |
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1.9 |
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Voltage |
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3.0 |
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IO=-50 A |
2.9 |
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3.0 |
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2.9 |
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2.9 |
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V |
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3.0 |
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IO=-4 mA |
2.58 |
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2.48 |
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2.4 |
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VOL |
Low Level Output |
2.0 |
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IO=50 A |
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0.0 |
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0.1 |
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0.1 |
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0.1 |
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Voltage |
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3.0 |
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IO=50 A |
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0.0 |
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0.1 |
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0.1 |
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0.1 |
V |
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3.0 |
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IO=4 mA |
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0.36 |
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0.44 |
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0.55 |
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II |
Input Leakage |
3.6 |
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VI = 5V or GND |
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± |
0.1 |
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± 1 |
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± 1 |
A |
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Current |
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ICC |
Quiescent Supply |
3.6 |
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VI = VCC or GND |
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2 |
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20 |
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20 |
A |
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Current |
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Table 7: Dynamic Switching Characteristics |
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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VOLP |
Dynamic Low |
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0.3 |
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0.5 |
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Voltage Quiet |
3.3 |
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VOLV |
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-0.5 |
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-0.3 |
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Output (note 1, 2) |
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VIHD |
Dynamic High |
3.3 |
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CL = 50 pF |
2 |
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V |
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Voltage Input (note |
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1, 3) |
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VILD |
Dynamic Low |
3.3 |
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0.8 |
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Voltage Input (note |
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1, 3) |
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1)Worst case package.
2)Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3)Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
3/11
74LVX08
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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CL |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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(pF) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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tPLH tPHL |
Propagation Delay |
2.7 |
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15 |
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6.3 |
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11.4 |
1.0 |
12.5 |
1.0 |
13.5 |
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Time |
2.7 |
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50 |
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8.8 |
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14.9 |
1.0 |
17.0 |
1.0 |
18.0 |
ns |
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3.3(*) |
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15 |
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4.8 |
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7.1 |
1.0 |
8.5 |
1.0 |
9.5 |
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3.3(*) |
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50 |
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7.3 |
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10.6 |
1.0 |
12.0 |
1.0 |
13.0 |
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tOSLH |
Output To Output |
2.7 |
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50 |
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0.5 |
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1.0 |
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1.5 |
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1.5 |
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tOSHL |
Skew Time (note1, |
3.3(*) |
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50 |
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0.5 |
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1.0 |
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1.5 |
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1.5 |
ns |
2) |
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1)Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW
2)Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25°C |
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-40 to 85°C |
-55 to 125°C |
Unit |
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(V) |
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Min. |
Typ. |
Max. |
Min. |
Max. |
Min. |
Max. |
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CIN |
Input Capacitance |
3.3 |
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4 |
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10 |
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10 |
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10 |
pF |
CPD |
Power Dissipation |
3.3 |
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18 |
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pF |
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Capacitance |
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(note 1) |
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1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω )
4/11