ST 74LVQ74 User Manual

74LVQ74

74LVQ74

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

■HIGH SPEED:

fMAX = 250 MHz (TYP.) at VCC = 3.3V

■COMPATIBLE WITH TTL OUTPUTS

■LOW POWER DISSIPATION: ICC = 2 μA (MAX.) at TA = 25 oC

■LOW NOISE:

VOLP = 0.2 V (TYP.) at VCC = 3.3V

■75Ω TRANSMISSION LINE DRIVING CAPABILITY

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN)

■PCI BUS LEVELS GUARANTEED AT 24mA

■BALANCED PROPAGATION DELAYS:

tPLH tPHL

■OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 3.6V (1.2V Data Retention)

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74

■IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The LVQ74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise

M	T
(Micro Package)	(TSSOP Package)

ORDER CODES :

74LVQ74M 74LVQ74T

3.3V applications.

A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse.

CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input.

It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

February 1999

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74LVQ74

INPUT AND OUTPUT EQUIVALENT CIRCUIT	PIN DESCRIPTION
	PIN No	SYMBOL	NAME AND FUNCT ION
	1, 13	1CLR,	Asyncronous Reset -
		2CLR	Direct Input
	2, 12	1D, 2D	Data Inputs
	3, 11	1CK, 2CK	Clock Input
			(LOW-to-HIGH, Edge-
			Triggered)
	4, 10	1PR, 2PR	Asyncronous Set - Direct
			Input
	5, 9	1Q, 2Q	True Flip-Flop Outputs
	6, 8	1Q, 2Q	Complement Flip-Flop
			Outputs
	7	GND	Ground (0V)
	14	VCC	Positive Supply Voltage

TRUTH TABLE

		I NPUTS		OUT PUT S		F UNCTI ON
CLR	PR	D	CK	Q	Q
L	H	X	X	L	H	CLEAR
H	L	X	X	H	L	PRESET
L	L	X	X	H	H
H	H	L		L	H
H	H	H		H	L
H	H	X		Qn	Qn	NO CHANGE
X:Don't Care

LOGIC DIAGRAM

Thislogic diagram has notbe used to esimate propagation delays

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			74LVQ74
ABSOLUTE MAXIMUM RATINGS
Symbol	Parameter	Val ue	Unit
VCC	Supply Voltage	-0.5 to +7	V
VI	DC Input Voltage	-0.5 to VCC + 0.5	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	± 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Current	± 50	mA
ICC or IGND	DC VCC or Ground Current	± 400	mA
Tstg	Storage Temperature	-65 to +150	oC
TL	Lead Temperature (10 sec)	300	oC

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Valu e	Uni t
VCC	Supply Voltage (note 1)	2 to 3.6	V
VI	Input Voltage	0 to VCC	V
VO	Output Voltage	0 to VCC	V
Top	Operating Temperature:	-40 to +85	oC
dt/dv	Input Rise and Fall Time (VCC = 3V) (note 2)	0 to 10	ns/V

1)Truth Table guaranteed: 1.2V to 3.6V

2)VIN from 0.8V to 2V

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74LVQ74

DC SPECIFICATIONS

Symb ol Parameter

VIH	High Level Input Voltage
VIL	Low Level Input Voltage
VOH	High Level Output
	Voltage
VOL	Low Level Output
	Voltage
II	Input Leakage Current
ICC	Quiescent Supply
	Current

	Test Co nditi ons			Valu e		Un it
VCC			TA = 25 oC		-40 to 85 oC
(V)			Min. T yp. Max. Mi n. Max.
3.0 to			2.0		2.0	V
3.6				0.8	0.8	V
3.0	VI(* ) =	IO=-50 μA	2.9 2.99		2.9
	VIH or	IO=-12 mA	2.58		2.48	V
	VIL	IO=-24 mA			2.2
3.0	VI(*) =	IO=50 μA	0.002	0.1	0.1
	VIH or	IO=12 mA	0	0.36	0.44	V
	VIL
		IO=24 mA			0.55
3.6	VI = VCC or GND			±0.1	±1	μA
3.6	VI = VCC or GND			2	20	μA

IOLD Dynamic Output Current		3.6	VOLD = 0.8 V max	36	mA
IOHD	(note 1, 2)		VOHD = 2 V min	-25	mA

1)Maximum test duration 2ms, one output loaded attime

2)Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω.

(*)All outputs loaded.

DYNAMIC SWITCHING CHARACTERISTICS

Symb ol	Parameter		Test Co nditi ons		Valu e	Un it
		VCC		TA = 25 oC		-40 to 85 oC
		(V)		Min. T yp. Max. Mi n. Max.
VOLP	Dynamic Low Voltage	3.3		0.2	0.8
VOLV	Quiet Output (note 1, 2)			-0.8 -0.2
VIHD	Dynamic High Voltage	3.3	CL = 50 pF		2	V
	Input (note 1, 3)
VILD	Dynamic Low Voltage	3.3		0.8
	Input (note 1, 3)

1)Worst case package

2)Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND

3)max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz

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