74LVC374A
OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE
■5V TOLERANT INPUTS
■HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V
■POWER DOWN PROTECTION ON INPUTS AND OUTPUTS
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V
■PCI BUS LEVELS GUARANTEED AT 24 mA
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention)
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374
■LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)
■ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015); MM > 200V
DESCRIPTION
The 74LVC374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs.
SOP TSSOP
PACKAGE |
T & R |
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SOP |
74LVC374AMTR |
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TSSOP |
74LVC374ATTR |
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While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
The Output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
July 2004 |
Rev. 2 |
1/14 |
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74LVC374A
PIN N° |
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NAME AND FUNCTION |
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OE |
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3 State Output Enable Input (Active LOW) |
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2, 5, 6, 9, 12, 15, 16,19 |
Q0 to Q7 |
3-State Outputs |
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3, 4, 7, 8, 13, 14, 17, 18 |
D0 to D7 |
Data Inputs |
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11 |
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CK |
Clock |
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10 |
GND |
Ground (0V) |
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20 |
VCC |
Positive Supply Voltage |
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Table 3: Truth Table |
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INPUTS |
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OUTPUT |
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OE |
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CK |
D |
Q |
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H |
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L |
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NO CHANGE |
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L |
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L |
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H |
H |
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X : Don’t Care
Z :High Impedance
2/14
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74LVC374A |
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Table 4: Absolute Maximum Ratings |
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Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7.0 |
V |
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VI |
DC Input Voltage |
-0.5 to +7.0 |
V |
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VO |
DC Output Voltage (VCC = 0V) |
-0.5 to +7.0 |
V |
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VO |
DC Output Voltage (High or Low State) (note 1) |
-0.5 to VCC + 0.5 |
V |
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IIK |
DC Input Diode Current |
- 50 |
mA |
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IOK |
DC Output Diode Current (note 2) |
- 50 |
mA |
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IO |
DC Output Current |
± |
50 |
mA |
ICC or IGND |
DC VCC or Ground Current per Supply Pin |
± |
100 |
mA |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
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TL |
Lead Temperature (10 sec) |
300 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
1)IO absolute maximum rating must be observed
2)VO < GND
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Value |
Unit |
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VCC |
Supply Voltage (note 1) |
1.65 to 3.6 |
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VI |
Input Voltage |
0 to 5.5 |
V |
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VO |
Output Voltage (VCC = 0V) |
0 to 5.5 |
V |
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VO |
Output Voltage (High or Low State) |
0 to VCC |
V |
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IOH, IOL |
High or Low Level Output Current (VCC = 3.0 to 3.6V) |
± |
24 |
mA |
IOH, IOL |
High or Low Level Output Current (VCC = 2.7 to 3.0V) |
± |
12 |
mA |
IOH, IOL |
High or Low Level Output Current (VCC = 2.3 to 2.7V) |
± |
8 |
mA |
IOH, IOL |
High or Low Level Output Current (VCC = 1.65 to 2.3V) |
± |
4 |
mA |
Top |
Operating Temperature |
-55 to 125 |
°C |
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dt/dv |
Input Rise and Fall Time (note 2) |
0 to 10 |
ns/V |
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1)Truth Table guaranteed: 1.2V to 3.6V
2)VI from 0.8V to 2V at VCC = 3.0V
3/14
74LVC374A
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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-40 to 85 °C |
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-55 to 125 °C |
Unit |
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(V) |
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Min. |
Max. |
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Min. |
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Max. |
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VIH |
High Level Input |
1.65 to 1.95 |
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0.65VCC |
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0.65VCC |
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Voltage |
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V |
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2.3 to 2.7 |
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1.7 |
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1.7 |
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2.7 to 3.6 |
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2 |
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2 |
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VIL |
Low Level Input |
1.65 to 1.95 |
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0.35VCC |
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0.35VCC |
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Voltage |
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V |
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2.3 to 2.7 |
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0.7 |
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0.7 |
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2.7 to 3.6 |
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0.8 |
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0.8 |
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VOH |
High Level Output |
1.65 to 3.6 |
IO=-100 A |
VCC-0.2 |
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VCC-0.2 |
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Voltage |
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1.65 |
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IO=-4 mA |
1.2 |
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1.2 |
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2.3 |
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IO=-8 mA |
1.7 |
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1.7 |
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V |
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2.7 |
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IO=-12 mA |
2.2 |
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2.2 |
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3.0 |
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IO=-18 mA |
2.4 |
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2.4 |
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3.0 |
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IO=-24 mA |
2.2 |
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2.2 |
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VOL |
Low Level Output |
1.65 to 3.6 |
IO=100 A |
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0.2 |
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0.2 |
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Voltage |
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1.65 |
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IO=4 mA |
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0.45 |
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0.45 |
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2.3 |
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IO=8 mA |
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0.7 |
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0.7 |
V |
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2.7 |
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IO=12 mA |
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0.4 |
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0.4 |
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3.0 |
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IO=24 mA |
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0.55 |
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0.55 |
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II |
Input Leakage |
3.6 |
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VI = 0 to 5.5V |
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± 5 |
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± 5 |
A |
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Current |
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Ioff |
Power Off Leakage |
0 |
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VI or VO = 5.5V |
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10 |
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10 |
A |
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Current |
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IOZ |
High Impedance |
3.6 |
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VI = VIH or VIL |
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± |
10 |
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± |
10 |
A |
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Output Leakage |
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VO = 0 to 5.5V |
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Current |
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ICC |
Quiescent Supply |
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VI = VCC or GND |
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10 |
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10 |
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Current |
3.6 |
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A |
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VI or VO = 3.6 to |
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10 |
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± |
10 |
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5.5V |
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∆ ICC |
ICC incr. per Input |
2.7 to 3.6 |
VIH = VCC-0.6V |
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500 |
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500 |
A |
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Table 7: Dynamic Switching Characteristics |
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Test Condition |
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Value |
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Symbol |
Parameter |
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VCC |
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TA = 25 °C |
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(V) |
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Min. |
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Typ. |
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Max. |
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VOLP |
Dynamic Low Level Quiet |
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3.3 |
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CL = 50pF |
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0.8 |
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V |
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Output (note 1) |
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VIL = 0V, VIH = 3.3V |
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VOLV |
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-0.8 |
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1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.
4/14
74LVC374A
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
CL |
RL |
ts = tr |
-40 to 85 °C |
-55 to 125 °C |
Unit |
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(V) |
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(pF) |
(Ω ) |
(ns) |
Min. |
Max. |
Min. |
Max. |
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tPLH tPHL |
Propagation Delay |
1.65 to |
1.95 |
30 |
1000 |
2.0 |
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TBD |
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TBD |
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Time D to Q |
2.3 to |
2.7 |
30 |
500 |
2.0 |
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TBD |
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TBD |
ns |
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2.7 |
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50 |
500 |
2.5 |
1.5 |
7.8 |
1.5 |
9.4 |
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3.0 to |
3.6 |
50 |
500 |
2.5 |
1 |
6.8 |
1 |
8.2 |
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tPLH tPHL |
Propagation Delay |
1.65 to |
1.95 |
30 |
1000 |
2.0 |
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TBD |
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TBD |
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Time LE to Q |
2.3 to |
2.7 |
30 |
500 |
2.0 |
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TBD |
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TBD |
ns |
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2.7 |
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50 |
500 |
2.5 |
1.5 |
7.8 |
1.5 |
9.4 |
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3.0 to |
3.6 |
50 |
500 |
2.5 |
1 |
6.8 |
1 |
8.2 |
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tPZL tPZH |
Output Enable Time |
1.65 to |
1.95 |
30 |
1000 |
2.0 |
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TBD |
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TBD |
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2.3 to |
2.7 |
30 |
500 |
2.0 |
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TBD |
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TBD |
ns |
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2.7 |
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50 |
500 |
2.5 |
1 |
8.7 |
1 |
10.4 |
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3.0 to |
3.6 |
50 |
500 |
2.5 |
1 |
7.7 |
1 |
9.2 |
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tPLZ tPHZ |
Output Disable Time |
1.65 to |
1.95 |
30 |
1000 |
2.0 |
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TBD |
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TBD |
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2.3 to |
2.7 |
30 |
500 |
2.0 |
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TBD |
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TBD |
ns |
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2.7 |
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50 |
500 |
2.5 |
2 |
7.6 |
2 |
9.1 |
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3.0 to |
3.6 |
50 |
500 |
2.5 |
2 |
7.0 |
2 |
8.4 |
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tW |
LE Pulse Width |
1.65 to |
1.95 |
30 |
1000 |
2.0 |
TBD |
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TBD |
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HIGH |
2.3 to |
2.7 |
30 |
500 |
2.0 |
TBD |
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TBD |
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ns |
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2.7 |
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50 |
500 |
2.5 |
3.3 |
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3.3 |
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3.0 to |
3.6 |
50 |
500 |
2.5 |
3.3 |
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3.3 |
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ts |
Setup Time D to LE |
1.65 to |
1.95 |
30 |
1000 |
2.0 |
TBD |
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TDB |
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(HIGH to LOW) |
2.3 to |
2.7 |
30 |
500 |
2.0 |
TBD |
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TBD |
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ns |
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2.7 |
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50 |
500 |
2.5 |
2 |
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3.0 to |
3.6 |
50 |
500 |
2.5 |
2 |
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2 |
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th |
Hold Time D to |
1.65 to |
1.95 |
30 |
1000 |
2.0 |
TBD |
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TBD |
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CLOCK, HIGH or |
2.3 to |
2.7 |
30 |
500 |
2.0 |
TBD |
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TBD |
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ns |
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LOW |
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2.7 |
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50 |
500 |
2.5 |
1.5 |
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1.5 |
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3.0 to |
3.6 |
50 |
500 |
2.5 |
1.5 |
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1.5 |
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tOSLH |
Output To Output |
2.7 to |
3.6 |
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1 |
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1 |
ns |
tOSHL |
Skew Time (note1, |
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2) |
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1)Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
2)Parameter guaranteed by design
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Test Condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25 °C |
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Unit |
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(V) |
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Min. |
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Typ. |
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Max. |
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CIN |
Input Capacitance |
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4 |
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pF |
CPD |
Power Dissipation Capacitance |
1.8 |
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fIN = 10MHz |
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28 |
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(note 1) |
2.5 |
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30 |
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pF |
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3.3 |
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34 |
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1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
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