74LCX74
Low voltage CMOS dual D-Type Flip Flop with 5V tolerant inputs
Features
■5V tolerant inputs
■High speed:
–fMAX = 150MHz (Max) at VCC = 3V
■Power down protection on inputs and outputs
■Symmetrical output impedance:
–|IOH| = IOL = 24mA (Min) at VCC = 3V
■PCI bus levels guaranteed at 24mA
■Balanced propagation delays:
–tPLH tPHL
■Operating voltage range:
–VCC (Opr) = 2.0V to 3.6V
■Pin and function compatible with 74 series 74
■Latch-up performance exceeds 500mA (JESD 17)
■ESD performance:
–HBM > 2000V
(MIL STD 883 method 3015); MM > 200V
SO-14 |
TSSOP14 |
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Description
The 74LCX74 is a low voltage CMOS dual D-type flip flop with preset and clear non inverting fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs.
A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse.
CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input.
It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
Order codes
Part number |
Package |
Packaging |
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74LCX74MTR |
SO-14 |
Tape and reel |
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74LCX74TTR |
TSSOP14 |
Tape and reel |
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July 2006 |
Rev 8 |
1/17 |
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www.st.com |
Contents |
74LCX74 |
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Contents
1 |
Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . |
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1.1 |
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2 |
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
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2.1 |
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.2 |
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
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2.3 |
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3 |
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
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3.1 |
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
5 |
4 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6 |
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
2/17
74LCX74 |
Logic symbols and I/O equivalent circuit |
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Note: |
This logic diagram has not to be used to estimate propagation delays |
3/17
Pin settings |
74LCX74 |
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2.2 |
Pin description |
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Table 1. Pin description |
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Pin N° |
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Symbol |
Name and function |
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1, 13 |
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Asynchronous reset - direct input |
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1CLR, |
2CLR |
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2, 12 |
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1D, 2D |
Data inputs |
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3, 11 |
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1CK, 2CK |
Clock input (LOW to HIGH, Edge Triggered) |
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4, 10 |
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Asynchronous set - direct input |
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1PR, |
2PR |
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5, 9 |
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1Q, 2Q |
True Flip-Flop outputs |
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6, 8 |
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Complement Flip-Flop outputs |
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1Q, |
2Q |
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7 |
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GND |
Ground (0V) |
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14 |
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VCC |
Positive supply voltage |
2.3 |
Truth table |
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Table 2. Truth table |
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Inputs |
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Outputs |
Function |
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CLR |
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PR |
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D |
CK |
Q |
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Q |
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L |
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H |
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X |
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X |
L |
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H |
CLEAR |
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H |
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L |
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X |
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X |
H |
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L |
PRESET |
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L |
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L |
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X |
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X |
H |
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H |
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H |
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H |
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L |
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L |
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H |
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H |
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H |
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H |
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H |
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L |
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H |
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H |
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X (1) |
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Qn |
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No change |
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Q |
n |
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1. X do not care
4/17
74LCX74 |
Maximum rating |
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stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the STMicroelectronics sure program and other relevant quality documents.
Table 3. Absolute maximum ratings
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply voltage |
-0.5 to +7.0 |
V |
VI |
DC input voltage |
-0.5 to +7.0 |
V |
VO |
DC output voltage (VCC = 0V) |
-0.5 to +7.0 |
V |
VO |
DC output voltage (high or low state) (1) |
-0.5 to VCC + 0.5 |
V |
IIK |
DC input diode current |
-50 |
mA |
IOK |
DC output diode current (2) |
-50 |
mA |
IO |
DC output current |
± 50 |
mA |
ICC |
DC supply current per supply pin |
± 100 |
mA |
IGND |
DC ground current per supply pin |
± 100 |
mA |
Tstg |
Storage temperature |
-65 to +150 |
°C |
TL |
Lead temperature (10 sec) |
300 |
°C |
1.IO absolute maximum rating must be observed
2.VO < GND
Table 4. Recommended operating conditions
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply voltage (1) |
2.0 to 3.6 |
V |
VI |
Input voltage |
0 to 5.5 |
V |
VO |
Output voltage (VCC = 0V) |
0 to 5.5 |
V |
VO |
Output voltage (high or low state) |
0 to VCC |
V |
IOH, IOL |
High or low level output current (VCC = 3.0 to 3.6V) |
± 24 |
mA |
IOH, IOL |
High or low level output current (VCC = 2.7V) |
± 12 |
mA |
Top |
Operating temperature |
-40 to 85 |
°C |
dt/dv |
Input Rise and Fall Time(2) |
0 to 10 |
ns/V |
1.Truth table guaranteed: 1.5V to 3.6V
2.VIN from 0.8V to 2V at VCC = 3.0V
5/17
Electrical characteristics |
74LCX74 |
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Table 5. DC specifications
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Test condition |
Value |
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Symbol |
Parameter |
VCC |
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-40 to 85°C |
Unit |
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(V) |
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Min |
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Max |
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VIH |
High level input |
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2.0 |
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V |
voltage |
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2.7 to 3.6 |
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VIL |
Low level input |
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0.8 |
V |
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voltage |
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2.7 to 3.6 |
IO=-100 A |
VCC-0.2 |
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VOH |
High level output |
2.7 |
IO=-12 mA |
2.2 |
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V |
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voltage |
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IO=-18 mA |
2.4 |
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3.0 |
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IO=-24 mA |
2.2 |
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2.7 to 3.6 |
IO=100 A |
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0.2 |
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VOL |
Low level output |
2.7 |
IO=12 mA |
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0.4 |
V |
voltage |
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IO=16 mA |
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0.4 |
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3.0 |
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IO=24 mA |
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0.55 |
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II |
Input leakage current |
2.7 to 3.6 |
VI = 0 to 5.5V |
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± 5 |
A |
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Ioff |
Power OFF leakage |
0 |
VI or VO = 5.5V |
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10 |
A |
current |
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ICC |
Quiescent supply |
2.7 to 3.6 |
VI = VCC or GND |
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10 |
A |
current |
VI or VO= 3.6 to 5.5V |
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± 10 |
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∆ICC |
I incr. per Input |
2.7 to 3.6 |
VIH = VCC - 0.6V |
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500 |
A |
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Table 6. Dynamic switching characteristics
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Test condition |
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Value |
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Symbol |
Parameter |
VCC |
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TA = 25 °C |
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(V) |
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Min |
Typ |
Max |
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VOLP |
Dynamic low level quiet |
3.3 |
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CL = 50pF |
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0.8 |
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V |
VOLV |
output (1) |
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VIL = 0V, VIH |
= 3.3V |
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-0.8 |
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1.Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.
6/17