ST 74LCX373M User Manual

74LCX373M

74LCX373

OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

■5V TOLERANT INPUTS AND OUTPUTS

■HIGH SPEED :

tPD = 8.0 ns (MAX.) at VCC = 3V

■POWER DOWN PROTECTION ON INPUTS AND OUTPUTS

■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V

■PCI BUS LEVELS GUARANTEED AT 24 mA

■BALANCED PROPAGATION DELAYS: tPLH tPHL

■OPERATING VOLTAGE RANGE:

VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention)

■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373

■LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)

■ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015); MM > 200V

DESCRIPTION

The 74LCX373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs.

These 8 bit D-Type latch are controlled by a latch

PIN CONNECTION AND IEC LOGIC SYMBOLS

SOP			TSSOP
ORDER CODES
PACKAGE		TUBE		T & R
SOP		74LCX373M		74LCX373MTR
TSSOP				74LCX373TTR

enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state.

It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

September 2001

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74LCX373

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No	SYMBOL			NAME AND FUNCTION
1		OE		3 State Output Enable
				Input (Active LOW)
2, 5, 6, 9, 12,	D0 to D7			Data Inputs
15, 16,19
3, 4, 7, 8, 13,	Q0 to Q7			3-State Outputs
14, 17, 18
11		LE		Latch Enable Input
10	GND			Ground (0V)
20	VCC			Positive Supply Voltage

TRUTH TABLE

			INPUT		OUTPUT
	OE		LE	D	Q
	H		X	X	Z
	L		L	X	NO CHANGE*
	L		H	L	L
	L		H	H	H

X : Don’t Care

Z : High Impedance

* : Q Outputs are latched at the time when the LE input is taken LOW.

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

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			74LCX373
ABSOLUTE MAXIMUM RATINGS
Symbol	Parameter	Value		Unit
VCC	Supply Voltage	-0.5 to +7.0		V
VI	DC Input Voltage	-0.5 to +7.0		V
VO	DC Output Voltage (OFF State)	-0.5 to +7.0		V
VO	DC Output Voltage (High or Low State) (note 1)	-0.5 to VCC + 0.5		V
IIK	DC Input Diode Current	- 50		mA
IOK	DC Output Diode Current (note 2)	- 50		mA
IO	DC Output Current	± 50		mA
ICC	DC Supply Current per Supply Pin	± 100		mA
IGND	DC Ground Current per Supply Pin	± 100		mA
Tstg	Storage Temperature	-65 to +150		°C
TL	Lead Temperature (10 sec)	300		°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

1)IO absolute maximum rating must be observed

2)VO < GND

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Value	Unit
VCC	Supply Voltage (note 1)	2.0 to 3.6	V
VI	Input Voltage	0 to 5.5	V
VO	Output Voltage (OFF State)	0 to 5.5	V
VO	Output Voltage (High or Low State)	0 to VCC	V
IOH, IOL	High or Low Level Output Current (VCC = 3.0 to 3.6V)	± 24	mA
IOH, IOL	High or Low Level Output Current (VCC = 2.7V)	± 12	mA
Top	Operating Temperature	-55 to 125	°C
dt/dv	Input Rise and Fall Time (note 2)	0 to 10	ns/V

1)Truth Table guaranteed: 1.5V to 3.6V

2)VIN from 0.8V to 2V at VCC = 3.0V

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