74LCX138MTR
74LCX138
LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS
■5V TOLERANT INPUTS
■HIGH SPEED:
tPD = 6.7ns (MAX.) at VCC = 3V
■POWER DOWN PROTECTION ON INPUTS AND OUTPUTS
■SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V
■PCI BUS LEVELS GUARANTEED AT 24 mA
■BALANCED PROPAGATION DELAYS: tPLH tPHL
■OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention)
■PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138
■LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)
■ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015); MM > 200V
DESCRIPTION
The 74LCX138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs.
If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will
SOP TSSOP
Table 1: Order Codes
PACKAGE |
T & R |
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SOP |
74LCX138MTR |
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TSSOP |
74LCX138TTR |
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go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems.
It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004 |
Rev. 4 |
1/12 |
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74LCX138
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
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PIN N° |
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SYMBOL |
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NAME AND FUNCTION |
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1, 2, 3 |
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A, B, C |
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Address Inputs |
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4, 5 |
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G2A, |
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G2B |
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Enable Inputs |
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6 |
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G1 |
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Enable Input |
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15, 14, 13, 12, 11, 10, 9, 7 |
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Y0 |
to |
Y7 |
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Outputs |
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8 |
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GND |
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Ground (0V) |
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16 |
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VCC |
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Positive Supply Voltage |
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Table 3: Truth Table |
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INPUTS |
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OUTPUTS |
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ENABLE |
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SELECT |
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G2B |
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G2A |
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G1 |
C |
B |
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A |
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Y0 |
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Y1 |
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Y3 |
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Y4 |
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Y5 |
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Y6 |
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Y7 |
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X |
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L |
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X : Don’t Care
2/12
74LCX138
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Table 4: Absolute Maximum Ratings
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage |
-0.5 to +7.0 |
V |
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VI |
DC Input Voltage |
-0.5 to +7.0 |
V |
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VO |
DC Output Voltage (VCC = 0V) |
-0.5 to +7.0 |
V |
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VO |
DC Output Voltage (High or Low State) (note 1) |
-0.5 to VCC + 0.5 |
V |
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IIK |
DC Input Diode Current |
- 50 |
mA |
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IOK |
DC Output Diode Current (note 2) |
- 50 |
mA |
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IO |
DC Output Current |
± |
50 |
mA |
ICC |
DC Supply Current per Supply Pin |
± |
100 |
mA |
IGND |
DC Ground Current per Supply Pin |
± |
100 |
mA |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
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TL |
Lead Temperature (10 sec) |
300 |
°C |
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
1)IO absolute maximum rating must be observed
2)VO < GND
3/12
74LCX138
Table 5: Recommended Operating Conditions
Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply Voltage (note 1) |
2.0 to 3.6 |
V |
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VI |
Input Voltage |
0 to 5.5 |
V |
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VO |
Output Voltage (VCC = 0V) |
0 to 5.5 |
V |
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VO |
Output Voltage (High or Low State) |
0 to VCC |
V |
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IOH, IOL |
High or Low Level Output Current (VCC = 3.0 to 3.6V) |
± |
24 |
mA |
IOH, IOL |
High or Low Level Output Current (VCC = 2.7V) |
± |
12 |
mA |
Top |
Operating Temperature |
-55 to 125 |
°C |
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dt/dv |
Input Rise and Fall Time (note 2) |
0 to 10 |
ns/V |
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1)Truth Table guaranteed: 1.5V to 3.6V
2)VIN from 0.8V to 2V at VCC = 3.0V
Table 6: DC Specifications
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Test Condition |
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Value |
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Symbol |
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VCC |
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-40 to 85 °C |
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-55 to 125 °C |
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(V) |
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Min. |
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Max. |
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Min. |
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Max. |
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VIH |
High Level Input |
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2.0 |
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2.0 |
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V |
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Voltage |
2.7 to 3.6 |
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VIL |
Low Level Input |
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0.8 |
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0.8 |
V |
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Voltage |
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VOH |
High Level Output |
2.7 to 3.6 |
IO=-100 A |
VCC-0.2 |
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VCC-0.2 |
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Voltage |
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2.7 |
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IO=-12 mA |
2.2 |
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2.2 |
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V |
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3.0 |
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IO=-18 mA |
2.4 |
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IO=-24 mA |
2.2 |
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2.2 |
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VOL |
Low Level Output |
2.7 to 3.6 |
IO=100 A |
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0.2 |
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0.2 |
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Voltage |
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2.7 |
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IO=12 mA |
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0.4 |
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0.4 |
V |
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3.0 |
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IO=16 mA |
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0.4 |
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0.4 |
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IO=24 mA |
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0.55 |
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0.55 |
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II |
Input Leakage |
2.7 to 3.6 |
VI = 0 to 5.5V |
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± 5 |
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± 5 |
A |
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Current |
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Ioff |
Power Off Leakage |
0 |
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VI or VO = 5.5V |
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10 |
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10 |
A |
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Current |
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ICC |
Quiescent Supply |
2.7 to 3.6 |
VI = VCC or GND |
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10 |
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10 |
A |
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Current |
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VI or VO= 3.6 to 5.5V |
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± 10 |
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± 10 |
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∆ ICC |
ICC incr. per Input |
2.7 to 3.6 |
VIH = VCC - 0.6V |
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500 |
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500 |
A |
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Table 7: Dynamic Switching Characteristics |
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Test Condition |
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Value |
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Symbol |
Parameter |
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VCC |
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TA = 25 °C |
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Unit |
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(V) |
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Min. |
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Typ. |
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Max. |
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VOLP |
Dynamic Low Level Quiet |
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3.3 |
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CL = 50pF |
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0.8 |
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V |
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Output (note 1) |
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VIL = 0V, VIH = 3.3V |
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VOLV |
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-0.8 |
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1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.
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