ST 54AC164245 User Manual

54AC164245

Rad-hard 16-bit transceiver, 3.3 V to 5 V bidirectional level shifter

Features

■Fully compatible with 54ACS164245

■Dual supply bidirectional level shifter

■Extended voltage range from 2.3 V to 5.5 V

■Separated enable pin for 3-state output

■Schmidt-triggered I/Os: 100 mV hysteresis

■Internal 26 Ω limiting resistor on each I/O

■High speed: Tpd = 8 ns maximum

■Bus hold

■Fail safe

■Cold spare

■Hermetic package

■100 krad (Si) at any Mil1019 dose rate

■SEL immune to 110MeV.cm2/mg LET ions

■RHA QML-V qualified

Description

The 54AC164245 is a rad-hard advanced highspeed CMOS, Schmitt trigger 16-bit bidirectional multi-purpose transceiver with 3-state outputs and cold sparing.

Designed for use as an interface between a 5 V bus and a 3.3 V bus in mixed 5 V/3.3 V supply systems, it achieves high-speed operation while maintaining the CMOS low-power dissipation.

Datasheet − production data

Ceramic Flat-48

The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package

All pins have cold spare buffers to change them to high impedance when VDD is tied to ground.

This IC is intended for two-way asynchronous communication between the data buses and the direction of the data transmission is determined by the nDIR inputs.

The A port interfaces with the 3.3 V bus but can also operate at 2.3 V. The B port operates with the 5 V bus.

	Table 1.	Device summary
	Reference		SMD pin	Quality	Package	Lead	Mass	EPPL	Temp range
				level		finish
	RHRAC164245K1		-	Engineering		Gold		-
				model					-55 °C
					Flat-48		1.50 g
	RHRAC164245K01V		5962R9858008VYC	QMLV-		Gold		Target	to +125 °C
				Flight
	Note:	Contact your ST sales office for information on the specific conditions for products in die form.

April 2012

Doc ID 18093 Rev 2

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This is information on a product in full production.

www.st.com

Functional description	54AC164245

1 Functional description

Figure 1. Logic diagram

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Table 2.	Function table
	Enable,			Direction, DIRx	Operation
		OEx
	L			L	B data to A bus
	L			H	A data to B bus
	H			X	Isolation

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54AC164245	Functional description

1.1Cold spare

The 54AC164245 features a cold spare input and output buffers. In high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 V (VDD = VSS, VDD - VSS = 0 V) without affecting the bus signals or injecting current from the I/Os to the power supplies. Cold sparing also allows to keep unpowered redundant devices so that they can be switched on only when required. Power consumption is therefore reduced by switching off the redundant circuit. This has no impact on the application. Cold spare is achieved by implementing a high impedance between I/Os and VDD. The ESD protection is ensured through a non-conventional dedicated structure.

1.2Power-up

During power up, all outputs are forced to high impedance. The high-impedance state is maintained approximately until VDD is high, thus avoiding any transient and erroneous signals during power-up.

1.3Pin connections

Figure 2. Pin connections

!-V

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Functional description				54AC164245
	Table 3.	Pin descriptions
		Pin n°	Symbol	Name and function
	1		DIR1	Direction control inputs
	2, 3, 5, 6, 8, 9, 11, 12		1B1 to 1B8	Side B inputs or 3-state outputs (5 V port)
	4,10, 15, 21, 28, 34, 39, 45		VSS	Reference voltage to ground
	7, 18		VDD1	Supply voltage (5 V)
	13, 14, 16, 17, 19, 20, 22, 23		2B1 to 2B8	Side B inputs or 3-state outputs (5 V port)
	24		DIR2	Direction control inputs
	25		nG2	Output enable inputs (active low)
	31, 42		VDD2	Supply voltage (3.3 V)
	47, 46, 44, 43, 41, 40, 38, 37		1A1 to 1A8	Side A inputs or 3-state outputs (3.3 V port)
	36, 35, 33, 32, 30, 29, 27, 26		2A1 to 2A8	Side A inputs or 3-state outputs (3.3 V port)
	48		nG1	Output enable inputs (active low)

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54AC164245	Absolute maximum ratings and operating conditions

2 Absolute maximum ratings and operating conditions

Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

Table 4.	Absolute maximum ratings (1) (2) (3)
Symbol	Parameter	Value	Unit
VDD1	5 V supply voltage (4)	-0.3 to +6.0	V
VDD2	3 V supply voltage	-0.3 to +6.0	V
VIA	DC input voltage range port A	-0.3 to VDD1+0.3 V	V
VIB	DC input voltage range port B	-0.3 to VDD1+0.3 V	V
VOA	DC output voltage range port A	-0.3 to VDD1+0.3 V	V
VOB	DC output voltage range port B	-0.3 to VDD1+0.3 V	V
IIA	DC input currents port A, anyone input	± 10	mA
IIB	DC input currents port B, anyone input	± 10	mA
Tstg	Storage temperature range	-65 to +150	°C
TL	Lead temperature (10 sec)	300	°C
TJ	Junction temperature range	175	°C
Rthja	Thermal resistance junction to ambient (5)	TBD	°C/W
	Flat package, 48 pins
Rthjc	Thermal resistance junction to case(5)	TBD	°C/W
	Flat package, 48 pins
ESD	HBM: human body model(6)	2	kV

1.Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.

2.Unless otherwise noted, all voltages are referenced to VSS.

3.The limits for the parameters specified herein shall apply over the full specified VDD range and case temperature range of -55°C to +125°C.

4.VDD1 (5 V) may remain disconnected.

5.Short-circuits can cause excessive heating and destructive dissipation. Values are typical.

6.Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.

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Absolute maximum ratings and operating conditions						54AC164245
	Table 5.		Operating conditions (1)
	Symbol		Parameter			Value	Unit
	VDD1		Supply voltage			4.5 to 5.5 or 2.3 to 3.6	V
	VDD2		Supply voltage			2.3 to 3.6 or 4.5 to 5.5	V
		VI	Input voltage			0 to VDD1	V
	VO		Output voltage			0 to VDD1	V
	Top		Operating temperature			-55 to +125	°C
	d	/ d	Input rise and fall time V	CC	= 3.0, 4.5 or 5.5 (2)	0 to 8	ns / V
	t	v

1.Unless otherwise noted, all voltages are referenced to VSS.

2.Derate system propagation delays by difference in rise time to switch point for tr or tf > 1 ns/V.

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54AC164245	Electrical characteristics

3 Electrical characteristics

Top = -55°C to +125°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 2.7 V to 3.6 V, unless otherwise

specified.

Table 6.

DC specifications (1)

Symbol

Parameter

Port

Test condition (V ) (2)

Limits

Unit

voltage

DD

Min.

Max.

3.3 V

VDD1

= 4.5 and 5.5 V

0.7 VDD2

Schmitt trigger positive going

VDD2 = 2.7 and 3.6 V

threshold port A

5.0 V

VDD1

= 4.5 and 5.5 V

0.7 VDD2

VDD2

= 4.5 and 5.5 V

VT+

V

3.3 V

VDD2

= 2.7 and 3.6 V

0.7 VDD1

Schmitt trigger positive going

VDD1 = 2.7 and 3.6 V

threshold port B

5.0 V

VDD1

= 4.5 and 5.5 V

0.7 VDD1

VDD2 = 2.7 and 3.6 V

3.3 V

VDD1

= 4.5 and 5.5 V

0.3 VDD2

Schmitt trigger positive going

VDD2 = 2.7 and 3.6 V

threshold port A

5.0 V

VDD1

= 4.5 and 5.5 V

0.3 VDD2

VDD2

= 4.5 and 5.5 V

VT-

V

3.3 V

VDD1

= 2.7 and 3.6 V

0.3 VDD1

Schmitt trigger positive going

VDD2 = 2.7 and 3.6 V

threshold port B

5.0 V

VDD1

= 4.5 and 5.5 V

0.3 VDD1

VDD2 = 2.7 and 3.6 V

3.3 V

VDD1

= 4.5 and 5.5 V

0.4

Schmitt trigger range of

VDD2 = 2.7 and 3.6 V

hysteresis port A

5.0 V

VDD1

= 4.5 and 5.5 V

0.6

VDD2

= 4.5 and 5.5 V

VH

V

3.3 V

VDD1

= 2.7 and 3.6 V

0.4

Schmitt trigger range of

VDD2 = 2.7 and 3.6 V

hysteresis port B

5.0 V

VDD1

= 4.5 and 5.5 V

0.6

VDD2 = 2.7 and 3.6 V

Input current high port A (for

3.3 V

VDD1

= 5.5 V

3

VDD2 = 3.6 V

input under test VI = VDD2 other

VDD1

= 5.5 V

inputs, V = V

DD2

or V

SS

)

5.0 V

3

I

VDD2

= 5.5 V

IIH

µA

Input current high port B (for

3.3 V

VDD1

= 3.6 V

3

VDD2 = 3.6 V

input under test VI = VDD1 other

VDD1

= 5.5 V

inputs, V = V

DD1

or V

SS

)

5.0 V

3

I

VDD2 = 3.6 V

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