54AC164245
Rad-hard 16-bit transceiver, 3.3 V to 5 V bidirectional level shifter
Features
■Fully compatible with 54ACS164245
■Dual supply bidirectional level shifter
■Extended voltage range from 2.3 V to 5.5 V
■Separated enable pin for 3-state output
■Schmidt-triggered I/Os: 100 mV hysteresis
■Internal 26 Ω limiting resistor on each I/O
■High speed: Tpd = 8 ns maximum
■Bus hold
■Fail safe
■Cold spare
■Hermetic package
■100 krad (Si) at any Mil1019 dose rate
■SEL immune to 110MeV.cm2/mg LET ions
■RHA QML-V qualified
Description
The 54AC164245 is a rad-hard advanced highspeed CMOS, Schmitt trigger 16-bit bidirectional multi-purpose transceiver with 3-state outputs and cold sparing.
Designed for use as an interface between a 5 V bus and a 3.3 V bus in mixed 5 V/3.3 V supply systems, it achieves high-speed operation while maintaining the CMOS low-power dissipation.
Datasheet − production data
Ceramic Flat-48
The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package
All pins have cold spare buffers to change them to high impedance when VDD is tied to ground.
This IC is intended for two-way asynchronous communication between the data buses and the direction of the data transmission is determined by the nDIR inputs.
The A port interfaces with the 3.3 V bus but can also operate at 2.3 V. The B port operates with the 5 V bus.
Table 1. |
Device summary |
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Reference |
SMD pin |
Quality |
Package |
Lead |
Mass |
EPPL |
Temp range |
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level |
finish |
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RHRAC164245K1 |
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Engineering |
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Gold |
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model |
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-55 °C |
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Flat-48 |
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1.50 g |
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RHRAC164245K01V |
5962R9858008VYC |
QMLV- |
Gold |
Target |
to +125 °C |
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Flight |
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Note: |
Contact your ST sales office for information on the specific conditions for products in die form. |
April 2012 |
Doc ID 18093 Rev 2 |
1/22 |
This is information on a product in full production. |
www.st.com |
Functional description |
54AC164245 |
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66PORT |
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66PORT |
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Table 2. |
Function table |
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Enable, |
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Direction, DIRx |
Operation |
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OEx |
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L |
L |
B data to A bus |
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L |
H |
A data to B bus |
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H |
X |
Isolation |
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2/22 |
Doc ID 18093 Rev 2 |
54AC164245 |
Functional description |
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The 54AC164245 features a cold spare input and output buffers. In high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 V (VDD = VSS, VDD - VSS = 0 V) without affecting the bus signals or injecting current from the I/Os to the power supplies. Cold sparing also allows to keep unpowered redundant devices so that they can be switched on only when required. Power consumption is therefore reduced by switching off the redundant circuit. This has no impact on the application. Cold spare is achieved by implementing a high impedance between I/Os and VDD. The ESD protection is ensured through a non-conventional dedicated structure.
During power up, all outputs are forced to high impedance. The high-impedance state is maintained approximately until VDD is high, thus avoiding any transient and erroneous signals during power-up.
!-V
Doc ID 18093 Rev 2 |
3/22 |
Functional description |
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54AC164245 |
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Table 3. |
Pin descriptions |
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Pin n° |
Symbol |
Name and function |
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1 |
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DIR1 |
Direction control inputs |
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2, 3, 5, 6, 8, 9, 11, 12 |
1B1 to 1B8 |
Side B inputs or 3-state outputs (5 V port) |
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4,10, 15, 21, 28, 34, 39, 45 |
VSS |
Reference voltage to ground |
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7, 18 |
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VDD1 |
Supply voltage (5 V) |
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13, 14, 16, 17, 19, 20, 22, 23 |
2B1 to 2B8 |
Side B inputs or 3-state outputs (5 V port) |
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24 |
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DIR2 |
Direction control inputs |
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25 |
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nG2 |
Output enable inputs (active low) |
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31, 42 |
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VDD2 |
Supply voltage (3.3 V) |
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47, 46, 44, 43, 41, 40, 38, 37 |
1A1 to 1A8 |
Side A inputs or 3-state outputs (3.3 V port) |
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36, 35, 33, 32, 30, 29, 27, 26 |
2A1 to 2A8 |
Side A inputs or 3-state outputs (3.3 V port) |
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48 |
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nG1 |
Output enable inputs (active low) |
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4/22 |
Doc ID 18093 Rev 2 |
54AC164245 |
Absolute maximum ratings and operating conditions |
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Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
Table 4. |
Absolute maximum ratings (1) (2) (3) |
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Symbol |
Parameter |
Value |
Unit |
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VDD1 |
5 V supply voltage (4) |
-0.3 to +6.0 |
V |
VDD2 |
3 V supply voltage |
-0.3 to +6.0 |
V |
VIA |
DC input voltage range port A |
-0.3 to VDD1+0.3 V |
V |
VIB |
DC input voltage range port B |
-0.3 to VDD1+0.3 V |
V |
VOA |
DC output voltage range port A |
-0.3 to VDD1+0.3 V |
V |
VOB |
DC output voltage range port B |
-0.3 to VDD1+0.3 V |
V |
IIA |
DC input currents port A, anyone input |
± 10 |
mA |
IIB |
DC input currents port B, anyone input |
± 10 |
mA |
Tstg |
Storage temperature range |
-65 to +150 |
°C |
TL |
Lead temperature (10 sec) |
300 |
°C |
TJ |
Junction temperature range |
175 |
°C |
Rthja |
Thermal resistance junction to ambient (5) |
TBD |
°C/W |
Flat package, 48 pins |
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Rthjc |
Thermal resistance junction to case(5) |
TBD |
°C/W |
Flat package, 48 pins |
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ESD |
HBM: human body model(6) |
2 |
kV |
1.Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.
2.Unless otherwise noted, all voltages are referenced to VSS.
3.The limits for the parameters specified herein shall apply over the full specified VDD range and case temperature range of -55°C to +125°C.
4.VDD1 (5 V) may remain disconnected.
5.Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
6.Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.
Doc ID 18093 Rev 2 |
5/22 |
Absolute maximum ratings and operating conditions |
54AC164245 |
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Table 5. |
Operating conditions (1) |
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Symbol |
Parameter |
Value |
Unit |
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VDD1 |
Supply voltage |
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4.5 to 5.5 or 2.3 to 3.6 |
V |
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VDD2 |
Supply voltage |
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2.3 to 3.6 or 4.5 to 5.5 |
V |
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VI |
Input voltage |
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0 to VDD1 |
V |
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VO |
Output voltage |
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0 to VDD1 |
V |
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Top |
Operating temperature |
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-55 to +125 |
°C |
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d |
/ d |
Input rise and fall time V |
CC |
= 3.0, 4.5 or 5.5 (2) |
0 to 8 |
ns / V |
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v |
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1.Unless otherwise noted, all voltages are referenced to VSS.
2.Derate system propagation delays by difference in rise time to switch point for tr or tf > 1 ns/V.
6/22 |
Doc ID 18093 Rev 2 |
54AC164245 |
Electrical characteristics |
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Top = -55°C to +125°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 2.7 V to 3.6 V, unless otherwise
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specified. |
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Table 6. |
DC specifications (1) |
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Symbol |
Parameter |
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Port |
Test condition (V ) (2) |
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Limits |
Unit |
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voltage |
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DD |
Min. |
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Max. |
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3.3 V |
VDD1 |
= 4.5 and 5.5 V |
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0.7 VDD2 |
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Schmitt trigger positive going |
VDD2 = 2.7 and 3.6 V |
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threshold port A |
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5.0 V |
VDD1 |
= 4.5 and 5.5 V |
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0.7 VDD2 |
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VDD2 |
= 4.5 and 5.5 V |
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VT+ |
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V |
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3.3 V |
VDD2 |
= 2.7 and 3.6 V |
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0.7 VDD1 |
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Schmitt trigger positive going |
VDD1 = 2.7 and 3.6 V |
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threshold port B |
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5.0 V |
VDD1 |
= 4.5 and 5.5 V |
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0.7 VDD1 |
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VDD2 = 2.7 and 3.6 V |
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3.3 V |
VDD1 |
= 4.5 and 5.5 V |
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0.3 VDD2 |
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Schmitt trigger positive going |
VDD2 = 2.7 and 3.6 V |
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threshold port A |
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5.0 V |
VDD1 |
= 4.5 and 5.5 V |
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0.3 VDD2 |
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VDD2 |
= 4.5 and 5.5 V |
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VT- |
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V |
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3.3 V |
VDD1 |
= 2.7 and 3.6 V |
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0.3 VDD1 |
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Schmitt trigger positive going |
VDD2 = 2.7 and 3.6 V |
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threshold port B |
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5.0 V |
VDD1 |
= 4.5 and 5.5 V |
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0.3 VDD1 |
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VDD2 = 2.7 and 3.6 V |
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3.3 V |
VDD1 |
= 4.5 and 5.5 V |
0.4 |
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Schmitt trigger range of |
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VDD2 = 2.7 and 3.6 V |
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hysteresis port A |
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5.0 V |
VDD1 |
= 4.5 and 5.5 V |
0.6 |
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VDD2 |
= 4.5 and 5.5 V |
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VH |
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V |
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3.3 V |
VDD1 |
= 2.7 and 3.6 V |
0.4 |
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Schmitt trigger range of |
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VDD2 = 2.7 and 3.6 V |
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hysteresis port B |
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5.0 V |
VDD1 |
= 4.5 and 5.5 V |
0.6 |
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VDD2 = 2.7 and 3.6 V |
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Input current high port A (for |
3.3 V |
VDD1 |
= 5.5 V |
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3 |
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VDD2 = 3.6 V |
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input under test VI = VDD2 other |
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VDD1 |
= 5.5 V |
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inputs, V = V |
DD2 |
or V |
SS |
) |
5.0 V |
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3 |
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I |
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VDD2 |
= 5.5 V |
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IIH |
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µA |
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Input current high port B (for |
3.3 V |
VDD1 |
= 3.6 V |
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3 |
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VDD2 = 3.6 V |
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input under test VI = VDD1 other |
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VDD1 |
= 5.5 V |
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inputs, V = V |
DD1 |
or V |
SS |
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5.0 V |
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3 |
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I |
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VDD2 = 3.6 V |
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Doc ID 18093 Rev 2 |
7/22 |