SPT SPT9210SCS Datasheet

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: (719) 528-2300 FAX: (719) 528-2370

FEATURES

• NTSC/PAL Compatible

• Composite/S-Video Input Selection Mux

• Integrated Dual Analog Signal Path

• Adjustable Internal Anti-Alias Filters

• Internal Clamp Circuits

• Automatic Gain Control

• Integrated Reference Voltage Source for SPT7852

• Matched Voltage Output Range for Driving SPT7852

BLOCK DIAGRAM

APPLICATIONS

• High-End NTSC/PAL Video Decoding

• High Quality S-Video Decoding

• Video Frame Grabbing

• Professional Video

• VCR Signal Capture

• Security Cameras

GENERAL DESCRIPTION

The SPT9210 is the analog front-end processing chip for the SPT video decoder chip set. The video decoder chip set is an integrated three chip solution for high quality video signal decoding of NTSC/PAL composite video and S-Video formats at 8.9 effective number of bits of dynamic performance.

The SPT9210 is a fully integrated analog video processor chip capable of processing standard video signals in either a single-channel composite video input mode or a dual-channel S-Video (component Y/C) input mode. As part of the chip set, the SPT9210 is specially designed to easily interface to the downstream SPT7852 dual 10-bit analog-to-digital converter (See figure 1.)

SPT9210

ANALOG VIDEO PROCESSOR

174 1810

9 7 8 12 13 11

Clamp

Bias

Low Pass

Filter

Low Pass

Filter

Sync

Separation

Automatic

Gain Control

Automatic

Gain Control

Gain Detect

Delay

Clamp

Voltage Regulator

Frequency

Adjustment

Vref

1 16 15

Select SW

Input Y

Input C

Vcc

Input Y/C

GND Vref

Vref

Clamp

Filter Adj.

VRL

Adjust

VRL

Force

VRL

Sense

VRH

Sense

VRH

Force

VRH

Adjust

Output C

Output Y

C-Clamp C

C-AGC C-Clamp Y

The SPT9210 provides luminance and chrominance channel DC restoration, anti-alias filtering, automatic gain control and signal offset and gain to match the front-end requirements of the SPT7852 dual 10-bit analog-to-digital converter.

In addition to performing the analog processing of the video signal before data conversion, the SPT9210 also provides the voltage reference sources for the SPT7852. The SPT9210 is available in a 20-lead SOIC package and operates over the commercial temperature range. It requires a single +5 V supply and dissipates 620 mW of power.

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SPT9210

ELECTRICAL SPECIFICATIONS

TA=+25 °C, VIN=1.0 V

P-P

, VCC=+5.0 V, unless otherwise specified.

TEST TEST

PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS

Video Signal Output

Y/C Output Amplitude (pin 14) Composite/S-Video Mode 2.5 V

P-P

C Output Amplitude (pin 6) S-Video Mode 0.7 V

P-P

Differential Gain Composite/S-Video Mode 0.5 % Differential Phase Composite/S-Video Mode 0.5 Degrees

Automatic Gain Control

Y/C Output Amplitude (pin 14) VIN=+3 dB 2.5 V

Composite/S-Video Mode

Y/C Output Amplitude (pin 14) V

=-6 dB 2.5 V

Composite/S-Video Mode

C Output Amplitude (pin 6) VIN=+3 dB 0.7 V

S-Video Mode

C Output Amplitude (pin 6) VIN=-6 dB 0.7 V

S-Video Mode

Clamp Circuit

Sync Tip Offset Level Composite/S-Video Mode 1.0 V C Output Bias Voltage S-Video Mode 2.5 V

Anti-Alias Filter Chrominance Signal Side

Frequency Response f

=3 MHz, VIN=0 dB 7.96 dB

Frequency Response fIN=5 MHz, VIN=0 dB 4.96 dB

Voltage Reference

(Top of Ladder) I

OUT

=+5 mA 3.6 V

VRL(Bottom of Ladder) I

OUT

=+5 mA 1.0 V

Digital Input (Select SW pin 1)

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V

Power Supply

Supply Current I

No Signal 70 mA

Supply Voltage V

4.75 5.75 V

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)

Supply Voltage

VCC...........................................................................+6 V

Temperature

Operating Temperature ................................. 0 to +70 °C

Junction Temperature ......................................... +175 °C

Lead Temperature, (soldering 3 seconds).......... +320 °C

Storage Temperature................................ -55 to +150 °C

Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal

applied conditions in typical applications.

TEST LEVEL CODES

All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.

TEST PROCEDURE

100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested

at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and

characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is

guaranteed over specified temperature range.

TEST LEVEL

III IV

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SPT9210

Figure 1 - SPT Video Decoder Chip Set

SPT VIDEO CHIP SET APPLICATION

The SPT9210 is the front-end analog video processor for the SPT NTSC/PAL video decoder chip set. This chip set, as shown in figure 1, is comprised of three monolithic chips, which together provide an overall integrated video decoding functionality at 8.9 effective number of bits of dynamic performance.

The full set includes the SPT9210 analog video processor, the SPT7852 dual 10-bit analog-to-digital converter and the SPT2110 NTSC/PAL video decoder. The SPT9210 is specifically designed to process video input signals so as to attain optimal data conversion by the SPT7852 analog-to-digital converter. Data sheets describing the overall chip set and the other components are available by contacting the factory.

SPT9210 GENERAL DESCRIPTION

P-P

video signals are amplified to match the optimal drive requirements of the SPT7852 dual 10-bit analog-to-digital converter.

INPUT SELECTION

As the typical interface circuit shows in figure 3, the mux selector pin (pin 1) controls selection between composite and S-Video (component Y/C). This is a TTL-level input. When composite video is selected (pin 1 high), the composite signal (pin 19) is fed into the luminance channel, and the chrominance channel is internally biased (i.e., no input is sourced). When S-Video is selected (pin 1 low), the S-Video luminance signal (pin 2) is fed into the luminance channel, and the SVideo chrominance signal (pin 3) is fed into the chrominance channel.

In addition to pin 19, another composite video signal can be applied to input pin 2. Pin 1 selects which video signal is to be processed. (Pin 1 high selects input from pin 19.) When operating with composite video on pin 2, decouple pin 3 to ground with a 0.1 µF capacitor (the chrominance input for Svideo). This will reduce the noise produced on this input.

A register or TTL buffer can drive pin 1 (video select switch). An optional transistor circuit is shown in figure 3. It is driven by the pin 1 signal with the collector tied to pin 3. It is used to reduce crosstalk that may occur when both composite and SVideo signals are operating simultaneously. The transistor circuit is only necessary if both signals are present.

All input video signals should be terminated with 75 Ω resistors and AC coupled to the SPT9210 with a 0.47 µF capacitor.

INTERNAL CLAMP, BIAS AND SYNC DETECTION

The signals fed into the luminance channel (pins 2 and 19), which are either a composite signal or a luminance (Y) signal, are internally DC restored to 2.0 V by an internal clamp circuit. Note that this is not the final output clamp voltage as discussed in the Final DC Clamp and Gain Stages section. The chrominance signal (pin 3) is biased to 2.5 V by an internal bias circuit.

The luminance signal path has a sync separation circuit that compares the sync signal to a detection threshold and generates internal gain control and output clamping control signals. These timing signals are used to control internal sampling of the sync tip amplitude by the automatic gain control circuit. (See the Automatic Gain Control discussion.)

Trap Filter

Y/C Separator

(Comb)

Luma

Processing

Chroma

Processing

Timing Generation

Control Parameter

Registers

Color Space

Conversion

10-Bit ADC

2X Clock MPU Interface

HSYNC VSYNC HBLNK VBLNK ODD

B u

Output Enable

Reset

Ref

Ladder

Timing

Pixel Clock

Reset

R Y

G Cr/Cb

Ext Adj

Clamp

LPF

AGC

Clamp

LPF

AGC

ADC VRef

Composite

Video Signal

S-Video

Y Signal

S-Video

C Signal

Select

Bias

Sync Det

SPT2110SPT7852SPT9210

u x

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SPT9210

ANTI-ALIAS FILTERS

Both luminance and chrominance video signal paths have an anti-alias filter with a cut-off frequency of approximately

4.8 MHz. The cut-off frequency can be changed by an external resistor value. The relationship between the external resistance value and the cut-off frequency is shown in the Typical Performance Curves section.

AUTOMATIC GAIN CONTROL

The SPT9210 performs automatic gain control (AGC) of the composite/luminance and chrominance signals. The horizontal sync signal level is used as a reference for control of the signal gain. The chrominance signal gain is slaved to the luminance gain value.

The gain circuitry can operate over an input voltage range of VIN = -6 dB to +3 dB (where 1 V

P-P

= 0 dB). The AGC will

maintain a 2.5 V

P-P

amplitude on the composite/luminance

signal output and 0.7 V

P-P

amplitude on the chrominance signal output. The AGC settling time can be adjusted via an external capacitor. SPT recommends using a 0.47 µF capacitor for most conditions. In cases where extreme fluctuation is possible, a diode inserted between pins 7 and 16 will restrict the maximum control voltage. This will serve to reduce recovery time.

FINAL DC CLAMP AND GAIN STAGES

After the clamp, low pass filtering and automatic gain control functions are performed. Each signal path is clamped to a fixed DC value and amplified to the proper voltage range for input into the SPT7852 analog-to-digital converter. The analog sync signal is retained in the output of the SPT9210 and passed on to the SPT7852 and SPT2110 NTSC/PAL video decoder.

For the composite/luminance output, the horizontal sync level is clamped to +1 V, and the full-scale amplitude of the composite luminance signal (including sync tip) is set to

2.5 V

P-P

amplitude by the AGC. (See figure 2.) The generated signal is optimized for SPT7852 performance (+1.0 to +3.5 V input range). The chrominance output signal is biased to

+2.5 V and a 0.7 V

P-P

full-scale amplitude is maintained by

the AGC. The output drive circuit is optimized for interface to the

SPT7852. When driving loads other than the SPT7852 (which have a capacitance >TBD µF), it may be necessary to insert a series resister between the output and the load so as to avoid oscillation.

ON-CHIP VOLTAGE REFERENCES

In addition to performing the analog processing of the video signal before data conversion, the SPT9210 also provides the voltage reference sources (force and sense for the top and bottom of the reference ladder) required by the SPT7852. This eliminates the need for external reference sources. A source of +3.5 V is provided to the top of the reference ladder and +1.0 V is provided to the bottom.

Pin 7 is the VL reference force pin and is tied to pin 4 of the SPT7852. Pin 13 is the VH reference force pin and is tied to pin 1 of the SPT7852. A 240 Ω resistor should be tied between pin 7 and pin 13 on the SPT9210. Pin 8 is the VL reference sense pin and is tied to pin 3 of the SPT7852. Pin 8 is the V

reference sense pin and is tied to pin 2 of the SPT7852. The values of VL and VH can be adjusted by changing the

external resistor values at pins 9 and 11, respectively. The curves in the Typical Performance Curve section show the voltage reference output values versus the external resistance values. The typical values for nominal +1.0 V and +3.5 V operation on VL and VH are approximately 10 kΩ and 25 kΩ, respectively.

The V

Ref

clamp pins need decoupling capacitors as shown in figure 3. Each pin should have a 0.1 µF and 10 µF capacitor connected in parallel for proper decoupling.

OTHER INFORMATION

The SPT9210 is available in a 20-lead SOIC package and operates over the commercial temperature range. It requires a single +5 V supply and dissipates 620 mW of power.

Figure 2 - Composite/Luminance Signal I/O Relationship

1.0 Vpp

SPT9210

3.5 V

1.0 V

0.0 V

Pin 2

Pin 19

Pin 14

Input Signal Output Signal

Composite

Signal

Y Signal

Composite/Y

Output

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