SPT SPT8100SIT Datasheet
SPT8100
16-BIT, 5 MSPS CMOS A/D CONVERTER
FEATURES
• 16-bit, 5 MSPS CMOS analog-to-digital converter
• On-chip PGA: gain range from 0 to 20 dB in seven
selectable settings:
0 dB, +3 dB, +6 dB, +12 dB, +15 dB, +18 dB, +20 dB
• DNL: ±0.5 LSB, INL: ±1.25 LSB
• SFDR: 94 dB @ ƒIN = 900 kHz, –8.1 dBFS
• Internal sample-and-hold and voltage reference
• Power dissipation: 465 mW at 5 MSPS; 230 mW at
2.5 MSPS
• +5 V analog supply and +3.3 to +5.25 V digital output
supply
• 44-lead LQFP plastic package.
GENERAL DESCRIPTION
The SPT8100 is a high performance, 16-bit analog-to-digital
converter that operates at a sample rate of up to 5 MSPS.
Excellent dynamic performance and high linearity is
achieved by a digitally calibrated pipelined architecture fabricated in CMOS process technology.
A low-noise programmable gain amplifier (PGA) is also incorporated on chip. The PGA is digitally programmable in
seven selected settings over a 0 to +20 dB range. The
APPLICATIONS
• Data acquisition systems
• IR imaging
• Scanners and digital copiers
• High-end CCD cameras
• Medical imaging
• Wireless communications
• Lab and test equipment
• Automatic test equipment
SPT8100 also features an on-chip internal sample-and-hold
and internal reference for minimal external circuitry.
It operates from a single +5 V supply. Total power dissipation, including internal reference, is 465 mW. A separate
digital output supply pin is provided for +3.3 V or 5 V logic
output levels. The SPT8100 is available in a 44-lead LQFP
package over the industrial temperature range of –40 °C to
+85 °C.
BLOCK DIAGRAM
Signal Processing Technologies, Inc.
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
V
IN
V
V
CM
GS2 – GS0
(Gain Set)
AV
+5V
Low-Noise
PGA
+
–
IN
VREF
AGND
BIAS
OGNDDGND
(Ext Bias
Capacitor)
BIAS
C
(Ext Bias
Resistor)
DV
DD
16-bit, 5 MSPS ADC
V
R
RTVRB
+5V
OV
DD
DD
+3/5 V
16-bits
CLK
4755 Forge Road, Colorado Springs, Colorado 80907, USA
OE (Output Enable)
OVR (Over-Range)
D15 – D0
(Data Outputs)
RS (Reset)
RDY (Ready)
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
DD
Output
Digital Outputs ......................................................10 mA
Temperature
Operating Temperature ............................. –40 to +85 °C
Junction Temperature ........................................+175 °C
Lead Temperature (soldering 10 seconds) ........ +300 °C
Storage Temperature ..............................–65 to +150 °C
Supply Voltages
AVDD........................................................................+6 V
DVDD........................................................................+6 V
OVDD........................................................................+6 V
Input Voltages
Analog Input................................... –0.5 V to VDD +0.5 V
CLK Input..................................................................V
AV
– DVDD.....................................................±100 mV
DD
Delta between AGND, DGND, and OGND .......±100 mV
Note 1: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA=T
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Resolution 16 Bits
DC Accuracy
MIN
to T
, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, R
MAX
=1.43 kΩ, unless otherwise specified.
EXT
TEST TEST SPT8100
Integral Nonlinearity V ±1.25 LSB
Differential Nonlinearity V ±0.5 LSB
Gain Error
Offset Error
1
2
VI –7.5 +7.5 %FSR
V –5 +5 %FSR
Analog Input (into PGA)
Differential Input Voltage Range
+, VIN–V5V
V
IN
PP
Input Capacitance IV 15 pF
Input Resistance
Input Bandwidth
3
4
PGA Gain = 0 dB IV 5.5 kΩ
V 11 MHz
Input Common Mode Voltage Range V 1.1 2.35 3.6 V
Programmable Gain Amp
Composite Input-Referred PGA Gain = 0 dB V 45.0 nV/√Hz
Noise Floor PGA Gain = 20 dB V 8.0 nV/√Hz
> 300 kHz
ƒ
IN
PGA Range V 20 dB
PGA Gain Steps
3
VI 3,6,12,15,18,20 dB
PGA Gain Accuracy VI ±0.3 dB
Conversion Characteristics
Maximum Conversion Rate VI 5 MHz
Pipeline Delay (Latency) IV 6
Clock Cycles
Reset Pulse Time (RS) IV 3 Clock Cycles
Reset Calibration Time FS = 5 MSPS V 150 ms
References and External Bias
– VRB (Internal Ref) VI 2.375 2.5 2.625 V
V
RT
Bias Resistor Range (External) IV 800 1430 2500 Ω
Output Voltage IV 2.23 2.35 2.47 V
V
CM
Output Current IV 50 µA
V
CM
V
RT
V
RB
1
Total gain error of PGA and ADC using internal references.
2
Total offset error of PGA and ADC relative to mid-scale.
3
See table I for input resistance as a function of PGA gain.
4
Input bandwidth is a frequency to which the fundamental energy drops by 3 dB
IV 3.45 3.65 3.85 V
IV 0.95 1.15 1.35 V
SPT
SPT8100
2 5/12/00
ELECTRICAL SPECIFICATIONS
TA=T
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
Dynamic Performance
MIN
to T
, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, R
MAX
=1.43 kΩ, unless otherwise specified.
EXT
TEST TEST SPT8100
1
Effective Number of Bits ADC Input = –1 dBFS
ƒ
= 60 kHz VI 12.2 13.0 Bits
IN
= 900 kHz V 12.7 Bits
ƒ
IN
2
Signal-to-Noise Ratio
(without Harmonics) ADC Input = –1 dBFS
ƒ
= 75 kHz VI 78 81 dB
IN
ƒ
= 900 kHz V 80 dB
IN
2
Harmonic Distortion ADC Input = –0.5 dBFS
= 60 kHz V –92 –84 dB
ƒ
IN
ƒ
= 900 kHz VI –82 dB
IN
Signal-to-Noise and Distortion
(SINAD) ADC Input = –1 dBFS
= 60 kHz V 75 80 dB
ƒ
IN
= 900 kHz VI 78 dB
ƒ
IN
Spurious Free Dynamic Range
ƒ
= 60 kHz ADC Input = –0.5 dB VI 85 94 dBc
IN
= 900 kHz VI 94 dBc
ƒ
IN
= 2 MHz R
ƒ
IN
ƒIN = 3 MHz R
3
= 1 kΩ @ 10 MSPS V 83 dBc
EXT
= 1 kΩ @ 10 MSPS V 78 dBc
EXT
Two-Tone Intermodulation
3rd Order Distortion ƒ
=400 kHz, ƒ2=410 kHz
1
ƒ1=890 kHz, ƒ2=900 kHz
4
V –94 dB
5
VI –89 dB
Inputs
GS0–GS2 Logic 1 Voltage VI 2.4 V
GS0–GS2 Logic 0 Voltage VI 0.8 V
CLK, RS Logic 1 Voltage VI 2.0 V
CLK, RS Logic 0 Voltage VI 0.8 V
Maximum Input Current Low VI –10 +10 µA
Maximum Input Current High VI –10 +10 µA
Input Capacitance V 5 pF
Digital Outputs
Logic 1 Voltage I
= –2 mA VI ODVDD – 0.5 V
OH
Logic 0 Voltage IOL = 2 mA VI 0.4 V
CLK to Output Delay Time (t
)C
D
= 20 pF IV 30 ns
LOAD
Power Supply Requirements
Voltages ODV
AV
DD
DV
Currents I
DD
DD
DD
IV 3.0 3.3 5.25 V
IV 4.75 5.0 5.25 V
IV 4.75 5.0 5.25 V
VI 93 103 mA
Power Dissipation VI 465 515 mW
1
Dynamic performance tested at ƒs=4.4 MSPS
2
0 dBFS is 5.0 V peak-to-peak differential
3
ADC Input = –8.1 dBFS, unless otherwise noted
TEST LEVEL CODES
TEST LEVEL TEST PROCEDURE
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level
column indicates the specific device
testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
4
Test Conditions: PGA setting of 6 dB; Analog Input at ADC = –0.7 dB
5
Test Conditions: PGA setting of 0 dB; Analog Input at ADC = –1.9 dB
I 100% production tested at the specified temperature.
II 100% production tested at T
= +25 °C, and sample tested at the specified
A
temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characterization
data.
V Parameter is a typical value for information purposes only.
VI 100% production tested at T
= +25 °C. Parameter is guaranteed over
A
specified temperature range.
SPT
SPT8100
3 5/12/00
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