SPT SPT2110SCT Datasheet

Signal Processing Technologies, Inc.

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: [phone] FAX: [phone]

SPT2110

NTSC/PAL VIDEO DECODER

FEATURES

• NTSC/PAL Video System Compatible

• Dual 9-Bit Wide Data Paths for Video Processing

• Composite or Component Video Inputs

• Supports Three Video Sampled Modes: Square Pixel,
ITU-R BT.601 (CCIR-601), and 4Fsc (NTSC Only)

• Sync Detector and Complete Timing Generator

• Comb Filters (NTSC)

• Two Output Formats: YCrCb (4:2:2), RGB (4:4:4)

• Picture Quality Adjustment Functions:

Luminance Signal: Peaking Compensation,

Contrast, Brightness

Chrominance Signal: Hue, Saturation

• MPU Interface Control

• 100-Lead PQFP Package

• +3.3 V Single Power Supply

BLOCK DIAGRAM

APPLICATIONS

• High-End NTSC or PAL Video Decoding

• S-Video Decoding

• Composite Video Decoding

• Video Frame Grabbers

• Video Projection and Displays

• Digital VCRs

• Digital Video Transmitters

• Video Printers

• Image Filing Systems

• Multimedia PCs

• Advanced Set-Top Boxes

• Security Cameras

GENERAL DESCRIPTION

The SPT2110 is a high-performance video digital signal
processor for NTSC and PAL applications. It processes 9-bit
composite digitized video or two 9-bit component digitized
video signals. All internal processing is done at 9 or more bits.
The decoder outputs the image data in YCrCb (4:2:2) or RGB
(4:4:4) formats. This product has many advanced internal

features not found in other decoder products. These features
include full 9-bit processing, AGC on both luminance and
chrominance processing, exceptional picture quality con­trols, complete timing generation and a simple MPU inter­face. All these features provide for easy digital video design
and produce digital image data that is free from dot error and
color noise. The SPT2110 video decoder is ideal for compos­ite or S-Video applications requiring high quality signal de­coding.

M

u
x

Trap Filter

M

u
x

Y/C Separator

(Comb)

Sample Alignment

Sample Alignment

Timing Generation

Control Parameter Registers

Color

Space

Conversion

MPU Interface

HSYNC
VSYNC
HBLNK
VBLNK
ODD
STATUS

9

9

CHR8 - 0

8

R Y

G Cr/Cb

B

5

8

8

8

Sample Alignment

CS WR RD RS D7-0

ClockReset OE

CBPF ACC

Demod

Demod

DTO

Burst

Comp

Sync Det

AGC

BPF

Coring

Peaking

LUM8 - 0

SYNC

SEP

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The SPT2110 is part of a three-chip solution for high quality
video signal decoding. The companion integrated circuits are
the SPT9210, a dual analog video processor, and the
SPT7852, dual 10-bit ADC. The SPT9210 provides internal
DC restoration and Automatic Gain Control (AGC) of the
video signal. The SPT7852 provides 10-bit resolution video
digitization.

The SPT2110 operates from a single +3.3 V supply. It is
available in a 100-lead PQFP package and operates over the
commercial temperature range.

GENERAL OVERVIEW

The SPT2110 video decoder is compatible with NTSC or PAL
video standards. It has two 9-bit digitized video inputs busses
and three 8-bit video data output busses with sync, blank,
field indicator and chrominance data indicator output signals.

The SPT2110 is fully programmable through the command
registers. Each command register is accessed by a single
address register. The control lines and the bidirectional 8-bit
data bus provide access to the command and address
registers.

DIGITAL VIDEO INPUT DATA BUSSES

The two 9-bit digital video input data busses have 3.3 volt
compatible logic levels. In composite mode, the composite
digital video is input through the LUM8…0, 9-bit data bus. In
component mode, the luminance component is input through
the LUM8…0, 9-bit data bus while the chrominance compo­nent is input through the CHR8…0, 9-bit data bus. Register 1
selects whether composite or component video input data will
be processed. The input busses expect valid data on each
rising edge of the clock input. Refer to the timing diagram,
figure 1.

Table I - Digital Image Input Busses Description

Bus Label Description

LUM8...0 Digitized video data for composite

video or the luminance signal input.
LUM8 is the MSB, and LUM0 is the LSB.

CHR8...0 Digitized video data for the chromi-

nance signal input. CHR8 is the MSB,
and CHR0 is the LSB.

DECODED DIGITAL VIDEO OUTPUT DATA
BUSSES

The three 8-bit digital video output data busses on the
SPT2110 have 3.3 volt compatible logic levels. All three
busses are used for RGB digital video data output. Two
busses are used for YC (YCrCb) digital video data. The RGB
data is NTSC or PAL video that has been translated to RGB
(4:4:4) format. The YC data is NTSC or PAL video that has
been translated to YCrCb (4:2:2) format. The luminance
portion of the YCrCb output (Y) is output on the Y/R7…0 bus,
and the color difference signal data (Cr and Cb) is output on
the C/B7…0 bus. Cr and Cb are alternately output every other
clock cycle. All three busses may be programmed to a tri­state level. Refer to the timing diagram, figure 1.

Table II - Digital Video Output Busses Description

Bus Label Description

Y/R7...0 Decoded video data for Y (luminance) or R

(red). Y/R7 is the MSB, and Y/R0 is the
LSB.

C/G7...0 Decoded video data for C (chrominance)

or G (green). C/G7 is the MSB, and C/G0
is the LSB.

B7...0 Decoded video data for B (blue). B7 is

the MSB, and B0 is the LSB.

VIDEO TIMING OUTPUT SIGNALS

The video timing output signals have 3.3 volt compatible logic
levels. They produce the temporal information that identifies
the spacial position of the video signal. They are used
downstream to synchronize signals and for odd/even field
identification. These discrete output timing control signals
may be programmed as positive or negative true logic or they
may be tri-stated.

The video timing output signals are described in table III. The
signal names are horizontal sync, vertical sync, horizontal
blank, vertical blank, odd/even field indicator and chromi­nance flag. Refer to timing diagrams 1, 3 and 4.

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Table III - Timing Control Signal Description

Signal
Label Description

HSYNC This is the horizontal synchronizing signal; its

width is equal to the width of the incoming
digitized video signal.

VSYNC This is the vertical synchronizing signal. 3H time

for NTSC starting after the three H lines of
equalizing pulses and 2.5H time for PAL starting
at beginning of line 1 and line 312.5.

HBLNK This is the horizontal blanking signal. Registers

DH and EH control the start and stop locations
of the active pixels. When this signal is
deasserted the following number of active video
pixels is displayed for the various sampling
modes.

- ITU-R BT.601 720 active pixels

- NTSC square pixel 640 active pixels

- NTSC4Fsc 768 active pixels

- PAL square pixel 768 active pixels

VBLNK This is the vertical blanking signal. Registers FH

and 10H control the start and stop locations of
the active lines.

ODD When active, this signal indicates that the odd

field is being output from the decoder.

CFLAG This signal indicates whether Cb or Cr data is

active.

Note: Due to asynchronous sampling of the video signal, a
periodic deviation of the sync width by one pixel clock may
be generated in HSYNC, VSYNC, HBLNK, VBLNK and
ODD signals.

CLOCK SIGNAL

The clock (CLK) input has is 3.3 volt compatible logic. The
clock is the master time-base controller for the SPT2110. The
SPT2110 synchronizes data input, data output, control signal
out, address and command register modifications and data
processing to the clock. A stable, jitter-free clock signal
should be used.

Table IV - Sample Mode Clock Frequencies

Sampling Mode Input Frequency (MHz)

NTSC Square Pixel 12.2727
NTSC ITU-R (CCIR-601) 13.500
NTSC 4 Fsc 14.3182
PAL Square Pixel 14.7500
PAL ITU-R (CCIR-601) 13.5000

MPU INTERFACE

The SPT2110 provides for microprocessor unit (MPU) based
programming and control through a 3.3 V compatible logic
interface. The MPU interface is comprised of a bidirectional
8-bit data bus and four discrete control registers. A descrip­tion of this interface is shown in table V.

COMMAND AND ADDRESS REGISTERS

The SPT2110 operational performance is controlled by inter­nal command registers that are accessed through the MPU
interface described above. There is one address register and
20 command registers (0H - 13H). All registers have read/
write capability.

The address register is used to identify the command register
to be operated. This register must be written to first with the
address of the target command register before a read/write
operation can be performed on the command register. Tables
VI and VII describe the normal operation for reading and
writing to the address register.

Most of the command registers control multiple functions, i.e.,
each bit or group of bits within a register controls a chip
function. When modifying a register a read of the register
should be performed first. Then alter the bit(s) while maintain­ing the rest of the bits in their present state. Finally, write the
modified data back into the register.

Tables VIII and IX describe the operation for reading and
writing to a selected command register. All registers have a
default setting when the STP2110 is reset. For a detailed
description of the functions of each register, refer to table XIII,
Command Register Description Table.

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Table V - MPU Interface Description

Signal Name Abbreviation Description

CHIP SELECT CS_ The Chip Select signal (active low logic) enables further action by the chip from the other

control lines This means the chip needs to process (recognize) one of the following

control signals: RS, WR_ or RD_.
REGISTER RS The Register Select signal (active high logic) enables access to the Command Register
SELECT that the address register is holding. When this signal is low it enables the address data

register.
WRITE WR_ The Write signal (active low logic) transfers the data on the data bus into the address or

command data register (depending on the level of RS).
READ RD_ The Read signal (active low logic) transfers the data in the address or command data

register (depending on the level of RS) onto the data bus.
DATA(7-0) D7-0 This is the 8-bit bidirectional data bus for transferring data to and from the SPT2110. The

direction is dictated by the WR_ (input) and RD_ (output) signals.

Refer to the Electrical Specification Table for correct interfacing of the SPT2110. Note the assert times required for each of
the control lines. The times must be a numerical multiple of the clock that operates the SPT2110.

The accessing of a Command register(s) is performed as shown in table VI below.
(Note that 1 defines logic high, 0 is logic low, X is defined as don’t care and D is valid data)

Table VI - Write Address Register

CONT.
STATE\
STEP CS_ WR_ RD_ RS DATA (7-0) COMMENTS

1 0110DDh
2 0010DDh Data needs to be valid on the data bus for minimum setup time

(relative to the WR_ signal).

3 0110DDh Data needs to remain valid on the data bus for minimum hold

time (relative to the WR_ signal).

4 111XXXh Completed Address Write

The address write sequence described above is a normal write sequence. A write can be performed by asserting
CS_ and RS (to logic low). Observe the minimum setup time before asserting WR_. Hold CS_ and RS for the hold
time and then release CS_ and RS. Then set the data bus to the valid address for the minimum setup time before
the rising edge of WR_. Then hold the data bus for the hold time required. Note that the WR_ assert time is a
multiple of the clock. This sequence will perform a valid write to the address register. The following read write
functions may be performed in a manner similar to the normal sequences outlined in the tables VII and VIII.

Table VII - Read Address Register
CONT.

STATE\
STEP CS_ WR_ RD_ RS DATA (7-0) COMMENTS

1 0110XXh
2 0100DDh Data is valid on the data bus after output delay time (relative to

the RD_ signal).

3 0110XXh Data continues to remain valid for output hold time delay (relative

to the RD_ signal).

4 111XXXh Completed Address Read.

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The following assumes the address register is already set.

Table VIII - Write Command Register

CONT.
STATE\
STEP CS_ WR_ RD_ RS Data (7-0) Comments

1 0111DDh
2 0011DDh Data needs to be valid on the data bus for minimum setup time

(relative to the WR_ signal).

3 0111DDh Data needs to remain valid on the data bus for minimum hold

time (relative to the WR_ signal).

4 111XXXh Completed Command Write.

Table IX - Read Command Register

CONT.
STATE\
STEP CS_ WR_ RD_ RS Data (7-0) Comments

1 0111XXh
2 0101DDh Data is valid on the data bus after output delay time (relative to

the RD_ signal).

3 0111XXh Data continues to remain valid for output hold time delay (relative

to the RD_ signal).

4 111XXXh Completed Command Read.

If the address already contains the correct address of the register to be accessed, it is not necessary to perform
an address register write. Only a command register acquisition is required to write or read the command register.

OTHER DISCRETE SIGNALS

The other signals not discussed are the Reset, Status and OE signals. The following table describes these functions.

Table X - Other Discrete Signals

Signal Input/
Name Output Description

RESET_ INPUT This signal is an input active low. It requires three or more input clocks while the signal

is active to reset the device. It resets all registers to their default states and clears all
data within the device.

STATUS_ OUTPUT This signal is an output active low signal. It will be asserted whenever video sync is

being detected and will go inactive when sync is not detected.

OE_ INPUT When asserted, this signal enables the output signals. This is an active low logic signal.

It tri-states the outputs when deasserted and enables them when asserted. The signals
that are controlled are the data output busses (RGB/YC), HSYNC, VSYNC, HBLNK,
VBLNK, ODD and CFLAG.

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LUMINANCE PROCESSING

LUMINANCE SEPARATION

For composite video the luminance needs to be separated
from chrominance in the baseband video. Each is processed
separately. Selection of the separation method is determined
by register 3H. Separation of the luminance from the chromi­nance is performed by a 2H comb, 1H comb or trap filter.
Comb filtering is available for NTSC signal processing only.
The comb is the best filter method for composite video. The
trap filter method of separation reduces the dynamic perfor­mance of the luminance signal above 2.3 MHz due to the filter
transfer function.

This separation is not necessary for component (Y/C, S-Video).
The comb filtering is inhibited, and the digitized data is sent
on to the luma processing circuitry.

SYNC SEPARATOR

The sync signals are separated from the luminance compo­nent and sent to the timing control circuit. The sync pulses are
used to synchronize the timing of the number of pixels per
line, number of lines, and odd field identification.

LUMINANCE MUX

A 2:1 mux is used to multiplex the digital luminance compo­nent data to either the trap filter or comb filter.

AGC

Automatic Gain Control (AGC) for the luminance signal is
derived from the amplitude of the sync signal. The video
luminance is scaled by the value derived from the sync signal
value. This is a very important feature for nonstandard video
signal values. In addition, the sync is removed from the
luminance signal at this stage before further luminance
processing.

PICTURE QUALITY FUNCTIONS

LUMINANCE SIGNAL CORRECTION

Luminance signal correction is composed of three luminance
digital signal processing functions. These functions include
selecting a frequency pass band that will be further en­hanced, a coring function and a peaking function. The peak­ing function must be set to a compensation value (other than
zero, default) for either of the other two functions to be
enabled. The Pass-Band (PBAND) Filter is controlled by
register 6H. It sets the lower limit of the pass band filter. These
frequencies will be peaked further downstream. The coring
function provides a hysteresis effect on pixel-to-pixel data
value changes based on a threshold coring level set by the
core register 7H. Coring is performed on the pre-peaked

signal levels. With the pass-band and the coring levels set,
the peaking compensation value is applied to those lumi­nance signals that fit in the selected profile. Peaking is a
multiplicative factor that gains up the selected frequencies.
The higher the peaking factor the more gain provided for
those selected frequencies. Peaking is controlled by register
8H.

Brightness is controlled by register 12H. This puts an additive
value to the luminance signal. This additive value is plus or
minus 32 LSBs of the luminance signal. It is a DC value for the
luminance signal. Brightness is applied after luminance sig­nal correction is performed.

Contrast is controlled by register 11H. This setting applies a
multiplying factor to the luminance signal. The coefficient
multiplies the luminance value after it has been corrected.

SYNC REINSERTION

The sync signals are reinserted into the luminance signal
after all luminance signal processing is performed.

LUMINANCE SAMPLE ALIGNMENT

Sample alignment circuitry ensures the same number of
pixels per line and field/frame. Counting registers control this
process based on the mode of operation. They determine the
number of pixels per line and the number of lines per field.

LUMINANCE COLOR SPACE CONVERSION

The color space conversion block uses the luminance signal’s
value to transform from the NTSC or PAL system format that
was originally digitized to either RGB of YCrCb. This process
requires the values of both luminance and chrominance be
synchronized in time to make this conversion correctly. The
transformation to RGB or YCrCb is performed using the
luminance and color difference signal data.

CHROMINANCE PROCESSING

COLOR SEPARATION

For composite video, the chrominance needs to be separated
from luminance in the baseband video. Each is processed
separately. Selection of the separation method is determined
by register 3H. Separation of the chrominance from the
luminance is performed by a 2H or 1H comb filter or the trap
filter. The comb separation is the best separation method for
composite video. Comb filtering is available for NTSC signal
processing only.

For component (Y/C, S-Video), this separation is not neces­sary. The comb filter is inhibited and the digitized chromi­nance data is sent on for chroma processing.