Spectrum Digital TMS320DM6437 Technical Reference

TMS320DM6437
Evaluation Module

Technical

Reference

2006 DSP Development Systems

TMS320DM6437 Evaluation

Module Technical Reference

509105-0001 Rev. C

December 2006

SPECTRUM DIGITAL, INC.

12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: [phone] Fax: [phone]

[e-mail] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,

copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digi tal Signal Processing development products or
services might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.

Copyright

© 2006 Spectrum Digital, Inc.

Contents

1 Introduction to the DM6437 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Provides you with a description of the DM6437 Evaluation Module, key features, and
block diagram.

1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.7 Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Describes the operation of the major board components on the DM6437 Evaluation Module.

2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Peripheral Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2.1 VL YNQ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2.2 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2.3 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.3 Video Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.3.1 Input Video Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.3.2 On Chip Video Output DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.4 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.5 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.6 I

2.6.1 I/O Expanders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.6.2 I

2.7 S/PDIF Analog, and Optical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.8 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.9 DM6437 Core CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.10 DM6437 Core Voltage Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2

C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Describes the physical layout of the DM6437 Evaluation Module and its connectors.

3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.1 J1, DAC A Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 5

3.2.2 J2, DAC B Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.3 J3, DAC C Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.4 J4, DAC A Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.5 J5, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.6 J10, S/PDIF Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.2.7 J16, +5V Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.2.8 J20, Mini PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.2.9 J501, Embedded Mini USB Emulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.2.10 P1, Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.2.1 1 P2, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.2.12 P3, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.2.13 P4, PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.2.14 P7, CAN Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.2.15 P8, RS-232 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.2.16 P10, Stereo Line In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.2.17 P11, Microphone In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.2.18 P12, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.2.19 P13, Stereo Line Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.2.20 P14, S/PDIF Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.2.21 DC_P1, Memory/Video Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.2.22 DC_P2, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.2.23 DC_P3, VLYNQ Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.3 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.3.1 JP1 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.3.2 JP2 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.3.3 JP3 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.3.4 JP4 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.5 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.5.1 SW1, Bootload Mode Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.5.2 SW2, Bootload Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.5.3 SW3, EMDATA Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.5.4 SW4, 4 Position User Readable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.5.5 SW5, Power On Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.5.6 SW6, Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.5.7 SW7, Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Contains the schematics for the DM6437 Evaluation Module

B Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Contains the mechanical information about the DM6437 Evaluation Module

About This Manual

This document describes the board level operations of the DM6437 Evaluation Module
(EVM). The EVM is based on the Texas Instruments TMS320DM6437 Processor.

The DM6437 Evaluation Module is a table top card that allows engineers and software
developers to evaluate certain characteristics of the DM6437 processor to determine if
the processor meets the designers application requirements. Evaluators can create
software to execute on board or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.
The DM6437 Evaluation Module will sometimes be referred to as the DM6437 EVM or

EVM.
Program listings, program examples, and interactive displays are shown in a special

italic typeface. Here is a sample program listing.

equations
!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.

This is an example of a caution statement.

A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.

Related Documents, Application Notes and User Guides

Information regarding this device can be found at the following Texas Instruments
website:

http://www.ti.com

Table 1: Manual History

Revision History

A Alpha Release
B Beta Release

Table 2: Board History

Revision History

A Alpha Release
B Beta Release

Chapter 1

Introduction to the

DM6437 EVM

Chapter One provides a description of the DM6437 EVM along with the
key features and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-2

1.2 Fun ctional Overview 1-3

1.3 Basic Operation 1-4

1.4 Memory Map 1-5

1.5 Configuration Switch Settings 1-6

1.6 Power Supply 1-6

1.7 Power Measurement 1-6

1-1

Spectrum Digital, Inc

1.1 Key Features

The DM6437 EVM is a PCI based or standalone development platform that enables
users to evaluate and develop applications for the TI DaVinci

Schematics, list of materials, and application notes are available to ease hardware
development and reduce time to market.

Figure 1-1, DM6437 EVM

TM

processor family.

The EVM comes with a full complement of on board devices that suit a wide variety of
application environments. Key features include:

• A Texas Instruments DM6437 processor operating up to 600 Mhz.

• 1 TVP5146M2 video decoder, supports composite or S video

• 4 video DAC outputs - component, RGB, composite (3 populated)

• 128 Mbytes of DDR2 DRAM

• UART, CAN I/O Interfaces

• 16 Mbytes of non-volatile Flash memory, 64 Mbytes NAND Flash, 2 Mbytes SRAM

• AIC33 stereo codec

2

• I

C Interface with onboard eeprom and expanders

• 10/100 MBS Ethernet Interface

• Configurable boot load options

• Embedded JTAG emulation interface

• 4 user LEDs and 4 position user switch

1-2 DM6437 EVM Technical Reference

Spectrum Digital, Inc

• Single voltage power supply (+5V)

• Expansion connectors for daughter card use

• VLYNQ Interface

• S/PDIF Interface, analog, and optical

1.2 Functional Overview of the DM6437 EVM

DAC B

DAC C

DAC D

OUT

SVHS

IN

Video IN

DAC A

DAC

Out

AEAW2

EMIF

AEM2
AEM1
AEM0

Video

Decoder

ENET

Ext JTAG

I2C Bus

RJ45

ENET

PHY

Embedded

JTAG Emulator

USB

EMU

UARTs

MII

JTAG

DC_P2

McBSP0SVHS

SPI ROM

VLNQ

Mini PCI

McBSP1 or McASP0

1.8V Supply

1.2V Core Supply

3.3V I/O Supply

DIP

34

2

1

LEDs

NAND

SRAM

NOR

Flash

12
34

FASTB

1234567

BM0
BM1
BM2
BM3

RST

POR

Flash

DDR2

DDR2

32

DC_P1

DM6437

Video P ort

PCI

PCI Connector

RS-232

CAN

UART/CAN Switches

AIC33

Codec

PWR

MIC IN

LINE IN

LINE OUT

HP Out

S/PDIF

(optical)

S/PDIF

Figure 1-2, Block Diagram DM6437 EVM

The DM6437 on the EVM interfaces to on-board peripherals through integrated device
interfaces and a 8-bit wide EMIF bus. The DDR2 memory is connected to its own
dedicated 32 bit wide bus. The EMIF bus is jumper selectable to be connected to the
Flash, SRAM, NAND, and daughter card expansion connectors which are used for
add-on boards.

On board video decoder and on chip encoders interface video streams to the DM6437
processor. One TVP5146M2 decoder and 4 on chip DAC channels are standard on the
EVM (only 3 output connectors are populated so that the board can fit in a PCI slot).
On screen display functions are implemented in software on the DM6437 processor.

An on-board AIC33 codec allows the DSP to transmit and receive analog audio
signals. The I

2

C bus is used for the codec control interface, while the McBSP controls
the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond
to microphone input, line input, line output, and headphone outputs.

The EVM includes 4 user LEDs, and 4 position user DIP switch which can be used to
provide the user with interactive feedback. These interfaces are implemented via

2

I

C expanders.

1-3

Spectrum Digital, Inc

VLYNQ, and ethernet MAC interfaces are integrated peripherals on the DM6437
processor exploiting its system on a chip architecture. VLYNQ is available when the
PCI is not used.

An included 5V external power supply is used to power the board. On-board switching
voltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and
+1.8V DDR2 memory. The board is held in reset until these supplies are within
operating specifications.

Code Composer communicates with the EVM through an embedded emulator or via
the 14 pin external JTAG connector.

1.3 Basic Operation

The EVM is designed to work with TI’s Code Composer Studio development. Code
Composer communicates with the board through the embedded emulator or an
external JTAG emulator. To start, follow the instructions in the Quick Start Guide to
install Code Composer. This process will install all of the necessary development tools,
documentation and drivers.

Detailed information about the EVM including examples and reference material is
available on the EVM’s CD-ROM.

1-4 DM6437 EVM Technical Reference

Spectrum Digital, Inc

1.4 Memory Map

The DaVinci family of processors have a large byte addressable address space, some
limitations to byte addressing are determined by peripheral interconnection to the
DM6437 device. Program code and data can be placed anywhere in the unified
address space. Addresses are multiple sizes depending on hardware implementation.
Refer to the appropriate device data sheets for more details.

The memory map shows the address space of a DM6437 processor on the left with
specific details of how each region is used on the right. By default, the internal memory
sits at the beginning of the address space. Portions of memory can be remapped in
software as L2 cache rather than fixed RAM.

The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to
the DDR2 memory. The Flash, NAND Flash, or SRAM are mapped into CS2 space and
selectable via JP2. When CS2 is used for daughter card interfacing JP2 must be set
appropriately.

Address

0x10800000

0x42000000

0x44000000

0x46000000

0x48000000

0x4C000000

0x80000000

Figure 1-3, Memory Map, DM6437 EVM

DM6437 EVM

Cache/RAM

CS2

CS3

CS4

CS5

VLNQ

DDR

1-5

Spectrum Digital, Inc

1.5 Configuration Switch Settings

The EVM has a two configuration switches that allow users to control the operational
state of the processor when it is released from reset. The configuration switches are
labeled SW1 and SW2 on the EVM board.

Switch SW1 configures the boot mode that will be used when the DSP starts executing.
By default the switches are configured to EMIF boot (out of 8-bit Flash). The DM6437
EVM only supports little endian mode and is not configurable. Refer to section 3.5.1 for
the boot load options using switch SW1.

1.6 Power Supply

The EVM operates from a single +5V external power supply connected to the main
power input (J16), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted
into +1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The
+1.2V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O
buffers and other chips on the board. The +1.8 volt supply is used for DM6437
DDR2 interface, and DDR2 memory.

There are three power test points on the EVM; TP23, TP34, and TP38. These test
points provide a convenient mechanism to check the EVM’s multiple power supplies.
The table below shows the voltages for each test point and what the supply is used for.

Test Point Voltage Voltage Use

TP23 +1.2 V DM6437 Core
TP34 +3.3V DSP I/O and logic
TP38 +1.8 V DDR2 Memory, DSP I/O, and logic

1.7 Power Measurement

The EVM supports power test points to allow measurement of the various power rails
on the DM6437 device. Series resistors are used in the device’s power domains
thereby measuring the voltage across these resistors. The current can be calculated
via V = I * R.

Refer to the test point section in chapter 3 for detailed information on measuring current
on the DM6437 device.

Table 1: Power Test Points

1-6 DM6437 EVM Technical Reference

Chapter 2

Board Components

This chapter describes the operation of the major board components on
the DM6437 EVM.

Topic Page

2.1 EMIF Interfaces 2-2

2.1.1 DDR2 Memory Interface 2-2

2.1.2 Flash, NAND Flash, SRAM Memory Interface 2-2

2.2 Peripheral Interfaces 2-2

2.2.1 VLYNQ Interface 2-2

2.2.2 UART Interface 2-2

2.2.3 CAN Interface 2-3

2.3 Video Interfaces 2-3

2.3.1 Input Video Port Interfaces 2-3

2.3.2 On Chip Video Output DACs 2-3

2.4 AIC33 Interface 2-4

2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator 2-5

2.5 Ethernet Interface 2-6

2.6 I

2.6.1 I/O Expanders 2-7

2.6.2 I

2.7 S/PDIF Analog, and Optical Interfaces 2-9

2.8 Daughter Card Interface 2-10

2.9 DM6437 Core CPU Clock 2-10

2.10 DM6437 Core Voltage Select 2-10

2

C Interface 2-6

2

C EEPROM 2-9

2-1

Spectrum Digital, Inc

2.1 EMIF Interfaces

A separate 8 bit EMIF with multiple chip selects divide up the address space and allow
for asynchronous accesses on the EVM. On board the CS2 is used for Flash, NAND
Flash, or SRAM.

2.1.1 DDR2 Memory Interface

The DM6437 device incorporates a dedicated 32 bit wide DDR2 memory bus. The
EVM uses two 512 megabit 16 bit wide memories on this bus, for a total of 128
megabytes of memory for program, data, and video storage. The internal DDR
controller uses a PLL to control the DDR memory timing. The interface supports rates
up to 166 Mhz., and is clocked on differential edges for optimal performance. Memory
refresh for DDR2 is handled automatically by the DM6437 internal DDR controller.

2.1.2 Flash, NAND Flash, SRAM Memory Interface

The DM6437 has 16 megabytes of NOR Flash, or 64 megabytes of NAND Flash, or
2 megabyte of SRAM memory mapped into the CS2 space. This NOR Flash memory,
and NAND Flash memory are used primarily for boot loading. SRAM is used for
debugging application code. The CS2 space is configured as 8 bits wide on the
DM6437 EVM for NOR Flash, SRAM, or NAND flash usage.

2.2 Peripheral Interfaces

The DM6437 has several peripheral interfaces which allow the user to interface to
external devices. These interfaces are outlined in the following sections.

2.2.1 VLYNQ Interface

The DM6437 brings its internal VLYNQ interface out to a mini PCI connector J20 and
small 20 pin connector DC_P3. The VL YNQ interface is multiplexed on the PCI/EM bus
and this bus must be reconfigured after boot up to support VLYNQ. A multiplexer is
used to minimize board layout stubs and allow as direct as possible interface for the
VLYNQ signals. VLYNQ is not operational if the board is used in a PCI slot.

2.2.2 UART Interface

The internal UART0 on the DM6437 device is driven to connector P8. The UART’s
interface is routed to a Texas Instruments MAX3221 RS-232 line driver prior to being
brought out to a male DB-9 connector, P8. The on board UART signals can be disabled
by pulling the RS232_ENABLEn signal high via the daughter card connectors.

2-2 DM6437 EVM Technical Reference

Spectrum Digital, Inc

2.2.3 CAN Interface

The internal CAN controller on the DM6437 device is driven to connector P7. The
controller is routed to a Texas Instruments SN65HVD235 CAN controller prior to being
routed to female DB-9 connector, P7. The on board CAN signals can be disabled by
pulling CAN_ENABLEn high via the daughter card connector.

2.3 Video Interfaces

The DM6437 EVM has video input and output ports to support a variety of user
applications. These are discussed in the two sections below.

2.3.1 Input Video Port Interfaces

The DM6437 EVM supports video capture via the devices internal video ports. A Texas
Instruments TVP5146M2 is used to decode composite video or S-video inputs into the
device. P2 is used for the S-video inputs and J5 for the composite inputs on the EVM.

User inputs can be driven via daughter card connector DC_P1 when the on board CBTs
are disabled by driving control TVP5146_ENABLEn signal high on DC_P1.

2.3.2 On Chip Video Output DACs

The DM6437 incorporates 4 output DACs to interface to various output standards. The
DACs are buffered via opamps and driven to four RCA jacks, J1-J4. The outputs of the
DACs are programmable to support composite video, component video, or RGB.

S-video output is available from connector P1. This connector is driven by video DACs
B and C from the DM6437. Video DAC B is the chroma and video DAC C is the luma.

2-3

Spectrum Digital, Inc

M

2.4 AIC33 Interface

The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output of
audio signals. The codec samples analog signals on the microphone or line inputs and
converts them into digital data so it can be processed by the DSP. When the DSP is
finished with the data it uses the codec to convert the samples back into analog signals
on the line output so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. The I

is used as the unidirectional control channel. The control channel is generally only used
when configuring the codec, it is typically idle when audio data is being transmitted,

The default configuration is to use the McBSP is used as the bi-directional data
channel. However, optionally the McASP can be used to drive the data channel. Data

channel selection is controller via an on board I
through the data channel. Many data formats are supported based on the three
variables of sample width, clock signal source and serial data format. The EVM
examples generally use a 16-bit sample width with the codec in master mode so it
generates the frame sync and bit clocks at the correct sample rate without effort on the
DSP side.

2

C expander. All audio data flows

2

C bus

The codec has a programmable clock from a PLL1705 PLL device. The default system
clock is 18.432 Mhz. The internal sample rate generate subdivides the 18.432 MHz
clock to generate common frequencies such as 48KHz and 8KHz. The sample rate is
set by a codec register. The figure below shows the codec interface on the DM6437
EVM.

SCL
SDA

cASP or McBSP

AXR[0]
AXR[1]
ACLKR
ACLKX
AFSR
AFSX

DX
DR
CLKR
CLKX
FSR
FSX

I2C

Control

I2C Format

Digital

I2S Format

SCL

SDA

DOUT

DIN

BCLK

WCLK

AIC33 Codec

Control Regi s ters

ADC

DAC

Analog

MIC IN
LINE IN

LINE OUT
HP OUT

MIC IN

LINE IN

LINE OUT

HP OUT

Figure 2-2, DM6437 EVM CODEC INTERFACE

2-4 DM6437 EVM Technical Reference

Spectrum Digital, Inc

2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator

The DM6437 EVM implements a multiple PLL clock generator for creating the Audio
clocks for the board.

In streaming video applications the audio and video sequences can lose
synchronization. The DM6437 uses a VCXO interpolation circuit to incrementally speed
up or slow down the STCLK input to allow for this synchronization to remain locked.

The PWM1 and timer inputs on DM6437 are used to control this feature. The PWM0
pin drives a PICX100-27W Voltage Controlled Oscillator which is and fed back into the
timer input pin.

The STCLK is also a source clock for the PLL1705 programmable PLL device. This
device creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK.

The PLL1705 is programmable via an I
the I/O expander is required to interface correctly to the PLL1705’s programmable
inputs.

The diagram below is a simplified diagram of this clocking scheme.

DM6437

TIMER
IN

PWM1

VCXO
Circuit Using
PICX100-27

2

C and Expander U13. Software sequencing on

To I/O Expander

P

P

P

L

L
L
M
S

PLL1705

XT1

STCLK

L

M

C

L
L
M
D

SCK03

SCK02
SCK01
SCK00

MCK02
MCK01

AUDIO_CLK

VID_CLK

Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator

2-5

Spectrum Digital, Inc

2.5 Ethernet Interface

The DM6437 integrates an ethernet MAC on chip. This interface is routed to the PHY
via CBT switches. The EVM uses an Micrel KS8001L PHY. The 10/100 Mbit
interface is isolated and brought out to a RJ-45 standard ethernet connector, P3. The

PHY directly interfaces to the DM6437. The ethernet address is stored in the I
ROM during manufacturing.

The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellow
and indicate the status of the ethernet link. The green LED, when on, indicates link and
when blinking indicates link activity. The yellow LED, when illuminated, indicates full
duplex mode.

2

2.6 I

C Interface

2

C bus on the DM6437 is ideal for interfacing to the control registers of many

The I
devices. On the DM6437 EVM the I
stereo Codec, I/O expanders. An I

format of the bus is shown in the figure below.

2

C serial

2

C bus is used to configure the video decoder,

2

C ROM is also interfaced via the serial bus. The

Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop

Write Sequence

Start Slave Address R Data STOP

Read Sequence

Figure 2-4, I2C Bus Format

The addresses of the on board peripherals are shown in the table below.

2

Table 1: I

C Memory Map

Device Address R/W Device Function

TVP5146M2 0x5D R/W U50 Video Decoder

PCF 8574A 0x38 R/W U10 User Input
PCF 8574A 0x39 R/W U11 User LEDs
PCF 8574A 0x3A R/W U13 PLL, User I/O

PCF8574A 0x3B R/W U64 User I/O

TL V320AIC33 0x1B R/W U43 CODEC

24WC256 0x50 R/W U25

2

C EEPROM

I

2-6 DM6437 EVM Technical Reference

Spectrum Digital, Inc

2.6.1 I/O Expanders

2

The DM6437 EVM uses four I
of these is an 8 bit I/O expander, a PCF8574A. At Power Up Reset the expanders are
initialized to 0xFF, all ones. The functions for each of the I/O expanders are shown in
the tables below.

Table 2: U10 I/O Expander

Pin Number Function Decription

P0 JP1 NTSC/PAL Select Read only video mode,1=NTSC,0=PAL
P1 SW7 Slide Switch Read only slide switch
P2 Reserved None
P3 Reserved None
P4 SW4-1 Read only user switch
P5 SW4-2 Read only user switch
P6 SW4-3 Read only user switch
P7 SW4-4 Read only user switch

C expanders to handle various bit I/O functions. Each

Table 3: U11 I/O Expander

Pin Number Function Description

P0 User LED DS1 0=Turns LED on, 1=Turns LED off
P1 User LED DS2 0=Turns LED on, 1=Turns LED off
P2 User LED DS3 0=Turns LED on, 1=Turns LED off
P3 User LED DS4 0=Turns LED on, 1=Turns LED off
P4 VLYNQ Reset 0=Removes Reset, 1=Applies Reset
P5 Reserved None
P6 User I/O DC_P2 To daughter card, DC_P2 Pin 81
P7 User I/O DC_P2 To daughter card, DC_P2 Pin 82

2-7

Spectrum Digital, Inc

Pin Number Function Mode Description

P0 User I/O RW Daughter Card, DC_P2 Pin 87
P1 User I/O RW Daughter Card, DC_P2 Pin 88
P2 User I/O RW Daughter Card, DC_P2 Pin 85
P3 User I/O RW Daughter Card, DC_P2 Pin 84
P4 PLL -SR W Write PLL1705 SR Pin
P5 PLL - FS2 W Write PLL1705 FS2 Pin
P6 PLL - FS1 W Write PLL1705 FS1 Pin
P7 PLL-CSEL W Write PLL1705 CSEL Pin

Pin Number Function Description

P0 McBSP_Enable to AIC23 * 1=Enable, 0=Disable
P1 McASP_Enable to AIC23 * 0=Enable, 1=Disable
P2 SPDIF Enable * 0=Enable, 1=Disable
P3 Reserved None
P4 Reserved None
P5 Reserved None
P6 Reserved None
P7 Core Voltage Select 0 = 1.05 Volt, 1 = 1.2 Volt

Table 4: U13 I/O Expander

Table 5: U64 I/O Expander

* only one should be enabled at a time

2-8 DM6437 EVM Technical Reference

Spectrum Digital, Inc

2.6.2 I2C EEPROM

2

The DM7436 EVM incorporates an I
general purpose storage.

This eeprom is also used to store the ethernet MAC address and the board’s revision.
The MAC address is also labeled on the board. Care should be taken not to erase
these items when user information is stored in the eeprom. Spectrum Digital uses
addresses 0x7F00 to 0x7FFF for manufacturing information. This information is
shown in the table below.

Table 6: DM6437 MAC Addresses

Address Contents

0x7F00 EMAC Address 0

0x7F01 EMAC Address 1
0x7F02 EMAC Address 2
0x7F03 EMAC Address 3
0x7F04 EMAC Address 4
0x7F05 EMAC Address 5
0x7F06 Reserved
0x7F07 Board Revision

C eeprom that can be used for booting or

(most significant)

2.7 S/PDIF Analog, and Optical Interfaces

The McBSP’s FSR pin on the DM6437 can be configured to operate as a S/PDIF
transmitter. The DM6437 EVM supports both analog and optical interfaces. The
analog S/PDIF output pin is routed to a driver and filter circuit before being output on

2

J10. I

C Expander U64 output P2 is used to enable the S/PDIF interface. When
S/PDIF is selected on the expamder (P2=0), the McASP enable should be disabled and
the McBSP enable should be disabled.Another driver is used to interface the optical
transmitter P14. When the S/PDIF interface is enabled the TLV320AIC33 codec is
disabled, the WCLK should be disabled prior to enabling the S/PDIF output.

The McBSP interface can be disabled for daughter card use by pulling the
AIC_ENABLEn signal high from the daughter card connector.

2-9

Spectrum Digital, Inc

2.8 Daughter Card Interfaces

The EVM provides expansion connectors that can be used to accept plug-in daughter
cards. The daughter card allows users to build on their EVM platform to extend its
capabilities and provide customer and application specific I/O. The expansion
connectors are for all major interfaces including memory, peripherals, and video
expansion.

The pin outs for this interface are documented in Section 3.
The connectors provide access to the DSP’s EMIF signals to interface with memories

and memory mapped devices. The video capture port is brought out to the daughter
card interface.

Several signals are used to disable the on board video peripherals so that they can be
used by the expansion connector. The table below indicates the operation of these
signals.

Table 7: Daughter Card Interface

Signal Function

AIC33_ENABLEn Disconnects CPU from on board codec

CI_EMA_ENABLEn Disables CI0 to CI7 from upper on board EMIF address lines

MEM_EMD7-0_ENABLEn Disables CPU from on board data bus

VIC_TINPOL_ENABLEn Disable CPU TINPOL pin from on board use

ENET_ENABLEn Disconnects CPU from on board ethernet PHY

CAN_ENABLEn Disconnects CPU from on board CAN

RS232_ENABLEn Disconnects CPU from on board UART

TVP5146_ENABLEn Disconnects CPU from on board video decoder

Other than the buffering, most daughter card signals are not modified on the board.

2.9 DM6437 Core CPU Clock

The DM6437 EVM uses a 27 Megahertz crystal to generate the input clock. The
DM6437 has an internal PLL which can multiply the input clock to generate the internal
clock. The PLL multiplier is set via software on the DM6437 device.

2.10 DM6437 Core Voltage Select

The DM6437 EVM has the ability to adjust the core voltage between 1.2 volts and

1.05 volts. an I/O expander is used to control this I

2-10 DM6437 EVM Technical Reference

2

C feature.

Chapter 3

Physical Description

This chapter describes the physical layout of the DM6437 EVM and its
interfaces.

Topic Page

3.1 Board Layout 3-3

3.2 Connectors 3- 4

3.2.1 J1, DAC A Video Out 3-5

3.2.2 J2, DAC B Video Out 3-5

3.2.3 J3, DAC C Video Out 3-5

3.2.4 J4, DAC D Video Out 3-6

3.2.5 J5, Video In 3-6

3.2.6 J10, S/PDIF Out 3-7

3.2.7 J16, +5V Input 3-7

3.2.8 J20, Mini PCI Interface 3-8

3.2.9 J501, Embedded Mini USB Emulation Interface 3-9

3.2.10 P1, Video Out 3-9

3.2.11 P2, Video In 3-10

3.2.12 P3, Ethernet Interface 3-10

3.2.13 P4, PCI Connector 3-11

3.2.14 P7, CAN Connector 3-13

3.2.15 P8, RS-232 UART 3-15

3.2.16 P10, Stereo Line In 3-15

3.2.17 P11, Microphone In 3-15

3.2.18 P12, Headphone Out 3-15

3.2.19 P13, Stereo Line Out 3-16

3.2.20 P14, S/PDIF Out (Optical) 3-16

3.2.21 DC_P1, Memory/Video Expansion 3-17

3.2.22 DC_P2, Peripheral Expansion 3-18

3.2.23 DC_P3, VLYNQ Connector 3-19

3-1

Spectrum Digital, Inc

Topic Page

3.3 Jumpers 3-19

3.3.1 JP1 Jumper 3-20

3.3.2 JP2 Jumper 3-20

3.3.3 JP3 Jumper 3-21

3.3.4 JP4 Jumper 3-21

3.4 LEDs 3-21

3.5 Switches 3-22

3.5.1 SW1, Bootload Mode Selections 3-22

3.5.2 SW2, Bootload Configuration Select 3-23

3.5.3 SW3, EMIF Data Select 3-23

3.5.4 SW4, 4 Position User Readable 3-23

3.5.5 SW5, Power On Reset Switch 3-23

3.5.6 SW6, Reset Switch 3-23

3.5.7 SW7, Slide Switch 3-24

3.6 T est Points 3-25

3-2 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.1 Board Layout

The DM6437 EVM is a 8.75 x 4.5 inch (210 x 115 mm.) ten (10) layer printed circuit
board which is powered by an external +5 volt only power supply. Figure 3-1 shows the
layout of the DM6437 EVM.

P10
P11

P13

P8

P7

DS501

J501

J6

P3

SW3

SW7

JP4
SW5
SW6

JP3

J5

J10
P14
P12

J16

DS5

DC_P3

J20

DC_P2

DC_P1

JP2

JP1

SW4

DS1-DS4

J1

P1

J2

Figure 3-1, DM6437 EVM, Interfaces Top Side

3-3

J3

J4

P2

P4

SW1

SW2

J5

Spectrum Digital, Inc

3.2 Connectors

The EVM has twenty three (23) connectors providing interfaces to various peripherals.
These connectors are described in the following sections.

Connector Size Function

Table 1: Connectors

J1 RCA DAC A *
J2 RCA DAC B
J3 RCA DAC C
J4 RCA DAC D
J5 RCA Video In
J6 14 External

Emulation Header
J10 RCA S/PDIF Out
J16 2.5 mm +5V In
J20 2 x 62 Mini PCI Interface

J501 Mini USB Embedded USB

Emulation Interface
P1 4 Pin DIN S-Video Out
P2 4 Pin DIN S-Video In
P3 RJ-45 Ethernet
P4 PCI PCI
P7 9 Pin D-sub CAN
P8 9 Pin D- su b RS-232 UART

P10 3.5 mm Stereo Line In
P11 3.5 mm Microphone In
P12 3.5 mm Headphone Out
P13 3.5 mm Stereo Line Out

P14 Optical S/PDIF Out
DC_P1 2x50 Expansion
DC_P2 2x45 Expansion
DC_P3 2x10 Expansion

* Not populated

3-4 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.1 J1, DAC A Video Out

J1 is an RCA jack used to interface to DAC A of the DM6437 to a video device. This
connector is driven directly by the VPSS back end via an opamp. This connector is not
installed for clearance reasons when using the PCI bus. The pinout of this connector is
shown below.

Shield (ground)

Signal Output

Figure 3-2, J1, RCA Jack

3.2.2 J2, DAC B Video Out

J2 is an RCA jack used to interface to DAC B of the DM6437 to a video device. This
connector is driven directly by the VPSS back end via an opamp. This connector is not
installed for clearance reasons when using the PCI bus. The pinout of this connector is
shown below.

3.2.3 J3, DAC C Video Out

J3 is an RCA jack used to interface to DAC C of the DM6437 to a video device. This
connector is driven directly by the VPSS back end via an opamp. This connector is not
installed for clearance reasons when using the PCI bus. The pinout of this connector is
shown below.

Shield (ground)

Signal Output

Figure 3-3, J2, RCA Jack

Shield (ground)

Signal Output

Figure 3-4, J3, RCA Jack

3-5

Spectrum Digital, Inc

3.2.4 J4, DAC D Video Out

J1 is an RCA jack used to interface to DAC D of the DM6437 to a video device. This
connector is driven directly by the VPSS back end via an opamp. This connector is not
installed for clearance reasons when using the PCI bus. The pinout of this connector is
shown below.

3.2.5 J5, Video In

J5 is an RCA jack used as a video input to the TVP5146M2 video decoder. This
connector brings in a video signal to the TVP5146M2. Do NOT plug into this
connector with the power on. The figure below shows this connector as viewed from the
card edge.

Shield (ground)

Signal Output

Figure 3-5, J4, RCA Jack

Pin 2, Shield (ground)

Pin 1, Signal Input

Figure 3-6, J5, Video In RCA Jack

Table 2: J5, Video In, RCA Jack

Pin # Signal Name

1 Pin 8, TVP5146M2
2GND

3-6 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.6 J10, S/PDIF Out

J10 is an RCA jack used as an analog output from the McBSP FSR signal on the DSP.
This connector brings out the SPDIF signal. Do NOT plug into this connector with the
power on. The figure below shows this connector as viewed from the card edge.

Pin 2, Shield (ground)

Pin 1, Signal Output

Figure 3-7, J10, S/PDIF Out, RCA Jack

Table 3: J10, S/PDIF, RCA Jack

Pin # Signal Name

1 S/PDIF Analog output
2GND

3.2.7 J16, +5V Input

Connector J16 is the input power connector. This connector bring in +5 volts to the
EVM. This is a 2.5 mm. jack. The figure below shows this connector as viewed from
the card edge.

+5V

J14

Front View

Figure 3-8, J16, +5 Volt Input Connector

Ground

PC Board

3-7

Spectrum Digital, Inc

3.2.8 J20, Mini PCI Interface

Connector J20 provides a mini-PCI on the DM6437 EVM. Do NOT plug into this
connector with the power on. The table below shows the signals on this connector.

2,3,4,5,6,7,8,10,11,

12,13,15,17,18,29,
30,38,39,47,49,51,
53,55,57,71,73,75,
77,80,82,84,86,93,

32,33,34,35,37,41,
42,44,45,46,48,50,
52,54,56,58,60,62,
64,66,68,69,72,74,
76,78,79,81,83,85,
87,90,91,92,94,95,

Table 4: J16, VLYNQ Card Interface

Pin # Signal

NC

98,100,104,105,

106,107,108,109,

113,115,116,117,

118,120,122,123,

124

9,14,20,23,25,27

GND

96,99,101,102,

110,114,119

111 VCC_1.8V

1,19,28,31,40,63,

70,88,89

97,103 VCC_5V

16 VLYNQ_CLK
21 VLYNQ_RXD0
22 VLYNQ_RXD1
24 VLYNQ_SCRUN
26 VLYNQ_RESET
59 VLYNQ_RXD2
61 VLYNQ_RXD3
36 VLYNQ_TXD0
65 VLYNQ_TXD2
67 VLYNQ_TXD3
43 VLYNQ_TXD1

VCC_3.3V

3-8 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.9 J501, Embedded Mini USB Emulation Interface

This connector allows the user to run software development tools and emulation
without an external emulator. The signals on this connector are shown in the table
below.

Table 5: J501, Embedded Mini USB Emulation Interface

Pin # Signal Name

1 VBUS
2D­3D+
4 ID (not used)
5 Ground

3.2.10 P1, Video Out

Connector P1 is a four pin mini din connector which interfaces to an S-video output
display device. This connector brings out the DAC B and DAC C. Do NOT plug into this
connector with the power on. The figure below shows this connector as viewed from the
card edge.

Pin 3
Pin 1

Figure 3-9, P1, Front View, Mini Din Connector

Table 6: P1, Video Out, Mini Din Connector

Pin # Signal Name

1 Ground
2 Ground
3DAC_IOUTB, Luma
4DAC_IOUTC, Chroma

3-9

Pin 4
Pin 2

Spectrum Digital, Inc

3.2.11 P2, Video In

Connector P2 is a four pin mini din S-video connector which interfaces to the
TVP5146M2 encoder. This connector brings in a video signal (LUMA) to pin 9 on the
TVP5146M2. Do NOT plug into this connector with the power on. The figure below
shows this connector as viewed from the card edge.

Figure 3-10, P2,Front View, Mini Din Connector

Table 7: J11, Video In, Mini Din Connector

3.2.12 P3, Ethernet Interface

The P3 connector is used to provide an 10/100 Mbps Ethernet interface. This is a
standard RJ-45 connector. The pinout for the P3 connector is shown in the table below.

Pin 3
Pin 1

Pin 4
Pin 2

Pin # Signal Name

1GND
2GND
3LUMA
4 Chroma

Table 8: P3, Ethernet Interface

Pin # Signal Pin # Signal

1 LXT_TDP 2 LXT_TDM
3 LXT_RDP 4 LXT_TDCT
5NC6LXT_RDM
7NC8 GND

Two LEDs are embedded into the connector to report link status.

T able 9: Ethernet LEDs

LED # Color

LED1 Green
LED2 Yellow

3-10 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.13 P4, PCI Connector

The P4 connector is a card edge PCI interface. This connector has an “A” and “B” side.
Because of the card seating notches the pin numbers are not contiguous. The “B” side
is the top component side. The I/O direction field is referenced from the PCI slot.

Table 10: P4, PCI Connector, “A” Side

Pin Signal I/O Description Pin Signal I/O Description

1 TRST- Not Used 2 +12 Volts Not Used
3 TMS Not Used 4 TDI I/O Tied to TDO
5 +5 Volts +5 Volts Power 6 INTA- O Interrupt Out
7 INTC- O Interrupt Out 8 +5 Volts +5 Volts Power

9 Rsvd.0 Not Used 10 +V I/O Not Used
11 Rsvd.1 Not Used 12 Key.1 Key
13 Key.2 Key 14 +3.3 Vaux Not Used
15 RST- I PCI_Resetn 16 +V I/O O Not Used
17 GNT- O Grant- 18 GND Ground
19 PME- 20 AD30 I/O/Z Address/Data 30
21 +3.3 Volts Not Used 22 AD28 I/ O/Z Address/Data 28
23 AD26 I/O/Z Address/Data 26 24 GND
25 AD24 I/O/Z Address/Data 24 26 IDSEL I Initialization Device Select
27 +3.3 Volts Not Used 28 AD22 I/ O/Z Address/Data 22
29 AD20 I/O/Z Address/Data 20 30 GND Ground
31 AD18 I/O/Z Address/Data 18 32 AD16 I/ O/Z Address/Data 16
33 +3.3 Volts Not Used 34 FRAME- I Frame
35 GND Ground 36 TRDY- I/O/Z Target Ready
37 GND Groun d 38 STOP- I/O/Z Stop Direction
39 +3.3 Volts Not Used 40 SDONE O Done
41 SBO- 42 GND Ground
43 PAR I/O/Z Parity 44 AD15 I/O/Z Address/Data 15
45 +3.3 Volts Not Used 46 AD13 I/ O/Z Address/Data 13
47 AD11 I/O/Z Address/Data 11 48 GND Ground
49 AD9 I/O/Z Address/Data 9 50 Key.3 Key
51 Key.4 Key 52 C/BE0 Command/Byte Enable0
53 +3.3 Volts Not Used 54 AD6 I/O/Z Address/Data 6
55 AD4 I/O/Z Address/Data 4 56 GND Ground
57 AD2 I/O/Z Address/Data 2 58 AD0 I/O/Z Address/Data 0
59 +V I/O Not Used 60 REQ64- Not Used
61 +5 Volts +5 Volts Power 62 +5 Vo lts +5 Volts Power

3-11

Spectrum Digital, Inc

The signals on the “B” side of the connector are shown in the table below.

Table 11: P4, PCI Connector, “B” Side

Pin Signal I/O Description Pin Signal I/O Description

1 -12 Vo lts Not Used 2 TCK I Not Used
3 GND Ground 4 TDO I Tied to TDO
5 +5 Volts +5 Volt Power 6 +5 Volts I +5 Volt Power
7 INTB- Interrupt OUT 8 INTD- Interrupt Out

9 PRSNT1- O Power Requirement 10 Rsvd.2
11 PRSNT2- O Power Requirement 12 Key.5 Key
13 Key.6 Key 14 Rsvd.3
15 GND Ground 16 CLK System Cl ock
17 GND Ground 18 REQ­19 +V I/O Not Used 20 AD31 I/O/Z Address/Data 31
21 AD29 I/O/Z A d dre ss/Da ta 29 22 GND Ground
23 AD27 I/O/Z A d dre ss/Da ta 27 24 AD25 I/O/Z Ad dre ss/D a ta 25
25 +3.3 Volts Not Used 26 C/BE3 I/O/Z Command/Byte Enable 3
27 AD23 I/O/Z A d dre ss/Da ta 23 28 GND Ground
29 AD21 I/O/Z A d dre ss/Da ta 21 30 AD19 I/O/Z Ad dre ss/D a ta 19
31 +3.3 Volts Not Used 32 AD17 I/O/Z Address/Data 17
33 C/BE2- I/O/Z Co mm and /Byte En ab le 2 34 GN D Ground
35 IRDY- I Initiator Ready 36 +3.3 Volts Not Used
37 DEVSEL- I/O/Z Device Select 38 GND Ground
39 LOCK- I Re sou rce Loc ked 40 PERR- I/ O/Z Parity Error
41 +3.3 Volts Not Used 42 SERR- O System Error
43 +3.3 Volts Not Used 44 C/BE1- I/O/Z Comman d/Byte Enable 1
45 AD14 I/O/Z A d dre ss/Da ta 14 46 GND Ground
47 AD12 I/O/Z A d dre ss/Da ta 12 48 AD10 I/O/Z Ad dre ss/D a ta 10
49 M66EN O 66 Mhz Enable 50 Key.7 Key
51 Key.8 Key 52 AD8 I/O/Z Address/Data 8
53 AD7 I/O/Z Address/Data 7 54 +3.3 Volts Not Used
55 AD5 I/O/Z Address/Data 5 56 AD3 I/O/Z Address/Data 3
57 GND Ground 58 AD1 I/O/Z Address/Data 1
59 +V I/O Not Used 60 ACK64- Not Used
61 +5 Volts +5 Volt Power 62 +5 Volts +5 Volt Power

3-12 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.14 P7, CAN Connector

The DM6437 EVM has a 9 Pin female D-connector which brings out the CAN transmit
and receive signals. This CAN interface uses the SN65HVD235 CAN driver. The pin
positions for the P7 connector as viewed from the edge of the printed circuit board are
shown below.

1

34

5

9

Figure 3-11, P7, DB9 Female Connector

The pin numbers and their corresponding signals are shown in the table below.

Table 12: P7, CANA Pinout

Pin # Signal Name

1 No Connect
2CANL
3GND
4 No Connect
5 No Connect
6 No Connect
7CANH
8 No Connect
9 No Connect

2

8

6

7

3-13

Spectrum Digital, Inc

3.2.15 P8, RS-232 UART Connector

The DM6437 EVM has an RS-232 connector which brings out the SCI transmit and
receive signals to be used as UART. This UART uses the MAX3221 RS-232 line driver
and is routed to a male 9 pin D-connector, P8. The pin positions for the P8 connector
as viewed from the edge of the printed circuit board are shown below.

Figure 3-12, P8, DB9 Male Connector

The pin numbers and their corresponding signals are shown in the table below. This
corresponds to a standard dual row to DB-9 connector interface used on personal
computers.

Table 13: P8, RS-232 UART Pinout

34

5

8

9

Pin # Signal Name

1 No Connect
2RXD
3TXD
4 No Connect
5GND
6 No Connect
7 No Connect
8 No Connect
9 No Connect

12

6

7

3-14 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.16 P10, Audio Line In Connector

The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.

Ground
Right Line In

Left Line In

Figure 3-13, Audio Line In Stereo Jack

3.2.17 P11, Microphone Connector

The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is
monaural. The signals on the plug are shown in the figure below.

Figure 3-14, Microphone Stereo Jack

3.2.18 P12, Headphone Connector

Connector P12 is a headphone/speaker jack. It can drive standard headphones or a
high impedance speaker directly. The standard 3.5 mm jack is shown in the figure
below.

Ground

Microphone In
Microphone Bias

Ground
Right Headphone

Left Headphone

Figure 3-15, Headphone Jack

3-15

Spectrum Digital, Inc

3.2.19 P12, Audio Line Out Connector

The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.

Figure 3-16, Audio Line Out Stereo Jack

3.2.20 P14, S/PDIF Out (Optical)

P14 is an optical transmitter connector used as an output from the McBSP FSR signal
on the DM6437 DSP. This connector brings out an optical S/PDIF signal. Do NOT plug
into this connector with the power on. The figure below shows this connector as viewed
from the card edge.

Ground
Right Line Out

Left Line Out

3-16 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.21 DC_P1, Memory/Video Expansion­Table 14: DC_P1, Memory/Video Expansion

Pin Signal Conn Pin Signal Conn

1 GROUND 2 GROUND
3 PCLK_GP[54] 4 Y1_EMD_ENABLEn
5 TVP5146_ENABLEn 6 GROUND
7 YI3_(CCD3)_GP39] 8 YI4_(CCD4)_GP40]

9 YI2_(CCD2)_GP[38] 10 YI5_(CCD5)_GP[41]
11 TI1_(CCD1)_GP[37] 12 TI6_(CCD6_GP[42]
13 YI0_(CCD0_GP[36] 14 YI7_(CCD7)_GP[43]
15 GROUND 16 GROUND
17 C_WE_RNW_GP[35] 18 C_FIELD_EM_A[21]_GP[34]
19 VD_GP[53] 20 HD_GP[52]
21 CI3_(CDD11)_EM_A[17]_EM_D[04]_GP[47] 22 CI4_(CDD12)_EM_A[16]_EM_D[03]_GP[48]
23 CI2_(CDD10)_EM_A[18]_EM_D[05]_GP[46] 24 CI5_(CDD13)_EM_A[15]_EM_D[02]_GP[49]
25 CI1_(CDD9)_EM_A[19]_EM_D[06]_GP[45] 26 CI6_(CDD14)_EM_A[14]_EM_D[01]_GP[50]
27 CI0_(CDD8)_EM_A[20]_EM_D[07]_GP[44] 28 CI7_(CDD15)_EM_A[13]_EM_D[00]_GP[51]
29 GROUND 30 GROUND
31 VCLK_GP[31] 32 VSYNC_EM_CS4n_GP[32]
33 GROUND 34 GROUND
35 VPBECLK_GP[30] 36 HSYNC_EM_CS5n_GP[33]
37 GROUND 38 GROUND
39 YOUT3_GP[25]_BOOTMODE3 40 YOUT4_GP[26]_FASTBOOT
41 YOUT2_GP[24]_BOOTMODE2 42 YOUT5_GP[27]
43 YOUT1_GP[23]_BOOTMODE1 44 YOUT6_GP[28]
45 YOUT0_GP[22]_BOOTMODE0 46 YOUT7_GP[29]
47 GROUND 48 GROUND
49 COUT3_EM_D[3]_GP[17] 50 COUT4_EM_D[4]_GP[18]
51 COUT2_EM_D[2]_GP[16] 52 COUT5_EM_D[5]_GP[19]
53 COUT1_EM_D[1]_GP[15] 54 COUT6_EM_D[6]_GP[20]
55 COUT0_EM_D[0]_GP[14] 56 COUT7_EM_D[7]_GP[21]
57 GROUND 58 GROUND
59 B0_LCD_FIELD_EM_A[3]_GP[11] 60 R0_EM_A[4]_GP[10]_(AEAW2)
61 G1_EM_A[1]_(ALE)_GP[9]_(AEAW1) 62 B1_EMA[2]_(CLE)_GP[8]_(AEAW0)
63 R2_EM_BA[0]_GP[6]_(AEM1) 64 R1_EM_A[0]_GP[7]_(AEM2)
65 B2_EM_BA[1]_GP[6]_(AEM0) 66 G0_EM_CS2n__GP[12]
67 EM_WAIT_(RDY/BSTn) 68 LCD_OE_EM_CS3n_GP[13]
69 GROUND 70 GROUND
71 EM_A[5]_GP[96] 72 EM_A[9]_GP[92]
73 EM_A[6]_GP[95] 74 EM_A[10]_GP[91]
75 EM_A[7]_GP[94] 76 EM_A[11]_GP[90]
77 EM_A[8]_GP[93] 78 EM_A[12]_GP[89]
79 EM_WEn 80 EM_OEn
81 GROUND 82 GROUND
83 MEM_EMD7-7_ENABLEn 84 CLK_OUT_PWM2_GP[84]
85 CI_EMA_ENABLEn 86 GROUND
87 RESETn 88 GP[4]_PWM1
89 SYS_RESETn 90 I2C_INT_ENABLEn
91 VCC_1V8 92 VCC_1V8
93 GROUND 94 GROUND
95 VCC_3V3 96 VCC_3V3
97 GROUND 98 GROUND
99 VCC_5V 100 VCC_5V

3-17

Spectrum Digital, Inc

3.2.22 DC_P2, Peripheral Expansion
Table 15: DC_P2, Peripheral Expansion

Pin Signal Conn Pin Signal Conn

1 GROUND 2 GROUND
3 VCC_5V 4 VCC_5V
5 VCC_3V3 6 VCC_3V3
7 VIC_TINPOL_ENABLEn 8 GROUND

9 CLKS1_TINPOL_GP[98] 10 CLKS0_TINPOL_GP[97]
11 GP[00] 12 GP[01]
13 GP[02] 14 GP[03]
15 RS232_ENABLEn 16 GROUND
17 URXD0_GP[85] 18 URTS0_PWM0_GP[88]
19 UTXD0_GP[86] 20 UCTS0_GP[87]
21 GROUND 22 GROUND
23 HECC_RX_TINP1L_URXD1_GP[56] 24 HECC_tX_TOUT1L_UTXD1_GP[55]
25 GROUND 26 CAN_ENABLEn
27 AUDIO_CLK 28 GROUND
29 AXR0[3]_FSR0_GP[102] 30 AXR0[2]_FSX0_GP[103]
31 AFSR0_DR0_GP[100] 32 AXR0[1]_DX0_GP[104]
33 AHCLKR0_CLKR0_GP[101] 34 ACLKR0_CLKX0_GP[99]
35 GROUND 36 GROUND
37 I2C_CLK 38 I2C_DATA
39 AIC33_ENABLEn 40 GROUND
41 AXR0_FSR1_GP[106] 42 AMUTEIN0_FSX1_GP[109]
43 AMUTE0_DR1_GP[110] 44 ACHLKX0_CLKR1_GP[108]
45 A CLKX0_CLKX1_GP[106] 46 AFSX0_DX1_GP[107]
47 GROUND 48 GROUND
49 RESET_OUTn 50 SPARE
51 SPARE 52 HCNTL0_MRXER_GP[76]
53 HDS1n_RXD1_GP[79] 54 HDS2n_RXD0_GP[78]
55 HINTn_RXD3_GP[82] 56 HRDYn_RXD2_GP[80]
57 GROUND 58 HD09_COL_GP[67]
59 HHWIL_RXDV_GP[74] 60 GROUND
61 HD10_CRS_GP[68] 62 HRNW_RXCLK_GP[77]
63 GROUND 64 GROUND
65 HCSnMDC_GP[81] 66 HASn_MDIO_GP[83]
67 GROUND 68 GROUND
69 HD11_TXD3_GP[69] 70 HD12_TXD2_GP[70]
71 HD13_TXD1_GP[71] 72 HD14_TXD0_GP[72]
73 HCNTL1_TXEN_GP[75] 74 ENET_ENABLEn
75 GROUND 76 GROUND
77 SPARE 78 HD15_TXCLK_GP[73]
79 GROUND 80 GROUND
81 USER_I2C_IO.A0P6 82 USER_I2C_IO.A0P7
83 SPARE 84 SPARE
85 USER_I2C_IO.A1P2 86 USER_I2C_IO.A1P3
87 USER_I2C_IO.A1P0 88 USER_I2C_IO.A1P1
89 GROUND 90 GROUND

3-18 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.2.23 DC_P3, VLYNQ Connector

The DC_P3 connector allows the user to connect the VLYNQ interface to other logic.
The pinout for the DC_P3 connector is shown in the table below.

T able 16: DC_P3, VLYNQ Header

Pin # Signal Conn Pin # Signal Conn

1 HD00_VLYNQ_SCRUN_GP[58] 2 VLYNQ_CLOCK_GP[57]
3 GROUND 4 GROUND
5 HD01_VLYNQ_RXD0_GP[59] 6 HD05_VLYNQ_TXD0_GP[63]
7 HD02_VLYNQ_RXD1_GP[60] 8 HD06_VLYNQ_TXD1_GP[64]

9 GROUND 10 GROUND
11 VCC_3V3 12 DC_P3_VLYNQ_RESETn
13 HD03_VLYNQ_RXD2_GP[61] 14 HD07_VLYNQ_TXD2_GP[65]
15 HD04_VLYNQ_RXD3_GP[62] 16 HD08_VLYNQ_TXD3_GP[66]
17 GROUND 18 GROUND
19 VCC_5V 20 VCC_5V

3.3 Jumpers

The DM6437 EVM has four (4) jumpers which are used to make certain logic or feature
determinations on the board. The function of each jumper is described in the table
below.

Table 17: Jumpers

Jumper # Function Size

JP1 NTSC/PAL Select 1x3

JP2 CS2 Select 2x4
JP3 * Reset 1x2
JP4 * Power Up Reset 1x2

* Not populated

3-19

Spectrum Digital, Inc

3.3.1 JP1 Jumper

Jumper JP1 is used to select the display output format, NTSC or PAL. This jumper
must be populated in one of the two configurations. When the center to NTSC is
selected the display output will be NTSC format. When the center to PAL is selected
the displa y ou t p ut wi ll b e in P AL f or mat . Th es e po si t io n s a re s ho wn in t h e fi g ur e be lo w .

Board
edge

PAL Selection

Board
edge

NTSC Selection

Figure 3-18, JP1 Jumper

3.3.2 JP2 Jumper

Jumper JP2 is a jumper bank used to select the routing of the CS2 signal. It can be
routed to Flash ROM, SRAM, NAND Flash, and daughter card connector. Only one of
these 1-2 selections should be made. The positions are shown in the figure below.

1

2

FLASH
SRAM

CS2-SEL

JP2

Figure 3-19, JP2 Jumper

NAND
DC

3-20 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.3.3 JP3 Jumper

Jumper JP3 is a jumper used to allow external switches to interface to the DM6437
power up reset signal.

3.3.4 JP4 Jumper

Jumper JP4 is a jumper used to allow external switches to interface to the DM6437
reset signal.

3.4 LEDs

The DM6437 EVM has eight (8) LEDs. Four of these LEDs (DS1-4) are under user

2

control and addressed over the I
the board. The remaining LEDs, DS501 and DS502 indicate embedded USB status.
DS502 is on when embedded USB emulation is selected and off when the external
JTAG emulator is plugged into connector J6. DS501 blinks as packets are sent to and
from the embedded USB emulator. The LED functions are summarized in the table
below.

C bus. LED DS5 indicates the presence of +5 volts on

Table 18: LEDs

LED # Use Color

DS1 User Defined Green
DS2 User Defined Green
DS3 User Defined Green
DS4 User Defined Green

DS5 +5V present Red
DS501 Embedded Emulation Status Green
DS502 Embedded/external EMU Green

3-21

Spectrum Digital, Inc

3.5 Switches

The DM6437 EVM has seven (7) switches. These switches are used to create certain
actions on the board or to select certain functions on the board. The switch functions
are summarized in the table below.

SW # Function

SW1 Bootload Mode Select
SW2 DM6437 Muxing Configuration
SW3 EMIF Data Select
SW4 4 position user readable
SW5 Power On Reset
SW6 Reset
SW7 Slide Switch

3.5.1 SW1, Bootload Mode Select

T able 19: Switches

Switch SW1 is an 8 position switch used to select the source of the bootload. Five (5) of
the eight (8) positions are used. The selections are shown in the table below.

Table 20: SW1, Bootload Mode Select

SW1[4:1] SW1[5]

0000 x x

0001 1* 0 HPI Boot DM6437 is slave 0x0010 0000
0001 1* 1 PCI Boot without auto-

0010 1* 0 PCI Boot with auto-

0010 1* 1 HPI Boot DM6437 is slave 0x0010 0000
0100 0 x EMIFA ROM Direct Boot DM6437 is master 0x4200 0000
0100 1 x EMIFA ROM Fast Boot DM6437 is master 0x0010 0000
0101 x x I2C Boot DM6437 is master 0x0010 0000
0110 1* x SPI Boot

0111 1* x NAND Flash DM6437 is master 0x0010 0000
1000 x x UART DM6437 is master 0x0010 0000
1011 x x EMAC Boot through

Auto

Detected

In this mode, FASTBOOT

used by bootloader code)

Boot

Description

Emulation Boot

setting is don’t care (not

initialization

initialization

(McBSP periphera l)

secondary bootloader

Notes

DM6437 is master 0x0010 0000

DM6437 is slave 0x0010 0000

DM6437 is slave 0x0010 0000

DM6437 is master 0x0010 0000

DM6437 is slave 0x0010 0000

DSPBOOTADDR

default

x = don’t care, * these boot modes must be accompanied with FASTBOOT = 1.

3-22 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.5.2 SW2, Bootload Configuration Select

Switch SW2 is an 4 position switch used to select the DM6437 multiplexing options
at reset. The selection are shown in the table below.

Table 21: SW2, Bootload Configuration Select

Position Function Description

1 AEM2 Specifies EMIF mode at reset
2 AEM1 Specifies EMIF mode at reset
3 AEM0 Specifies EMIF mode at reset
4 AEAW2 Specifies EMIF mode at reset

3.5.3 SW3, EMIF Data Select

Switch SW3 is used to select between data bus pins for the asynchronous EMIF
controller. The functions of this switch are shown in the table below.

Table 22: SW3, EMDATA Select

Position Function Description

1 Not used Not Used
2 MEM_EMD7-0_SELECT 0=Selects CI0-7 as EMIF data bus D0:D7 pins

3.5.4 SW4, 4 Position User Readable

Switch SW4 is a 4 position bank of user readable switches via the I
individual switches can be placed in any position and read by the user software

from the expander. See the section on I

3.5.5 SW5, Power On Reset Switch

Switch SW5 is a momentary switch that asserts power on reset to the DM6437 device.

3.5.6 SW6, Reset Switch

Switch SW6 is a momentary switch that asserts a reset to the DM6437 processor.

1=Selects CI0-7 as COUT data bus D0:D7 pins

2

C expander. The

2

C expanders for more information .

3-23

Spectrum Digital, Inc

3.5.7 SW7, Slide Switch

Switch SW7 is a 2 position slide switch used by demonstration software. The switch is
read via a I

2

C expander. Refer to the I2C section for more information.

3-24 DM6437 EVM Technical Reference

Spectrum Digital, Inc

3.6 Test Points

The EVM has 51 test points. All test points appear on the top of the board. The
following figure identifies the position of each test point. the next table list each test
point and the signal appearing on that test point .

TP36
TP18
TP17

TP15
TP16

TP21
TP14
TP13

TP29
TP37

TP12

TP7

TP30

TP31

TP27

TP25

TP26

TP28

TP38

TP32

TP34

TP33

TP23

TP22

TP47
TP46

TP8

TP59

TP10

TP69
TP70

TP41

TP1

TP40

TP64

TP42

TP43

TP48,TP49

TP4,TP5

TP6,TP2

TP58

TP19

TP20

Figure 3-20, DM6437 EVM, Test Points

3-25

Spectrum Digital, Inc

Table 23: DM6437 EVM Test Points

Test Point

#

TP1 RESETOUTn TP27 GND
TP2 RSV4 TP28 GND
TP6 RSV5 TP29 GND
TP7 GND TP30 GND

TP8 GND TP31 VCC_5V
TP10 GND TP32 3V3_PWR_OK
TP12 Ethernet PHY Interrupt Pin TP36 1V8_P WR_OK
TP13 CAN Driver Output B_CANH TP40 DM6437 I2CCLK
TP14 CAN Driver Output B_CANL TP41 DM6437 I2CDATA
TP15 Codec MFP2 Pin TP52 VDD_1P1V
TP16 Codec MPF3 Pin TP53 VDD_1P1V
TP17 Codec GPIO1 Pin TP58 VIDEO DECODER GLCO/I2C Pin
TP18 Codec GPIO2 Pin TP59 VIC INPUT CLOCK
TP19 VIDEO DECODER AVID/GPIO Pin TP61 DM6437 HECC_RX
TP20 VIDEO DECODER INTREQ Pin TP64 DM6437 HECC_TX
TP21 CORE_PWR_O K TP69 DM6437 PWM1
TP25 GND TP70 DM6437CLK_OUT
TP26 GND

Signal

Test Point

#

Signal

Table 24: Power Pair Test Points

Power Pairs

Input1 Input2

TP4 TP5 DDR_VDDL 0.1 ohms
TP22 TP23 DSP_CORE_VDD 0.0 25 ohm s
TP33 TP34 VCC_3V3 0.025 ohms
TP37 TP38 VCC_1V8 0.025 ohms
TP42 TP43 DVD_3V3 0.025 ohms
TP47 TP46 DVDD_1V8 0.025 ohms
TP48 TP49 PLLPWR18 0.1 ohms
TP52 TP53 VDDA_1P1V 0.1 ohms
TP54 TP55 VDDA_1P8V 0.1 ohms

Power Domain

Resistance B etw een

Inputs

3-26 DM6437 EVM Technical Reference

Appendix A

Schematics

This appendix contains the schemati cs for the DM64 37 EVM.

A-1

Spectrum Digital, Inc

1

C

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

TITLE SHEET

SPECTRUM DIGITAL INCORPORATED

AUDIO CODEC - 00110(MFP1)(MFP0) AIC33

VIC PLL Expander - 0111(A2)(A1)(A0)

LED Expander - 0111(A2)(A1)(A0)

EEPROM - 1010(A2)(A1)(A0)

VIDEO DECODER - 101110(I2CA)TVP5146

DWG NO

Wednesday, December 06, 2006 1 34

B
Size:

Date:

Title:

Page Contents:

2

3

4

SCHEMATIC CONTENTS

SHEET01 - TITLE

SHEET02 - BLOCK DIAGRAM

SHEET03 - DSP CLKS/RST/EMU

SHEET04 - EMULATION

06/01/2006

R.R.P.

AB

AAA

2

3

DATE6DATE

DATE8DATE

06/01/2006

06/01/2006

06/01/2006

C.M.D.

R.R.P.

R.R.P.

RLSE

QA

MFG

4

USED ON

APPLICATION

NEXT ASSY

10

9

I2C Address Table

DEVICE FUNCTION

BINARY

00111000B USER INPUT Expander - 0111(A2)(A1)(A0)PCF8574

ADDRESS

HEX

0x38

SHEET05 - DSP Serial/CAN/I2 C

SHEET06 - DSP VP/EMIF/PC I/ENET

SHEET07 - DSP DDR Interface

SHEET08 - DSP DACS/GND-pins

SHEET09 - DSP Pow er Pins

SHEET10 - Boot DIP Switches

00111001B PCF8574

0x39

SHEET11 - VIC

SHEET12 - I2C Expanders

PCF8574

00111010B

0x3A

SHEET13 - I2C Expanders 2

SHEET14 - DDR2 Memories

PCF8574 VLYNQ IO Expander - 0111(A2)(A1)(A0)

CAT24C256

00111011B

01010000B

00011011B

01011101B

0x3B

0x50

0x1B

0x5D

DATE

DATE

DATE

06/01/2006

06/01/2006

R.R.P.

T.W.K.

R.R.P.

CHK

ENGR-MGR

DWN

ENGR

SHEET15 - EMIF Mux ing

SHEET16 - NAND-Flash/SRAM

SHEET17 - NOR-Flash/EEPROM

SHEET18 - ENET Mux ing

SHEET19 - ENET

SHEET20 - CAN

SHEET21 - RS232

SHEET22 - PCI-Mux

SHEET23 - PCI-M ux II

SHEET24 - PCI-Connector

SHEET25 - VLYNQ

SHEET26 - AIC33

SHEET27 - SPDIF/TVP5146- Switch

SHEET28 - TVP5146

SHEET29 - Video Out

SHEET30 - VIDEO DC Conn.

SHEET31 - EMAC/MCBSP DC Con n.

SHEET32 - VLYNQ/EMIF DC Con n.

SHEET33 - RES ET SUPERVISOR

SHEET34 - POWER

7

16 17 18 19 20

26 27 28 29 30

A

A

5

33 34

BB

REVISION STATUS OF SHEETS

AA

31 32

D D

C C

B B

ACBCAAA

ACCA

A

21 22 23 24 25 06/01/2006

AB

REV

SH

REV

A A

15

5

4

14 12 13

CAA

35

AAA AA

2

C

1

11

SH

SH

REV

A-2 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet of

1

509102-0001

Embedded

EMU

McBSP

EMU Header

S/PDIF Out

Audio Switch Ste reo Codec

DC Connector

CAN Switch CA N XCVR

UART Switches RS-232 XCVR

Video Out

Connectors

DDR2 SDRAM

Crystal/Osc

EMU Muxes

TMS320DM6437 Evaluation Module

BLOCK DIAGRAM

SPECTRUM DIGITAL INCORPORATED

DWG NO

Wednesday, December 06, 2006 2 34

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Date:

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1

2

MISC

DC Connector

cBSP0/McASP0

Socket

M

imer0
T

WM1
P

IO/PCI
G

SPI EEPROM

3

VIC

4

McBSP1/MCASP0

Timer1/HECC/

UART1

UART0/PWM0

DACs

DSP

I2C

I2C Expanders

I2C EEPROM

Video In

DC Connector

CCDC/EMIF/

McASP1/PCI

EMIF-Ctrl

Video SwitchVideo Decoder

EMIF SwitchNAND/NOR/SRAM

DDR2 IF

PLL

EMIF-Addr/PCI

Emulator

VENC/EMIF

Video Out

DC Connector

VLYNQ/PCI/

UHPI

PCI AD

UHPI/PCI/EMAC

ENET SwitchesENET XCVR

EMAC

Power Supplies

Reset Logic

VLYNQ

mPCI Connector

VLYNQ

DC Connector

DC Connector

2

3

4

Boot DIP Switches

5

D D

C C

B B

PCI Switches/Mux

PCI Edge Conn

A A

A-3

5

Spectrum Digital, Inc

1

2

C

Revision:

Sheet of

1

RESET_OUTn 22,31

TP1

TP30

TP2

TP30

SPECTRUM DIGITAL INCORPORATED

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

DSP CLKS/RST/EMU

Wednesday, December 06, 2006 3 34

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2

L15

N3

U1ADM6437

RESETOUTn

3

4

R1

10K

C1

1uF

VCC_3V3

R233

RESETnM4PORn

T3

N4

PCIEN23

SYS_RESETn17,19,26,28,30,33

RESETn4,22,30

K5

RSV4

RSV3L5RSV2

MXO

PCIEN

MXI/CLKIN

MXVSS

J19

K19

K18

R3

NO-POP

Y1

27MHz

C2 18 pF

VCC_1V8

L1

C4 18 pF

12

C3

.1uF

BLM21PG221SN1D

R19 NO-POP

R5 0

R4NO-POP

3

4

3

B

OPTIONAL OSCILLAT OR POPULATION

CRYSTAL AND CAPS REMOVED WHEN

SW6

1

2

5

JP3

HEADER 2 NO-POP

PUSHBUTTON SW

A

AA BB

OSCILLATOR IS USED

VCC4OUT

U2

GND2EN

NO-POP

ASFL3-27.000MHZ-EK-T

1

102229-0027

5

D D

C C

B B

A A

A-4 DM6437 EVM Technical Reference

Spectrum Digital, Inc

B

Revision:

Sheet of

1

C169

VCC_3V3

R148 NO POP

2

3

VCC_3V3

C164

0.1uF

VCC_3V3

4

VCC_3V3

C166

0.1uF

VCC_3V3

U41

JTAG MULTIPLEXERS

USB

EMBEDDED

EMU ON

R149

150

DS502

Green

4

3

5

2

U38

SN74AHC1G14DCKRG4

C165

0.1uF

R6

1K

DSP_TCK

NO POP

C168

0.1uF
R9 33

4

U37

SN74LVC1G32

53

VCC_3V3

1

2

C167

0.1uF

SP_EMU1

DSP_EMU0

DSP_TRST#

D

16

4

7

94A12

A

1A

2A

3

VCC

B2

4B1

3B1

4B213S

1B1

3

1B232B152B2

U539

2

6

14

11

10

_EMU1

T_TCK_RET

T

T_EMU0

T_TRSTn

XDS_EMU0

XDS_TRST#

XDS_TCK_RTN

XDS_EMU1

16

C163

VCC

2

DS_TDO
X

0.1uF

DSP_TDO

4

1A

1B1

T_TDO

U35

53

DSP_TDI

7

2A

B1

3B1

2B2

5

6

11

T_TDI

XDS_TDI

XDS_TCK

1

T_TCK

R8 33

4

3A94A

3B2101B232

14

XDS_TMS

4B1

2

DSP_TMS

12

T_TMS

4B213S

SN74LVC1G32

VCC_3V3

8

GND

OE

1

15

SN74CBTLV3257PWR

U1FDM6437

TMS

R2

R3

DSP_TMS

DSP_TDO

DSP_TDI

DSP_TRST#

8

GND

OE

SN74CBTLV3257PWR

1

15

EMU_STS

VCC_3V3

R152

10K

R150

10K

VCC_5V

5V

Embedded_USB_1

VCC_3V3

EMU1N2EMU0P2TDOP3TDIP4TRSTn

TCK

N1

DSP_TCK

DSP_EMU1

DSP_EMU0

R10 NO-POP R11 1K

T_TDO

T_EMU1

T_EMU0

T_TMS

T_TCK

T_TDI

T_TRSTn

T_TDI

T_TCK

T_TDO

T_TMS

T_EMU0

T_EMU1

T_TRSTn

3.3V

USB_DSP_RSTn

PONRSn

SPECTRUM DIGITAL INCORPORATED

R13 1K

R12 NO-POP

T_TCK_RET

GND

T_TCK_RET

CLK_12MHZ

CLK_24MHZ

Embedded_USB

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

DSP CLKS/RST/EMU

Wednesday, December 06, 2006 4 34

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Date:

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Page Contents:

1

2

3

4

XDS_EMU1

DS_TRST#
X

6

4

12

2

14

c
n

J6

GND

GND8GND10GND

TRST

EMU1

D

TMS1TDI3P

5

VCC_3V3

D D

TDO7TCKRET9TCK11EMU0

TSW-107-14-G-D-006

5

13

XDS_TVD

XDS_EMU0

XDS_TCK

XDS_TDO

XDS_TCK_RTN

DS_TMS
X

XDS_TDI

C C

VCC_3V3

R151

10K

VCC_3V3

RESETn3,22,30

EMU_SYS_RESETn33

B B

ALT_AIC33_CLK26

A A

A-5

5

Spectrum Digital, Inc

1

A

Revision:

Sheet o f

1

509102-0001

I2C_DATA 12,13,17,26,28,31

I2C_CLK 12,13,17,26,28,31

R16

2.2K

VCC_3V3

R15

2.2K

TOUT1L 20,21,31

TINP1L 20,21,31

TMS320DM6437 Evaluation Module

DWG NO

DSP Serial/CAN/I2C

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 5 34

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2

TP61

TP64

TP-60

PWM1 11,30

CLK_OUT 6,11,30

3

PWM1_I2C_INT

42

1

VCC_3V3

4

U3

C7

.1uF

3 5

74LVC1G125DCKRG4

I2C_INT12

U1EDM6437

R14 33

F3

M1

K4

GP[4]/PWM1

CLK_OUT/PWM2/GP[84]

AMUTEIN0/FSX1/GP[109]F2AFSX0/DX1/GP[107]G2AXR0[0]/FSR1/GP[105]H2AMUTE0/DR1/GP[110]

ACLKX0/CLKX1/GP[106]

AHCLKX0/CLKR1/GP[108]

F1

G3

G1

TP-60

TP41

TP40

TP-30

UTXD0 21,31

URXD0 21,31

UCTS0 31

URTS0 31

L2

K3

L1

L4

L3

TXD0/GP[86]

U

UCTS0/GP[87]

URXD0/GP[85]

TP-30

GIO000 23

GIO002 23

GIO001 23

GIO003 23

E4

M2

M3

I2C_CLK

I2C_DATA

AD[0]/GP[0]E1AD[1]/GP[1]E2AD[2]/GP[2]E3AD[3]/GP[3]

URTS0/PWM0/GP[88]

HECC_RX/TINP1L/URXD1/GP[56]

HECC_TX/TOUT1L/UTXD1/GP[55]

HCLKR0/CLKR0/GP[101]

A

J2

AXR0[1]/DX0/GP[104]J3AXR0[2]/FSX0/GP[103]H3AXR0[3]/FSR0/GP[102]

ACLKR0/CLKX0/GP[99]H1CLKS0/TOUT0L/GP[97]

G4

CLKS1/TINP0L/GP[98]

AFSR0/DR0/GP[100]

J4

K2

H4

2

3

4

R434 33

R429 0

R432 0

R430 0

R18

NO-POP

R251

10K

VCC_3V3

5

I2C_INT_ENABLEn30

D D

R431 0

FSR126,31

DR126,31

FSX126,31

CLKR126,31

DX126,31

CLKX126,31

C C

CLKR031

R436 33

R435 33

R433 33

DX017,26,31

FSX017,31

FSR031

CLKX017,26,31

TINP0L11,31

DR017,26,31

TOUT0L31

5

B B

A A

A-6 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet o f

1

RXCLK 23

RXD3 23

RXD2 23

RXD1 23

RXD0 23

RXER 23

TXEN 23

RXDV 23

MDC 23

VSYNC 30

CI7 22

CI6 22

CI5 22

CI4 22

CI3 22

CI2 22

CI1 22

C_FIELD 15,30

EM_A02_CLE 16,17,30

EM_BA1 10,16,17,30

EM_BA0 10,16,17,30

EM_A00 10,16,17,30

EM_A01_ALE 16,17,30

EM_A04 10,16,17,30

EM_A03 16,17,30

R167 20K

R166 20K

R165 NO-POPRN14G RPACK8-22

R168 NO-POP

89

2

VCC_3V3

10111213141516

RN2 RPACK8-22

EM_A09 22

EM_A06 22

EM_A05 22

EM_A07 22

EM_A08 22

EM_A11 22

EM_A10 22

EM_A12 22

1234567

CI0 22

HSYNC 30

EM_CS2 15

LCD_OE 30

AD26 22

AD28 22

C_WEN 30

RN14BRPACK8-22

RN14ARPACK8-22

RN14CRPACK8-22

3

2

1

A

A

A

B

B

B

14

15

16

AD30 22

RN14ERPACK8-22

5

4

A

A

B

B

12

13

MDIO 23

SPECTRUM DIGITAL INCORPORATED

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

DSP VP/EMIF/PCI/ENET

Wednesday, December 06, 2006 6 34

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Page Contents:

1

2

B11

A10

C16

A16

D8

B9

D12

C17

B17

B16

A17

B18

U1GDM6437

M_A[6]/AD20/GP[95]

EM_A[5]/AD19/GP[96]B8E

R1/EM_A[0]/GP[7]/(AEM2)

B2/EM_BA[1]/GP[5]/(AEM0)

R2/EM_BA[0]/GP[6]/(AEM1)

G1/EM_A[1]/(ALE)/GP[9]/(AEAW1)

3

EM_WAIT/(RDY/BSYn)

EM_OEn

EM_WEn

COUT2/EM_D[2]/GP[16]

COUT1/EM_D[1]/GP[15]

COUT0/EM_D[0]/GP[14]

E15

E14

D15

9

4

11

B
A

8

6

RN14 H RPACK8- 22

RN14F RPACK8-22

D17

D18

D16

10

B

B

A

A

7

89

10111213141516

RN1 RPACK8-22

WAIT_BSYn PULL UP ON PAGE 16

5

COUT015,30

COUT115,30

READ_OE16,17,30

COUT215,30

WRITE_WE16,17,30

WAIT_BSYn16,30

EM_A[7]/AD22/GP[94]C9EM_A[8]/AD21/GP[93]

C_FIELD/EM_A[21]/GP[34]

R0/EM_A[4]/GP[10]/AEAW2)

B0/LCD_FIELD/EM_A[3]/GP[11]

B1/EM_A[2]/(CLE)/GP[8]/(AEAW0)

COUT3/EM_D[3]/GP[17]

COUT4/EM_D[4]/GP[18]

COUT5/EM_D[5]/GP[19]

COUT6/EM_D[6]/GP[20]

COUT7/EM_D[7]/GP[21]

F16

F17

E16

A12

E18

E17

1234567

1234567

RN4 RPACK8-22

YI7

COUT315,30

YI727,30

COUT415,30

COUT515,30

COUT615,30

COUT715,30

B10

C11

A11

D10

D9

C10

EM_A[10]/AD23/GP[91]A9EM_A[11]/AD24/GP[90]

EM_A[9]/PIDSEL/GP[92]

EM_A[12]/PCBE3/GP[89]

YI7(CCD7)/GP[43]

YI6(CCD6)/GP[42]

YI5(CCD5)/GP[41]

YI4(CCD4)/GP[40]

YI3(CCD3)/GP[39]

B13

B14

C13

D14

C14

D11

B12

C12

CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]

CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]

CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]

CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]

CI1(CCD9)/EM_A[19]/PREQn/EM_D[6]/GP[45]

CI2(CCD10)/EM_A[18]/PRSTn/EM_D[5]/GP[46]

CI4(CCD12)/EM_A[16]/PGNTn/EM_D[3]/GP[48]

YI2(CCD2)/GP[38]

YI1(CCD1)/GP[37]

YI0(CCD0)/GP[36]

YOUT7/GP[29]

B15

C15

H15

H16

1234567

10111213141516

8 9

RN6 RPACK8-10

YI0YI1

YI3

YI5

YI2

YI4

YI6

YI627,30

YI527,30

YI427,30

YI327,30

YI227,30

YI127,30

YI027,30

YOUT610,30

YOUT510,30

YOUT730

YOUT4_FASTB OOT10,30

E19

C19

C18

F19

E10

E11

D13

C_WE/RNW/GP[35]

G0/EM_CS2n/GP[12]

LCD_OE/EM_CS3n/GP[13]

E12

AD26

AD28

SYNC/EM_CS4n/GP[32]
V

HSYNC/EM_CS5n/GP[33]

CI0(CCD8)/EM_A[20]/PINTAn/EM_D[7]/GP[44]

PBECLK/GP[30]

VCLK/GP[31]

VD/GP[53]

PCLK/GP[54]

HD/GP[52]

YOUT6/GP[28]

V

YOUT5/GP[27]

YOUT4/GP[26]/(FASTBOOT)

YOUT3/GP[25]/(BOOTMODE3)

YOUT2/GP[24]/(BOOTMODE2)

YOUT1/GP[23]/(BOOTMODE1)

YOUT0/GP[22]/(BOOTMODE0)

F15

F18

H17

G17

G16

G15

VLYNQ_CLOCK/PCICLK/GP[57]

A7

A13

A14

A15

D19

G19

D2

B3

D3

C3

A3

C2

C4

AD30

HINTn/MRXD3/AD6/GP[82]

HDS1n/MRXD1/AD7/GP[79]B2HDS2n/MRXD0/AD9/GP[78]

HRNW/MRXCLK/AD8/GP[77]

HHWIL/MRXDV/AD13/GP[74]

HCNTL1/MTXEN/AD11/GP[75]

HCNTL0/MRXER/AD10/GP[76]

HRDYn/MRXD2/PCBE0/GP[80]

HD0/VLYNQ_SCRUN/AD18/GP[58]C8HD1/VLYNQ_RXD0/AD16/GP[59]D7HD2/VLYNQ_RXD1/AD17/GP[60]A8HD3/VLYNQ_RXD2/PCBE2n/GP[61]B7HD4/VLYNQ_RXD3/PFRAMEn/GP[62]C7HD5/VLYNQ_TXD0/PIRDYn/GP[63]A6HD6/VLYNQ_TXD1/PTRDYn/GP[64]D6HD7/VLYNQ_TXD2/PDEVSELn/GP[65]B6HD8/VLYNQ_TXD3/PPERRn/GP[66]A5HD9/MCOL/PSTOPn/GP[7]C6HD10/MCRS/PSERRn/GP[68]B5HD11/MTXD3/PCBE1/GP[69]C5HD12/MTXD2/PPAR/GP[70]D5HD13/MTXD1/AD14/GP[71]B4HD14/MTXD0/AD15/GP[72]D4HD15/MTXCLK/AD12/GP[73]

D1

C1

HASn/MDIO/AD3/GP[83]

HCSn/MDCLK/AD5/GP[81]

3

A4

4

89

10111213141516

R312 0

R268 N O-POP

R311 0

R184 0 RN14DRPACK8-22

R313 0

R27 22

R183 N O-POP

VD27,30

HD27,30

AD1822

AD1622

VCLK30

VPBECLK30

VID_CLK11

CLK_OUT5,11,30

YOUT1_BOOTMODE110,30

YOUT3_BOOTMODE310,30

YOUT0_BOOTMODE010,30

YOUT2_BOOTMODE210,30

AD1722

PCLK27

PCICLK22

PCBE2n22

COL23

CRS23

TXD323

TXD223

TXD123

TXD023

PPERn23

PTRDYn23

PIDRDYn22

PFRAMEn22

PDEVSELn23

TXCLK23

5

D D

C C

B B

A A

A-7

Spectrum Digital, Inc

1

DDR_A[0:12] 14

2

RN7 RPACK4-22

3

DR_A4

DDR_A0

DDR_A1

DDR_A2

DDR_A3

D

DDR_A5

DDR_A6

DDR_A7

678

678

123

4 5

123

4 5

RN8 RPACK4-22

DDR_A4

BDDR_A1

BDDR_A2

BDDR_A0

BDDR_A3

B

BDDR_A5

BDDR_A6

BDDR_A7

W13

U13

V13

U12

V12

W12

W11

V11

U1CDM6437

DR_A[6]

DDR_A[0]

DDR_A[1]

DDR_A[2]

DDR_A[3]

DDR_A[4]

DDR_A[5]

D

DDR_A[7]

A

Revision:

Sheet of

1

509102-0001

VCC_1V8

TMS320DM6437 Evaluation Module

DWG NO

DSP DDR Interface

SPECTRUM DIGITAL INCORPORATED

L3

DDR_BS02 14

DDR_BS01 14

DDR_BS00 14

DDR_WE 14

DDR_CAS 14

DDR_RAS 14

DDR_CKE 14

DDR_WE

DDR_CAS

DDR_RAS

DDR_BS00

DR_A12

DDR_A8

DDR_A9

DDR_A10

DDR_A11

D

678

678

4 5

123

4 5

RN10 RPACK4-22

RN9 RPACK4-22

BDDR_A8

BDDR_A9

BDDR_A10

BDDR_A11

BDDR_A12

BDDR_BS00

U8

U10

W10

W9

V10

U11

DDR_A[8]

DDR_A[9]

DDR_A[10]

DDR_A[11]

DDR_A[12]

DDR_CKEBDDR_CKE

DDR_BS01

DDR_BS02

123

45

123

678

RN11 RPAC K4-22

BDDR_CAS

BDDR_RAS

BDDR_WE

BDDR_BS02

BDDR_BS01

T7

U7

U9

V8

T8

DDR_CKE

DDR_WEn

DDR_BS[0]

DDR_BS[1]V9DDR_BS[2]

DDR_CASn

DDR_RASn

DDR_CLK_N 14

DDR_CS 14

R29 22

BDDR_CS DDR_ CS

T9

DDR_CSn

DDR_CLK 14

DDR_DQM0 14

DDR_DQM3 14

DDR_DQM1 14

DDR_DQM2 14

DR_DQM1

DDR_DQM0

D

DDR_DQM2

DDR_DQM3

R85 22

R84 22

R86 22

R87 22

R30 10

R31 10

R32 200

DDR_DQM1

BDDR_DQM0

B

BDDR_DQM2

BDDR_DQM3

BDDR_CLK_N DDR_CLK_N

BDDR_C LK DDR_CLK

W7

T4

DDR_DQM[0]

T10

W8

T14

T16

DDR_CLK0

DR_DQM[3]

DDR_CLK0n

DDR_DQM[1]T6DDR_DQM[2]

D

BLM21PG221SN1D

1 2

TP5

TP-30

1uF

C10

R35 0.00X

TP4

TP-30

0.1uF

C8

R33 200

TP6

TP-30

R34 0

DDR_PADREFP

R13

T12

T13

T11

RSV5

DDR_ZP

DDR_ZN

DDR_VSSDLL

DDR_VDDDLL

Wednesday, December 06, 2006 7 34

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Date:

Title:

Page Contents:

2

3

DR_D[6]

DDR_D[0]

DDR_D[1]T2DDR_D[2]U1DDR_D[3]U2DDR_D[4]V2DDR_D[5]U3D

DDR_D[7]W3DDR_D[8]V4DDR_D[9]W4DDR_D[10]U5DDR_D[11]V5DDR_D[12]W5DDR_D[13]V6DDR_D[14]W6DDR_D[15]V7DDR_D[16]

T1

V3

DR_D4

DDR_D6

DDR_D0

4

DDR_D[0:31]14

5

D D

DDR_D8

DDR_D1

DDR_D2

DDR_D3

D

DDR_D5

DDR_D7

DDR_D9

DDR_D[17]

DDR_D[18]

DDR_D[19]

DDR_D[20]

DDR_D[21]

DDR_D[22]

DDR_D[23]

T17

V14

V15

V16

U15

W14

W15

W16

DR_D15

DDR_D12

DDR_D14

DDR_D20

DDR_D16

DDR_D19

DDR_D21

DDR_D22

DDR_D23

DDR_D17

DDR_D10

DDR_D11

DDR_D13

D

DDR_D18

DDR_D24

C C

DR_D[31]

DDR_DQS[0]

DDR_DQS[1]U6DDR_DQS[2]

DDR_D[24]

DDR_D[25]

DDR_D[26]

DDR_D[27]

DDR_D[28]

T18

V17

U17

U18

W17

DDR_D25

DDR_D26

DDR_D28

DDR_D27

DDR_DQS[3]

DDR_D[29]

DDR_D[30]

D

T19

V18

U19

DR_D29

DDR_D31

D

DDR_D30

DDR_DQS0

VCC_1V8

DDR_VREF

U4

T15

U14

U16

0.1uF

C9

REF_STL
V

DDR_DQS1

DDR_DQS2

DDR_DQS3 DDR_PADREFN

DDR_DQS214

DDR_DQS314

DDR_DQS114

DDR_DQS014

R76

1K 1%

R77

1K 1%

C5

C111

0.1uF

0.1uF

VREF_STL14

B B

Designers mus t use routing techniques from

DDR2 PCB

Layout Applica tion Note

TP8

TP-60

TP10

TP-60

TP9

TP-60

TP7

TP-60

4

5

A A

A-8 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

DSP DACS/GND-pins

SPECTRUM DIGITAL INCORPORATED

DAC_IOUT_B 29

DAC_IOUT_A 29

DAC_IOUT _ D 29

DAC_IOUT _ C 29

Wednesday, December 06, 2006 8 34

B
Size:

Date:

Title:

Page Contents:

1

2

L11

L13

L17

L19

M10

M12

M14

M16

M17

M18

M19

M6

N11

N13

N14

P10

P12

P14

R11

R15

R17

R18

R19

V19

N18

N17

P19

P18

P15

P16

U1DDM6437

DAC_IOUT_A

DAC_VREF

N19

3

REF_0.5V
V

4

R37 7.5K 1%

SSA_1P1V
V

DAC_IOUT_B

C11

R39

4.99K 1%

VSSA_1P8V

DAC_IOUT_C

DAC_IOUT_D

DDA_1P1V

DAC_RBIAS

V

VDDA_1P8V

P17

N16

N15

DAC_RBIAS29

.1uF

1uF

C12

R322 0.1

ss.42

U1HDM6437

Vss.38K6Vss.39K8Vss.40

Vss.41

V

Vss.43

Vss.44L7Vss.45L9Vss.46

Vss.47

Vss.48

Vss.49

Vss.50

Vss.51

Vss.52

Vss.53

Vss.54M8Vss.55

Vss.56

Vss.57

Vss.58N5Vss.59N7Vss.60N9Vss.61

Vss.62

Vss.63

Vss.64P6Vss.65P8Vss.66R1Vss.67

Vss.68

Vss.69

ss.5

Vss.1

Vss.2B1Vss.3

Vss.6E9Vss.4

V

Vss.8

Vss.9

Vss.10F4Vss.11F6Vss.12F8Vss.13

Vss.14

Vss.15

Vss.16G5Vss.18G9Vss.19

Vss.20

Vss.21

Vss.22

Vss.23H6Vss.24H8Vss.25

Vss.26

Vss.27

Vss.28

Vss.29

Vss.7

E7

F12

F14

F10

A19

B19

E13

C14

.001uF

C13

.1uF

10uF

+ C15

+ C16

TP53

TP-30

R323 0.1

TP52

TP-30

Vss.17

G7

H10

H12

H14

G11

G13

C18

.001uF

C17

.1uF

10uF

TP55

TP54

H19

G18

TP-30

TP-30

Vss.30J5Vss.31J7Vss.32J9Vss.33K1Vss.34

J11

J13

J15

J17

J18

W2

Vss.70

Vss.71

Vss.72R5Vss.73R7Vss.74R9Vss.75

Vss.76W1Vss.77

Vss.37

Vss.35

Vss.36

K10

K16

K12

K14

2

3

4

R38

5

VCC_3V3

1K

R36

D D

R41

0

NO-POP

42

5 3

1

U4

TLV431ADBV

VREF =1.24 VOLTS

L4

1 2

BLM21PG221 SN1D

DSP_CORE_VDD

C C

L5

1 2

BLM21PG221 SN1D

VCC_1V8

B B

A A

A-9

5

Spectrum Digital, Inc

1

0.1uF

C37

C26

0.1uF

0.1uF

C25

2

3

0.1uF

C24

0.1uF

C23

0.1uF

C22

0.1uF

C21

0.1uF

C20

0.1uF

C19

C28

33uF

+

C27

33uF

+

0.1uF

C36

0.1uF

C35

0.1uF

C34

0.1uF

C33

0.1uF

C32

0.1uF

C31

0.1uF

C30

0.1uF

C29

C39

33uF

+

A

Revision:

Sheet o f

0.1uF

C188

0.1uF

C70

0.1uF

C67

0.1uF

C66

0.1uF

C65

0.1uF

C190

0.1uF

C48

0.1uF

C47

0.1uF

C46

0.1uF

C45

0.1uF

C44

0.1uF

C43

0.1uF

C42

C41

33uF

+

0.1uF

C189

0.1uF

C54

0.1uF

C53

0.1uF

C52

0.1uF

C51

0.1uF

C50

0.1uF

C49

C56

33uF

+

C55

33uF

+

Place near DDR side of package

0.1uF

C64

0.1uF

C63

0.1uF

C62

0.1uF

C61

0.1uF

C60

0.1uF

C59

0.1uF

C58

C69

33uF

+

C57

33uF

+

12

VCC_1V8

L6

BLM21PG221 SN1D

TP49

TP-30

R3200.00x

TP48

TP-30

C73

1uF

C72

0.1uF

TMS320DM6437 Evaluation Module

SPECTRUM DIGITAL INCORPORATED

Title:

1

509102-0001

DWG NO

DSP Power Pin s

Wednesday, December 06, 2006 9 34

B
Size:

Date:

Page Contents:

2

3

C71

DVDD_3V3

4

0.025

5

VCC_3V3

DVDD_3V3

K17

M15

P1

K15

U1JDM6437

DVDD_3V3

R317

DVdd33.20

DVdd33.21L6DVdd33.22

DVdd33.19

DVdd33.2

DVdd33.1A1DVdd33.4E6DVdd33.5E8DVdd33.3A2DVdd33.6

A18

TP43

TP-60

TP42

TP-60

D D

DVdd33.23M5DVdd33.24N6DVdd33.25

F11

F13

DVdd33.7

G10

G12

DVdd33.26G8DVdd33.27

DVdd33.8F5DVdd33.9F7DVdd33.10F9DVdd33.11

DVdd33.28

Vdd33.12
D

G6

H18

G14

VDD_CORE

C

DVdd33.13

DVdd33.14H5DVdd33.15J1DVdd33.16

DVdd33.17

DVdd33.18

J6

J14

J16

DSP_CORE_VDD

CVDD_CORE

J12

H11

H9

K13

J10

J8

U1IDM6437

CVdd.14

CVdd.15H7CVdd.17

CVdd.16

CVdd.11

CVdd.13

CVdd.12

CVDD_CORE

CVdd.3

CVdd.2M9CVdd.1

CVdd.6

CVdd.7

CVdd.4

CVdd.5L8CVdd.9K9CVdd.10

M7

L10

L12

M11

M13

POWER TEST POINT AT THE REGULATOR FOR 1.2 V

C C

DVDD_1V8

R14

R16

W18

DVDDR2.9

DVDDR2.10

DVDDR2.1

MXVDD

L18

DVDDR2.11R4DVDDR2.12R6DVDDR2.13R8DVDDR2.14T5DVDDR2.15V1DVDDR2.16

DVDDR2.2

DVDDR2.3

DVDDR2.4P5DVDDR2.5P7DVDDR2.6P9DVDDR2.7

P11

P13

B B

W19

DVDDR2.17

DVDDR2.8

R10

R12

TP46

TP-60

TP47

TP-60

N10

N12

H13

U1BDM6437

Vdd.18

CVdd.21N8CVdd.20

CVdd.19

C

Vdd.8
C

K7

K11

L14

DVDD_1V8

R319

0.025

VCC_1V8

1000pF

E5

L16

RSV1

U1KDM6437

PLLPWR18

MH44MH55MH6

MH11MH22MH3

A A

6

3

U1LDM6437

4

5

A-10 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet o f

1

509102-0001

YOUT0 -> BootMode0

YOUT1 -> BootMode1

YOUT2 -> BootMode2

YOUT3 -> BootMode3

YOUT4 -> FASTB

TMS320DM6437 Evaluation Module

DWG NO

Boot DIP Switches

VCC_3V3

1234567

89

RN13 RPACK8-1.5K

10111213141516

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 10 34

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Date:

Title:

Page Contents:

1

2

1234567

89

1234567

1615141312

YOUT0_BOOTMODE06,30

YOUT1_BOOTMODE16,30

YOUT2_BOOTMODE26,30

8

10

11

DIP_SWITCH-8

R364

20K

YOUT66,30

YOUT56,30

YOUT4_FASTB OOT6,30

YOUT3_BOOTMODE36,30

SW1

ON

R258

20K

VCC_3V3

3

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8 9

RN12

RPACK8-20K

4

EM_A00 6,16,17,30

EM_BA0 6,16,17,30

EM_BA1 6,16,17,30

EM_A04 6,16,17,30

B2_AEM0

R1_AEM2

R2_AEM1

R0_AEAW 2

R176

20K

R175

20K

R43

20K

R42

20K

123

45

123

4

SW2

ON

678

DIP_SWITC H-4

R45 1.5K

R173 1. 5 K

R44 1.5K

R174 1. 5 K

CC_3V3
V

2

3

4

5

D D

C C

B B

A A

A-11

5

Spectrum Digital, Inc

A

Revision:

VID_CLK 6

1

2

3

4

C77

0.1uF
R46 33

42

R47 0

1

VCC_3V3

U5

VCC_3V3

3 5

74LVC1G125DCKRG4

C84

10uF

+

C83

0.1uF

C82

0.1uF

C81

0.1uF

C80

C367

+

VCC_3V3

C79

C78

NO-POP

C86

VCC_3V3

0.1uF

10uF

9

AGND

U7

CSEL

12

PLL_CSEL13

C85

0.1uF

VCC_3V3

NO-POP

Y2

27MHz

U6

TP59

TP-30

AUDIO_CLK 26,31

0.1uF
R54 33

R58 0

42

74LVC1G125DCKRG4

1
3 5

U8

VCC_3V3

R55 NO-POP

R57 NO-POP

R53 NO-POP

R50 33

8

19

2

13

20

14

VCC

VDD11VDD2

VDD3

SCKO0

SCKO33SCKO118SCKO2

MCKO215MCKO1

PLL1705DBQ

XT110XT2

DGND14DGND2

SR7FS26FS1

5

PLL_FS113

PLL_FS213

PLL_SR13

8

7

X2

NC

X1

1

2

DGND3

11

16

17

R59

NO-POP

R350 33

R60

33

C370

10pF

6

5

VDD

CLKOUT

PI6CX100-27W

GND

VIN3NC

4

C87

0.1uF

TINP0L 5,31

SPECTRUM DIGITAL INCORPORATED

R62 33

5

4

3

B

VCC

C89

0.1uF

PLL_PCLK30

GND

U9

A

OE

2

1

SN74CBTLV1G125

R189

R324

NO-POP

VCC_3V3

10K

VIC_TINP0L_ENABLEn31

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

VIC

Wednesday, December 06, 2006 11 34

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Date:

Title:

Page Contents:

2

3

4

R49 100K

2.2K

R48

VCC_3V3

5

D D

C C

Q1

2N3904

C88

R52 22.1K 1%

TP69

TP-60

100pF

5

R51 NO-POP R56 33

PWM15,30

R437 0

TP70

TP-60

CLK_OUT5,6,30

B B

A A

A-12 DM6437 EVM Technical Reference

Spectrum Digital, Inc

C

Revision:

Sheet of

1

509102-0001

R67

123

45

RN38

678

RPACK4-1K

R7 1K

SW7

GS01MSAKE

3

2

1

4 5

2

SILKSCREEN:

NTSC by pin 1

PAL by pin 3

R17 1K

3
2
1

JP1

3 PIN JUMPER

VCC_3V3

330

DS4

LED_RED

R66

330

DS3

LED_GRN

USER CONTROLLED LEDS

R65

330

DS2

LED_GRN

R64

330

DS1

LED_GRN

VCC_3V3

8

15P314

11

A06A17A29P010P212P1

GND

U11

VDD5SDA4SCL2INT1P720P619P517P4

VCC_3V3

C91

.1uF

NC.13NC.2

NC.418NC.3

PCF8574APWRG4

16

13

TMS320DM6437 Evaluation Module

DWG NO

I2C Expanders

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 12 34

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1

2

3

4

5

RN37

RPACK8-10K

8 9
7

10

6

11

5

12

4

13

3

14

2

15

1

16

VCC_3V3

15P314

11

1

A06A17A29P010P212P

U10

VCC_3V3

C90

.1uF

VDD5SDA4SCL2INT1P

I2C_CLK5,13,17,26,28,31

I2C_DATA5,13,17,26,28,31

GND

NC.13NC.2

7

P619P517P4

NC.418NC.3

20

16

VCC_3V3

SILKSCREEN:

SW4 PADDLE DIP-4

8

USER SWITCHES

4 5
3

6

2

7

1

8

VCC_3V3

RN20

RPACK4-10K

PCF8574APWRG4

13

R74

10K

2

1

3

5

U66

4

C187

.1uF

SN74AHC1G14DCKRG4

I2C_INT5

USER_I2C_IO.A0P731

USER_I2C_IO.A0P631

VLYNQ_RESET25,32

3

4

5

D D

C C

B B

A A

A-13

Spectrum Digital, Inc

1

A

Revision:

Sheet of

1

C206

0.1uF

McASP_ONn 26

4

U74

53

1

2

SPECTRUM DIGITAL INCORPORATED

SN74LVC1G32

McBSP_ONn 26

C205

0.1uF

4

U73

SN74LVC1G32

53

VCC_3V3

1

2

4

U42

SN74AHC1G14DCKRG4

3

5

VCC_3V3

2

1

VCC_3V3

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

I2C Expanders

Wednesday, December 06, 2006 13 34

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Date:

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Page Contents:

2

R185

10K

MEM_EMD7-0_SELECT 15

3

R252

NO-POP

VCC_3V3

1

23

1

2

SW3

4

4

DIP_SWITCH-2

VCC_3V3

AIC33_ENABLEn31

45
3
2
1

RN34

RPACK4-10K

VCC_3V3

6
7
8

A06A17A29P010P212P1

U13

VDD5SDA4SCL2INT1P720P619P517P4

R161 1K

VCC_3V3

C92

0.1uF

C170

0.1uF

I2C.IOP3

I2C.IOP5

I2C.IOP4

SPDIF_ONn 26

RN15

RPACK8-10k

89
7

10

6

11

5

12

4

13

3

14

2

15

1

VCC_3V3

C185

0.1uF

16

A06A17A29P010P212P1

U64

VDD5SDA4SCL2INT1P720P619P517P4

11

VCC_3V3

USER_I2C_IO.A1P0 31

USER_I2C_IO.A1P1 31

USER_I2C_IO.A1P2 31

USER_I2C_IO.A1P3 31

8

15P314

11

3

C.1

GND

N

NC.2

C.4

PCF8574APWRG4

N

NC.3

16

18

13

N22
R

RPACK4-10K

45
3

6

2

7

1

VCC_3V3

8

I2C.IOP6

CORE_VDD_S EL EC T 33

15P314

8

GND

NC.13NC.2

PCF8574APWRG4

NC.418NC.3

16

13

2

3

4

I2C_CLK5,12,17,26,28,31

I2C_DATA5,12,17,26,28,31

PLL_CSEL11

PLL_FS111

PLL_FS211

PLL_SR11

VCC_3V3

5

D D

C C

B B

I2C_CLK5,12,17,26,28,31

I2C_DATA5,12,17,26,28,31

5

A A

A-14 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet o f

1

22uF

C103

+

C101

0.1uF

C100

0.1uF

C99

0.1uF

C98

0.1uF

2

VCC_1V8VCC_1V8

V1

U17

VDD.1M9VDD.2H1VDD.3R9VDD.4D1VDD.5

VDDQ.1F3VDDQ.2F7VDDQ.3K1VDDQ.4K3VDDQ.5K7VDDQ.6K9VDDQ.7D9V

VREF_STL 7

509102-0001

DDR_D30

DDR_D25

678

4 5

BDDR_D30

BDDR_D28

BDDR_D25

BDDR_D27

BDDR_D26

BDDR_D25

G7

DQ9F2DQ8F8DQ7J9DQ6J1DQ5L9D

DR_D16

DDR_D27

DDR_D23

D

123

123

RN28 RPACK4-22

DDR_D16

BDDR_D27

BDDR_D23

B

DDR_D22

BDDR_D24

BDDR_D23

B

DDR_D20

DDR_D17

DDR_D21

DDR_D22

DDR_D19

DDR_D18

678

678

4 5

123

4 5

RN30 RPACK4-22

BDDR_D17

BDDR_D19

BDDR_D20

BDDR_D22

BDDR_D21

BDDR_D18

BDDR_D21

BDDR_D20

BDDR_D19

BDDR_D18

BDDR_D17

BDDR_D16

L1

Q4

DQ3L3DQ2L7DQ1K2DQ0

M3

K8

VSS.1U9VSS.2T1VSS.3H3VSS.4D3VSS.5

VSSQ.1G8VSSQ.2J8VSSQ.3D7VSSQ.4J2VSSQ.5E2VSSQ.6L8VSSQ.7L2VSSQ.8E8VSSQ.9

H7

G2

M7

VSSDL

VSSQ.10

TMS320DM6437 Evaluation Module

DWG NO

DDR2 Memories

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 14 34

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DDR_D29

DDR_D26

DDR_D24

DDR_D31

C110

0.1uF

C109

0.1uF

C108

0.1uF

VREF_STL

C107

0.1uF

F1

F9

H9

DDQ.8

VDDQ.9

VDDQ.10

678

123

4 5

RN24 RPACK4-22

C113

0.1uF

RN26 RPACK4-22

BDDR_D29

BDDR_D31

BDDR_D24

BDDR_D26

BDDR_D[16:31]

BDDR_D31

BDDR_D30

BDDR_D29

BDDR_D28

M2

DQ15E9DQ14E1DQ13G9DQ12G1DQ11G3DQ10

VDDLM1VREF

1

2

92-ball DDR Package

J3

BDDR_DQS2

R8322

DDR_DQM3

DDR_DQM2

DDR_DQS2

DDR_DQS27

DDR_DQM27

DDR_DQM37

H7

G2

M7

VSSDL

VSSQ.10

64 MEGABYTES 64 MEGABYTES

92-ball DDR Package

Layout schematic is shown for the 92-ball

DDR Package but is compatible with 84-ball

DDR2 Devices.

3

4

J3

BDDR_DQS0DDR_DQS0

DDR_DQM1

DDR_DQM0

R82 22

DDR_D[0:31]7

5

DR_D14
D

DDR_D12

DDR_D2

678

123

4 5

DDR_D14
B

BDDR_D12

BDDR_D2

BDDR_D0 DDR_D0

DDR_D6

BDDR_D7

BDDR_D9

B

BDDR_D8

DQ9F2DQ8F8DQ7J9DQ6J1DQ5L9D

DT

CS#P8CAS#P7RAS#N7WE#N3CKEN2CKM8CK#N8UDQS#/NUD8UDQSE7LDQS#/NUH8LDQSJ7UDME3LDM

N9

DDR_CLK

DDR_CS

DDR_RAS

DDR_CKE

DDR_CAS

DDR_WE

R79 22

DDR_D4

DDR_D3

DDR_D6

DDR_D1

DDR_D11

DDR_D9

678

123

4 5

123

RN29 RPACK4-22

RN27 RPAC K4-22

BDDR_D3

BDDR_D1

BDDR_D4

BDDR_D11

BDDR_D9

BDDR_D6

BDDR_D1

BDDR_D4

BDDR_D2

BDDR_D5

BDDR_D3

BDDR_D0

L1

K8

Q4

DQ3L3DQ2L7DQ1K2DQ0

VSS.1U9VSS.2T1VSS.3H3VSS.4D3VSS.5

DT

CS#P8CAS#P7RAS#N7WE#N3CKEN2CKM8CK#N8UDQS#/NUD8UDQSE7LDQS#/NUH8LDQSJ7UDME3LDM

N9

R78 22

DDR_WE

DDR_CLK

DDR_CS

DDR_CAS

DDR_CKE

DDR_RAS

DDR_CLK_N

BDDR_DQS3

R8122

DDR_DQS3

DDR_DQS37

M3

VSSQ.1G8VSSQ.2J8VSSQ.3D7VSSQ.4J2VSSQ.5E2VSSQ.6L8VSSQ.7L2VSSQ.8E8VSSQ.9

BDDR_DQS1DDR_DQS1

R80 22

DDR_CLK_N

DDR_A5

DDR_A7

DDR_A6

C106

C93

C105

C104

VDDQ.1F3VDDQ.2F7VDDQ.3K1VDDQ.4K3VDDQ.5K7VDDQ.6K9VDDQ.7D9V

DDR_A6

DDR_A5

DDR_A7

3

A2R7A1R3A0R8BA2P1BA1P3BA0P2NC.1

T2

DDR_A1

DDR_A2

DDR_A3

DDR_A4

0.1uF

0.1uF

0.1uF

0.1uF

F9

H9

F1

DDQ.8

VDDQ.9

VDDQ.10

3

A2R7A1R3A0R8BA2P1BA1P3BA0P2NC.1

T2

DDR_A4

DDR_A3

DDR_A2

DDR_A1

NC.2

NC.3

NC.4

NC.5D2NC.6V8NC.7A9NC.8A8NC.9A2NC.10A1NC.11H2RFU.1V3RFU.2V7O

AA9

AA8

AA2

AA1

DDR_A0

DDR_BS00

DDR_BS01

DDR_BS02

DDR_D5

DDR_D7

DDR_D8

DDR_D13

DDR_D15

BDDR_D[0:15]

VREF_STL

M2

AA9

678

123

RN23 RPACK4-22

BDDR_D13

BDDR_D15

BDDR_D8BDDR_D13

BDDR_D15

BDDR_D14

DQ15E9DQ14E1DQ13G9DQ12G1DQ11G3DQ10

NC.2

NC.3

NC.4

AA8

AA2

AA1

DDR_D10

678

4 5

4 5

RN25 RPAC K4-22

BDDR_D7

BDDR_D5

BDDR_D10

BDDR_D10

BDDR_D12

BDDR_D11 DDR_D28

G7

NC.5D2NC.6V8NC.7A9NC.8A8NC.9A2NC.10A1NC.11H2RFU.1V3RFU.2V7O

C112

0.1uF

VREF_STL

VDDLM1VREF

DDR_A0

DDR_BS02

DDR_BS01

DDR_BS00

A12V2A11U7A10R2A9U3A8U8A7U2A6T7A5T3A4T8A

DR_A9

DDR_A8

D

DDR_A10

DDR_A11

DDR_A12

3

4

22uF

C102

+

C97

0.1uF

C96

0.1uF

C95

0.1uF

C94

0.1uF

V1

U16

VDD.1M9VDD.2H1VDD.3R9VDD.4D1VDD.5

A12V2A11U7A10R2A9U3A8U8A7U2A6T7A5T3A4T8A

DR_A9
D

DDR_A8

DDR_A12

DDR_A11

DDR_A10

5

DDR_CS7

DDR_WE7

DDR_CLK7

DDR_CKE7

DDR_RAS7

DDR_BS027

DDR_BS017

DDR_A[0:12]7

D D

DDR_BS007

C C

DDR_CAS7

DDR_DQS17

DDR_DQS07

DDR_CLK_N7

B B

DDR_DQM17

DDR_DQM07

A A

A-15

Spectrum Digital, Inc

A

Revision:

MEM.EM_D[7:0] 16,17

1

C116

VCC_3V3

MEM.EM_A[20:13] 16,17

MEM.EM_A19

MEM.EM_A17

MEM.EM_A20

MEM.EM_A18

1234567

0.1uF

EM.EM_D4

MEM.EM_D5

M

MEM.EM_D2

MEM.EM_D3

16

1A42A73A94

VCC

U20

1B122B153B1114B1141

.CI5

B.CI4

B

B.CI2

B.CI3

VCC_3V3

R91

10K

MEM.EM_A14

MEM.EM_A13

MEM.EM_A16

MEM.EM_A15

8

12

A

GND

B2

2B263B2104B2

OE15S

74CBTLV3257PWR

1

3

13

COUT4

COUT5

COUT3

COUT2

COUT56,30

COUT46,30

COUT26,30

COUT36,30

BMEM_EMD7-0_SELECT

SRAM_CEn 16

NAND_CEn 16

FLASH_CEn 17

DC_EM_CS2n 30

246

8

JP2

CONN 4x2

135

7

SPECTRUM DIGITAL INCORPORATED

EM_CS2 SELECT

PIN 1 TO 2 FLASH

PIN 5 TO 6 SRAM

PIN 3 TO 4 NAND FLASH

89

10111213141516

RN31 RPACK8-47K

EM_CS26

C115

0.1uF

MEM.EM_D1

MEM.EM_D0CO UT7

MEM.EM_D7

MEM.EM_D6

VCC_3V3

16

1A42A73A94A

VCC

U19

1B122B153B1114B1141B232B263B2104B2

2

3

C114

CC_3V3
V

4

0.1uF

U18

.CI1

B.CI6

B.CI0

B

VCC_3V3

EM.EM_A14

M

MEM.EM_A13

MEM.EM_A15

MEM.EM_A21

24

1B121B251B361B491B5102B1152B2162B3192B4202B5

VCC

1A131A241A371A481A5112A1142A2172A3182A4212A5

.CI6

B.CI5

B

B.CI7

B.CI7

MEM.EM_A16

B.CI4

8

12

GND

OE

S

74CBTLV3257PWR

5

1

1

13

OUT0

COUT1

C

COUT6

BMEM_EMD7-0_SELECT

COUT16,30

COUT06,30

COUT76,30

COUT66,30

R90

R248

10K

NO-POP

MEM_EMD7-0_ENABLEn30

EM.EM_A20
M

MEM.EM_A19

MEM.EM_A18

MEM.EM_A17

12

23

MEM.EM_A21 17

EM.EM_A21

M

GND

OE
1

1

3

1

22

.CI0

B.CI3

B

B.CI1

B.CI2

R89 47K

2OE

SN74CBTLV3384PW

TMS320DM6437 Evaluation Module

Title:

PIN 7 TO 8 DAUGHTERCARD

Sheet of

1

509102-0001

DWG NO

EMIF Muxing

Wednesday, December 06, 2006 15 34

B
Size:

Date:

Page Contents:

2

3

4

4

B.CI422,30

B.CI522,30

B.CI622,30

B.CI722,30

B.CI322,30

B.CI022,30

B.CI122,30

B.CI222,30

C_FIELD6,30

U71

53

1

2

SN74LVC1G32

C196

0.1uF

VCC_3V3

R88

5

NO-POP

VCC_3V3

D D

10K

R247

CI_EMA_E NABLEn30

C195

.1uF

4

5

VCC_3V3

C C

2

1

R451 0

SN74AHC1G14DCKRG4

3

U69

MEM_EMD7-0_SELECT13

B B

A A

5

A-16 DM6437 EVM Technical Reference

Spectrum Digital, Inc

B

Revision:

Sheet o f

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

NAND-Flash/SRAM

SPECTRUM DIGITAL INCORPORATED

C123

.1uF

VCC_3V3

2

C119

C118

CC_3V3
V

3

4

MEM.EM_D[7:0] 15,17MEM.EM_A[18:13]15,17

R69

VCC_3V3

10K

EM.EM_D5

MEM.EM_D3

MEM.EM_D2

MEM.EM_D1

MEM.EM_D7

MEM.EM_D0

MEM.EM_D6

M

E1
D6

R750

DQ0B6DQ1C5DQ2C6DQ3D5DQ4E5DQ5F5DQ6F6D

VDD.2
VDD.1

A20

H6

G2

R94NO-POP

MEM.EM_A17

MEM.EM_A16

MEM.EM_A18

MEM.EM_D4

G6

Q7

12
A

A13G4A14F3A15F4A16E4A17D3A18H1A19

G3

EM.EM_A13

MEM.EM_A15

MEM.EM_A14

M

B.EM_A1117,22,30

B.EM_A1217,22,30

VCC_3V3

0.1uF

0.1uF

U22

EM_BA06,10,17,30

R107

F2

E2

G1

NC.2B1NC.3C1NC.7C2NC.8D2NC.9

NC.4F1NC.5

NC.10

H5

EM_A036,17,30

EM_A046,10,17,30

B.EM_A0617,22,30

B.EM_A0717,22,30

B.EM_A0817,22,30

B.EM_A0917,22,30

B.EM_A1017,22,30

B.EM_A0517,22,30

EM_A01_ALE6,17,30

EM_A02_CLE6,17,30

R93

10K

0

R70

NO-POP

E3

B2

NC.1A1NC.6

NC.11

IS62WV102416BLL-10MLI

GND.2

E6

GND.1

D1

A0A3A1A4A2A5A3B3A4B4A5C3A6C4A7D4A8H2A9H3A10H4A11

CEB5WEG5OE

CE2

A2

A6

R95

0

VCC_3V3

EM_BA16,10,17,30

EM_A006,10,17,30

READ_OE6,17,30

WRITE_WE6,17,30

SRAM_CEn15

MEM.EM_D6

MEM.EM_D5

MEM.EM_D4

MEM.EM_D7

H5

J8

H7

J5

NC.J3J3NC.J5

NAND512W3A2BZA6EU23

J6

G7

I/O4K6I/O5J7I/O6K7I/O7

NC.H3H3NC.H5

NC.H6H6NC.H7

NC.G7

NC.D3D3NC.D6D6NC.D7D7NC.D8D8NC.E3E3GND1C5R/#BC8#RED4#CEC6NC.E4E4NC.E5E5VCC1H8GND2K3NC.E6E6NC.E7E7CLED5ALEC4#WEC7#WPC3NC.E8E8NC.F3F3NC.F4F4NC.F5F5NC.F6

R98 0

R97

10K

VCC_3V3

R96

10K

VCC_3V3

VCC_3V3

READ_OE6,17,30

WAIT_BSYn6,30

NAND_CEn15

MEM.EM_D0

MEM.EM_D2

MEM.EM_D3

MEM.EM_D1

R99 NO-POP

F8

K5

K8

G6

VCC2

GND3

G3

G8

I/O0H4I/O1J4I/O2K4I/O3

PRE

NC.F7F7NC.F8

NC.G3

NC.G4G4NC.G5G5NC.G6

F6

WRITE_WE6,17,30

EM_A01_ALE6,17,30

EM_A02_CLE6,17,30

C122

.1uF

R100

10K

R101

NO-POP

VCC_3V3

Wednesday, December 06, 2006 16 34

B
Size:

Date:

Title:

Page Contents:

CE DON'T CARE DEVICE

NC.M10

M10

NC.M9

M9

NC.L10

L10

NC.L9

L9

NC.M2

M2

NC.M1

M1

NC.L2

L2

NC.L1

L1

NC.B10

B10

NC.B9

B9

NC.A10

A10

NC.A9

A9

NC.B1

B1

NC.A2

A2

NC.A1

A1

1

2

3

4

5

D D

C C

B B

A A

A-17

5

Spectrum Digital, Inc

1

R102

10K

VCC_3V3

MEM.EM_D[7:0] 15,16

2

EM_BA0 6,10,16,30

0

MEM.EM_D3

MEM.EM_D2

MEM.EM_D1

MEM.EM_D7

MEM.EM_D0

MEM.EM_D6

MEM.EM_D5

MEM.EM_D4

G5

G7

F6

DQ10F4DQ11G4DQ12F5DQ13G6DQ14

B.EM_A0816, 22,30

B.EM_A0916, 22,30

A4

VCC

RY/BY

DQ15/A-1

18

A17B3A

A19D5A20D4A21C5A22B8A23

E7

C4

EM.EM_A15

MEM.EM_A13

MEM.EM_A14

M

MEM.EM_A16

MEM.EM_A17

MEM.EM_A18

B.EM_A1016, 22,30

B.EM_A1116, 22,30

B.EM_A1216, 22,30

E3

Q0
D

DQ1H3DQ2E4DQ3H4DQ4H5DQ5E5DQ6H6DQ7E6DQ8F3DQ9

3

0

24

A

A1D2A2C2A3A2A4B2A5D3A6C3A7A3A8B6A9A6A10C6A11D6A12B7A13A7A14C7A15D7A16

U

E2

M_BA1

EM_A006,10,16,30

E

EM_A01_ALE6,16,30

EM_A02_CLE6,16,30

,10,16,30
6

4

G3

EM_A036,16,30

EM_A046,10,16,30

B.EM_A0616, 22,30

B.EM_A0716, 22,30

B.EM_A0516, 22,30

VCC_3V3

MEM.EM_A19

F1

D8

VIO.1

MEM.EM_A20

C124

H7

VIO.2

VSS.1H2VSS.2

NC/A24

F8

C8

R153 NO-POP

R154 0

EM_BA06,10,16,30

MEM.EM_A2115

0.1uF

C125

0.1uF

VCC_3V3

C183

0.1uF

E1

E8

NC1A1NC2B1NC3C1NC4D1NC5

VSS.3

BYTEF7CEF2OEG2RESET

READ_OE6,16,30

WRITE_WE6,16,30

NC6G1NC7H1NC8A8NC9

B5WEA5

SYS_RESETn3,19,26,28,30,33

A

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

NOR-Flash/EEPROM

SPECTRUM DIGITAL INCORPORATED

C366

0.1uF

VCC_3V3

R309

10K

G8

H8

NC10

S29GL256N11FFI010

WP/ACC

B4

VCC_3V3

R106

NO-POP

R104

10K

VCC_3V3

Internal pull-downs

4A01A12A23

7

WP

VSS

U25

C126

0.1uF

CAT24C256

VCC

SCL6SDA

8

5

I2C_CLK5,12,13,26,28,31

I2C_DATA5,12,13,26,28,31

8

7

VCC

U65

CS

2

1

FSX05,31

VCC_3V3

Wednesday, December 06, 2006 17 34

B
Size:

Date:

Title:

Page Contents:

2

DX0 5,26,31

CLKX0 5,26,31

5

6

SI

SCK

HOLD

WP3SO

4

DR05,26,31

R310 10K

3

GND

SOCKETED_SPI_EEPROM

4

R71

R105

NO-POP

VCC_3V3

R103

10K

5

MEM.EM_A[20:13]15,16

D D

10K

5

FLASH_CEn15

C C

B B

A A

A-18 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

ENET Muxing

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 18 34

B
Size:

Date:

Title:

Page Contents:

1

2

C129

C127

0.1uF

EPHY.TXCLK 19

EPHY.TXD0 19

EPHY.TXD1 19

16

VCC

26
U

1B122B153B1114B1141B232B263B2104B2

B.TXCLK23,31

RN35

RPACK4-100K

1A42A73A94A

B.TXD023,31

B.TXD123,31

4 5
3
2
1

EPHY.TX_EN 19

12

8

GND

OE15S

74CBTLV3257PWR

1

13

B.TXEN23,31

C128

0.1uF

CC_3V3
V

U27

3

4

EPHY.TXD2 19

EPHY.TXD3 19

EPHY.RX_CLK 19

24

1B121B251B361B491B5102B1152B2162B3192B4202B5

VCC

1A131A241A371A481A5112A1142A2172A3182A4212A5

B.TXD323,31

B.TXD223,31

B.RXCLK23,31

VCC_3V3

EPHY.RXD2 19

EPHY.RXD3 19

EPHY.COL 19

EPHY.CRS 19

EPHY.MDIO 19

EPHY.MDC 19

23

12

ND
G

OE

1OE12

SN74CBTLV3384PW

22

13

B.COL23,31

B.CRS23,31

B.RXD223,31

B.RXD323,31

B.MDC23,31

B.MDIO23,31

C175

0.1uF

4

U14

SN74LVC1G32

53

1

2

VCC_3V3

6
7
8

0.1uF

EPHY.RXD0 19

EPHY.RXD1 19

EPHY.RX_DV 19

EPHY.RX_ER 19

VCC_3V3

16

12

1A42A73A94A

VCC

U28

1B122B153B1114B1141B232B263B2104B2

13

B.RXD023,31

B.RXD123,31

B.RXDV23,31

B.RXER23,31

4 5
3

6

2

7

1

8

RN36

RPACK4-100K

2

8

GND

OE15S

74CBTLV3257PWR

3

1

4

R358

1K

5

D D

C C

VCC_3V3

R326

R246

NO-POP

10K

ENET_ENABLEn31

B B

A A

A-19

5

Spectrum Digital, Inc

1

SILKSCREEN:

ETHERNET

P3 RJ45 HALO HFJ11-2450E-L21

LED2-12LED2+11LED1-10LED1+

VDD_3V3A

EPHY.LED0

C134

0.1uF

2

C137

C132

4.7uF

C136

C131

0.1uF

3

VDD_1V8RX

VDD_3V3A

PHY_1V8

C133

4.7uF

+

C130

0.1uF

NC17GND8TXD+1TXD-2RXD+3RXD-6RXD-CT

9

PHY.LED2
E

R110

49.9

R109

49.9

4.7uF

0.1uF

VDD_1V8PLL

TXD-CT

4

C141

4.7uF

C140

0.1uF

VDDPLL

47

VDDRCV

38

VDDRX

31

VDDC1

13

VDDIO2

24

VDDIO1

7

U30

S0

14

S1

13

5

C142

40

41

TX-

TX+

TX_CLK/REF_CLK15TXD017TXD118TXD219TXD320TX_EN16TX_ER

A

Revision:

GND_E_ENET

GND_E_ENET

C143

0.1uF

VDD_3V3A

GND_E_ENET

1000pF 2kV

R117

49.9

R115

49.9

R114

NO_POP

33

RX+

43

32

34

RX-

NC142NC2

FXSD/FXEN

14

VCC_3V3

PHY.LED0

E

R124 6.65K

R127 330

27

26

37

REXT

LED0/TEST

COL/RMII21C

22

R129

NO-POP

R130

EPHY.LED2

R128 330

28

29

ED1/SPD100
L

LED2/DUPLEX

RS/RMII_BTB

RXD0/PHYAD46RXD1/PHYAD35RXD2/PHYAD24RXD3/PHYAD13RX_DV/CRSDV/PCS_LPBK9RX_ER/ISO11MDC2MDIO1INT#/PHYAD0

L56

L55

BLM21PG221SN1D

BLM21PG221SN1D

NO-POP

VCC_3V3

C199

.1uF

VCC_3V3

R131 10K

U72

VCC4OUT

1

L8 BLM21PG221SN1D

VCC_3V3 VDD_3V3A

R134

NO-POP

R137

NO-POP

R249 22

3

25MHz

GND2EN

SPECTRUM DIGITAL INCORPORATED

PHY_1V8

45XI46

XO

KS8001L

GND7

44

GND6

39

GND5

LED3/NWAYEN

RX_CLK

10

25

48

36

GND4

35

GND3

23

GND2

12

GND1

8

PD#

RESET#

30

R136

NO-POP

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

ENET

Wednesday, December 06, 2006 19 34

B
Size:

Date:

Title:

Page Contents:

VDD_1V8PLL

VDD_1V8RX

2

L9 BLM21PG221SN1D

L11 BLM21PG221SN1D

3

C139

4.7uF

VCC_3V3

4

5

C138

0.1uF

D D

R111 22

EPHY.TXD218

EPHY.TXD318

EPHY.TXD018

EPHY.TXD118

EPHY.TXCLK18

R120 NO-POP

R116 NO-POP

R118 NO-POP

R132 10

TP12

R123 NO-POP

R121 NO-POP

R126 NO-POP

R119 NO-POP

R113

NO-POP

R112

NO-POP

EPHY.TX_EN18

C C

1 16

2 15

3 144 13

5 12

RN32 RPACK8-10

PHY.CRS

EPHY.RXD018

EPHY.RXD118

EPHY.RXD218

EPHY.COL18

E
8

1

EPHY.MDC18

EPHY.RX_CLK18

1.5K

R133

VCC_3V3

6 11

7 10

8 9

EPHY.RXD318

EPHY.RX_DV18

EPHY.RX_ER18

B B

R135

NO-POP

TP-30

EPHY.MDIO18

SYS_RESETn3,17,26,28,30,33

VCC_3V3

10K

R192

A A

4

5

A-20 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

GND_E_CAN

DB9-FEMALE

1

2

594837261

TP13

TP-60

D1

PGB0010603_NO-POP

P7

A B

GND_E_CAN

TP14

TP-60

R141

120

C151

R140

B_CANH

B_CANL

D2

4700pF_NO-POP

0

PGB0010603_NO-POP

Texas Instru me nts

Sheet of

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

CAN

Wednesday, December 06, 2006 20 34

B
Size:

Date:

Title:

Page Contents:

1

2

C148

100pF_NO-POP

2

T1

3

R138 10K

3

VCC_3V3

4

VCC_3V3

C147

R343 0

7

8

NC.2

U31

D1GND2VCC3R

R139

10K

CAN_D

14

1B32B63B84B

VCC

0.1uF

U32

1A22A53A94A

12

TINP1L5,21,31

TOUT1L5,21,31

5

C149

100pF_NO-POP

1

4

ACT45B-510-2P_NO-POP

R342 0

R360

0

6

5

NC.1

CANL

CANH

4

R256 33

AN_R
C

11

C150

0.1uF

SN65HVD235DRG4

R361 NO-POP

VCC_3V3

C146

0.1uF

R362 0

R363 N O-POP

VCC_3V3

VCC_5V

7

3

4

GND

OE

1OE12OE43

4OE

3

10

1

SN74CBTLV3125 PWRG4

R188

R328

NO-POP

VCC_3V3

10K

5

CAN_ENABLEn31

D D

C C

B B

A A

A-21

Spectrum Digital, Inc

A

Revision:

Sheet o f

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

RS232

Wednesday, December 06, 2006 21 34

B
Size:

Date:

Title:

Page Contents:

2

3

C156

10pF

C155

10pF

T_OUT

T_IN11R_OUT

UART_RXD

12

1A42A73A94A

P8

A B

GND_E_RS232GND_E_RS232

L57

C158

10pF

GND_E_RS232

C162

L13 1uH

GND_E_RS232

8

9

R257 33

GND_E_RS232

C157

10pF

C160

1uF

10

5

R_IN

C2+

INVALID

C1+2C1-

EN

1

R145 0

C159

1uF

1uF

C161

1uF

7

6

3

V-

V+

C2-

MAX3221CPWRG4

GND

4

14

BLM21PG221SN1D

GND_E_CAN

GND_E_RS232

L58

BLM21PG221SN1D

SPECTRUM DIGITAL INCORPORATED

8

GND

OE15S

74CBTLV3257PWR

1

13

DB9-MALE

1

GND_E_RS232

594837261

R143

10K

2

R142

10K

L12 1uH

16

12

13

FORCEON

FORCEOFF

U34

VCC

15

C154

47uF

3

+

C153

1uF

UART_TXD

VCC_3V3 VCC_3V3VCC_3V3 VCC_3V3

16

C152

.1uF

VCC

U33

1B122B153B1114B1141B232B263B2104B2

4

UTXD05,31

URXD05,31

TINP1L5,20,31

TOUT1L5,20,31

R144

VCC_3V3

5

D D

C C

VCC_3V3

R146

NO-POP

R147

10K

R187

10K

NO-POP

RS232_ENABLEn31

B B

A A

4

5

A-22 DM6437 EVM Technical Reference

Spectrum Digital, Inc

B

Revision:

Sheet o f

1

2

C186

0.1uF

3

PCI_P_AD[31:0]23,24

PIDRDYn 6

AD18 6

AD16 6

AD17 6

PFRAMEn 6

PCBE2n 6

EM_A06 6

EM_A07 6

EM_A08 6

EM_A10 6

PCI_DETECTn23

PCI_DETECTn

1

S

VCC.1

17

U52

EM_A05 6

EM_A09 6

509102-0001

9

10

B

B

A

PCI_S_AD19

PCI_S_AD17

PCI_S_AD16

PCI_S_AD18

PCI_S_AD20

PCI_S_AD22

PCI_S_AD21

PCI_S_AD23

2

116A137A158A189A21

25

27

A

1A

2A43A64A95

1B1

2B1523B1

54

50

PCI_P_IRDYn24

PCI_P_C/BEn224

PCI_P_FRAMEn24

CI4 6

PCICLK 6

11A

10A2312A

NC.13NC.25NC.37NC.410NC.512NC.614NC.716NC.8

B1

4B1475

6B1437B1418B13910B1

45

PCI_P_AD17

PCI_P_AD18

PCI_P_AD19

PCI_P_AD16

CI1 6

AD30 6

CI3 6

CI5 6

1B2

9B1

2B2513B2484B2465B2446B2427B2408B23711B23112B2

11B13212B1

53

36

34

30

R3310

R3290

R3080

R3320

R30722

R3470

PCI_P_IDSEL24

PCI_P_AD20

PCI_P_AD21

PCI_P_AD22

PCI_P_AD23

AD26 6

AD28 6

CI7 6

CI6 6

EM_A12 6

EM_A11 6

VLYNQ_RXD225,32

VLYNQ_RXD325,32

VLYNQ_TXD025,32

VLYNQ_RXD125,32

VLYNQ_RXD025,32

VLYNQ_SCRUN25,32

56

55

28

20

22

NC.9

NC.14

NC.13

NC.1024NC.1126NC.12

9B23510B2

29

33

12

16

14

15

13

11

B

B

B

B

B

B

A

A

A

A

A

A

5

1

3

2

4

6

RN3E RPACK8-22

RN3A RPACK8-22

RN3C RPACK8-22

RN3B RPACK8-22

RN3D RPACK8-22

RN3F RPACK8-22

B.EM_A0516,17,30

B.EM_A0616,17,30

B.EM_A0716,17,30

B.EM_A0816,17,30

B.EM_A1016,17,30

B.EM_A0916,17,30

A

8

7

RN3H RPACK8-22

RN3G RPACK8-22

SN74CBT16292DGGR

GND.1

8

GND.2

19

GND.3

38

GND.4

49

C363

R339

R338

NO-POP

NO-POP

NO-POP

C362

NO-POP

C364

5.6pF

C178

0.1uF

PCI4.1V

CI2 6

PCI_S_RSTn

PCI_S_PINTAn

TMS320DM6437 Evaluation Module

DWG NO

PCI-Switches

SPECTRUM DIGITAL INCORPORATED

C120

0.1uF

5

R170

10K

VCC_3V3 VCC_3V3

Wednesday, December 06, 2006 22 34

B
Size:

Date:

Title:

Page Contents:

RESETn 3,4,30

R177 NO-POP

NO-POP

4

U36

SN74LVC1G07

3

2

1

1

2

3

16

PCI_S_CLKOUT0

CI_S_GNTn

PCI_S_AD31

P

PCI_S_REQn0

R158 0

C184

4

PCI4.1V23

5

PCI_DETECTn

0.1uF

1

2

95A116A137A158A189A21

S

1A

2A43A64

VCC.1

17

U51

1B1

2B1523B1

54

50

47

PCI_P_AD31

PCI_P_CLK24

PCI_P_GNT n24

PCI_P_R EQn24

PCI_P_AD[31:0]23,24

D D

PCI_S_AD30

PCI_S_AD29

A

B1

4

5B1456B1437B1418B13910B1

PCI_P_AD30

PCI_P_AD29

PCI_S_C/BEn3

PCI_S_AD25

PCI_S_AD26

PCI_S_AD27

PCI_S_AD28

PCI_S_AD24

25

27

11A

10A2312A

NC.13NC.25NC.37NC.410NC.512NC.614NC.716NC.8

1B2

9B1

2B2513B2484B2465B2446B2427B2408B23711B23112B2

11B13212B1

53

36

34

30

PCI_P_AD28

R33322

PCI_P_AD27

PCI_P_AD26

PCI_P_AD25

PCI_P_AD24

1234567

PCI_P_C/BEn324

B.CI115,30

B.CI415,30

VLYNQ_CLOCK25,32

C C

56

55

28

20

22

NC.9

NC.1024NC.1126NC.12

SN74CBT16292 DGGR

NC.14

NC.13

GND.1

8

GND.2

19

GND.3

38

GND.4

49

9B23510B2

29

33

10111213141516

8 9

RN5 RPACK8-33

B.CI315,30

B.CI715,30

B.CI615,30

B.CI515,30

B.EM_A1216,17,30

B.EM_A1116,17,30

C361

5.6pF

0

R337

PCI4.1V23

VCC_3V3

PCI_P_PINTAn

R171 0

B.CI015,30

PCI_P_PINTAn24

R181 0

VCC_3V3

B B

U12

C144

0.1uF

4

1A

VCC

1B1

2

4

U40

53

1

PCI_P_RSTn24 CI0 6

8

7

12

2A

3A94A

GND

4B1

3B1

4B213S

OE

3B2101B232B152B2

1

6

11

SN74LVC1G08

14

NO-POP

SN74CBT3257PW

15

PCI_DETECTn

R172 0

2

B.CI215,30

RESET_OUTn3,31

A A

A-23

4

5

Spectrum Digital, Inc

A

Revision:

GIO002 5

GIO001 5

GIO000 5

MDC 6

RXER 6

RXD0 6

RXCLK 6

RXD1 6

RXD3 6

MDIO 6

GIO003 5

PCI_DETECTn

1

S

VCC.1

TXEN 6

PCI_S_AD10

PCI_S_AD8

PCI_S_AD9

2

1A

2A43A64A95A116A137A158A189A

1B1

2B1523B1

54

50

PCI_P_AD9

PCI_P_AD8

PCI_P_AD10

TXD0 6

TXD1 6

RXDV 6

TXCLK 6

RXD2 6

PCI_S_AD7

PCI_S_AD5

PCI_S_AD6

PCI_S_C/BEn0

4B1475B1456B1437B1418B13910B1

PCI_P_C/BEn024

PCI_P_AD5

PCI_P_AD7

PCI_P_AD6

COL 6

CRS 6

TXD2 6

TXD3 6

CI_S_AD4

PCI_S_AD3

P

PCI_S_AD0

PCI_S_AD1

PCI_S_AD2

56

21

25

27

11A

10A2312A

NC.13NC.25NC.37NC.410NC.512NC.614NC.716NC.8

1B2

9B1

2B2513B2484B2465B2446B2427B2408B23711B23112B2

11B13212B1

53

36

34

30

B.RXD218,31

B.RXD018,31

B.RXER18,31

B.RXCLK18,31

CI_P_AD4

PCI_P_AD3

PCI_P_AD0

PCI_P_AD1

PCI_P_AD2

P

PTRDYn 6

PDEVSELn 6

PPERn 6

55

24

28

20

22

C.10

NC.9

N

0B2

9B2351

33

B.MDC18,31

B.RXD118,31

B.RXD318,31

B.MDIO18,31

B.GP[02]31

B.GP[03]31

SN74CBT162 92DGGR

NC.14

NC.13

NC.1126NC.12

GND.1

8

GND.2

19

GND.3

38

GND.4

49

29

B.GP[01]31

B.GP[00]31

SPECTRUM DIGITAL INCORPORATED

PCIEN 3

1

PCI_DETECTn22

17

U54

2

3

PCI4.1V

C176

0.1uF

PCI4.1V 22

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

PCI-Muxing

Wednesday, December 06, 2006 23 34

B
Size:

Date:

Title:

Page Contents:

2

3

PCI_S_STOPn

PCI_S_PAR

PCI_S_AD13

PCI_S_AD14

PCI_S_AD15

PCI_S_C/BEn1

PCI_S_AD11

PCI_S_SERRn

CI_DETECTn
P

PCI4.1V

C174

4

5

0.1uF

PCI4.1V

D5

LM4040DCIM3-4.1

R68 1.5K

VCC_5V

PCI_P_AD[31:0]22,24

1

2

S

A

1

2A43A64A95A116A137A158A189A

VCC.1

17

B1

U53

1

2B1523B1

54

50

2 1

PCI_P_AD13

PCI_P_AD11

PCI_P_AD12 PCI_S_AD12

D D

4B1475B1456B1437B1418B13910B1

PCI_P_AD14

PCI_P_AD15

PCI_P_C/BEn124

25

27

21

11A

10A2312A

NC.13NC.25NC.37NC.410NC.512NC.614NC.716NC.8

1B2

9B1

2B2513B2484B2465B2446B2427B2408B23711B2311

11B13212B1

53

36

34

30

B.TXD018,31

B.TXD118,31

B.TXEN18,31

B.RXDV18,31

PCI_P_PAR24

B.TXCLK18,31

PCI_P_STOPn24

PCI_P_PERRn24

PCI_P_TRDYn24

PCI_P_SERRn24

PCI_P_DEVSELn24

C C

56

55

28

20

22

C.12

NC.9

NC.1024NC.1126N

9B23510B2

33

R3350

R3340

B.COL18,31

B.CRS18,31

B.TXD218,31

B.TXD318,31

VLYNQ_TXD325,32

SN74CBT16292DGGR

NC.14

NC.13

GND.1

8

GND.2

19

GND.3

38

GND.4

49

2B2

29

R33622

C365

5.6pF

VLYNQ_TXD125,32

VLYNQ_TXD225,32

B B

PCI_DETECTn 22

C121

0.1uF

4

U39

SN74AHC1G14DCKRG4

3

PCI_DETECTn

R315

5

VCC_3V3

2

1

0

PCI_PLUGn24

A A

4

5

A-24 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

PCI-Connector

SPECTRUM DIGITAL INCORPORATED

Length to Cap no greater that 0.25 inches

Any number of pin shares as long as does not exceed length

Trace size to cap 20 mil

C182

0.1uF

2

Length to Cap no greate r that 0.25 inches

Any number of pin shares as long as does not exceed length

Trace size to cap 20 mil

C179

0.1uF

C172

0.1uF

PCI_VIO

PCIVCC_3V3

A53,B54

Length to Cap no g reater that 0.25 inches

Any number of pin shares as long as does not exceed lengt h

Trace size to cap 20 mil

C181

0.1uF

C180

0.1uF

A21,A27,B25,B31 A 33,A39,B41,B43

C203

0.1uF

VCC_5V

C204

33uF

+

Wednesday, December 06, 2006 24 34

B
Size:

Date:

Title:

Page Contents:

1

2

3

PCI_P_AD[31:0] 22,23

PCIVCC_3V3

4

PCI_PLUGn 23

VCC_5V

PCI_VIO

A3

A5

A4

A1

A2

MS

TDI

+5V

T

+12V

TRST

R178 0

P4

ND

-12VB1TCKB2G

TDOB4+5VB5+5VB6INTBB7INTDB8PRSNT1B9Rsvd.2

B3

PCI_VIO

R164 NO-POP

5

R163 10K

CC_3V3
V

VCC_5V

PCIVCC_3V3

PCI_VIO

B19,B59 A1 0,A16,B19 A59,B59

A10,A16,A59

PCI_P_RSTn 22

PCI_P_PINTAn 22

A8

A9

A6

A7

+5V

INTA

INTC

Rsvd.0

R179 0

PCI_P_GNTn 22

A11

A15

A17

A18

A14

A10

A16

RST

GNT

Key.1

Key.2

+V I/O

+V I/O

Rsvd.1

3.3Vaux

PRSNT2

Key.5

Key.6

Rsvd.3

GND

CLK

GND

B11

B10

B18

B14

B15

B16

B17

R180 0

PCI_P_CLK22

PCIVCC_3V3

B25,B31,B36,B41,B43,B54

A21,A27,A33,A39,A45,A53

PCI_P_FRAMEn 22

PCI_P_TRDYn 23

PCI_P_STOPn 23

PCI_P_PAR 23

PCI_P_AD16

PCI_P_AD18

PCI_P_AD20

PCI_P_AD22

PCI_P_AD24

PCI_P_AD26

PCI_P_AD28

PCI_P_AD30PCI_P_AD31

PCI_P_IDSEL 22

A20

A22

A23

A25

A26

A28

A29

A31

A21

A19

A24

PME

GND

AD30

AD28

AD26

+3.3V

REQ

+V I/O

AD31

AD29

GND

AD27

B19

B20

B21

B22

B23

B24

PCI_P_REQn22

PCI_P_AD29

PCI_P_AD27

PCI_P_AD25

A32

A27

A33

A30

A34

A35

A36

D22

GND

GND

AD24

+3.3V

IDSEL

AD25

+3.3V

C/BE3

AD23

B26

B25

B27

PCI_P_AD23

PCI_P_C/BEn322

GND

A

AD20

AD18

AD16

+3.3V

FRAME

ND
G

AD21

AD19

+3.3V

AD17

C/BE2

GND

IRDY

B28

B33

B35

B29

B30

B31

B32

B34

B36

PCI_P_AD21

PCI_P_AD19

PCI_P_AD17

PCI_P_IRDYn22

PCI_P_C/BEn222

PCI_P_AD15

A44

A39

A40

A37

A38

A41

A42

A43

PAR

SBO

GND

GND

AD15

+3.3V

TRDY

STOP

SDONE

+3.3V

DEVSEL

GND

LOCK

PERR

+3.3V

SERR

+3.3V

C/BE1

B37

B39

B40

B42

B44

B38

B41

B43

PCI_P_PERRn23

PCI_P_C/BEn123

PCI_P_SERRn23

PCI_P_DEVSELn23

PCI_P_C/BEn0 23

PCI_P_AD0

PCI_P_AD2

PCI_P_AD4

PCI_P_AD6

PCI_P_AD11

PCI_P_AD13

PCI_P_AD9

A46

A47

A45

B45

PCI_P_AD14

A53

A48

A52

A49

AD9

GND

AD13

AD11

Key.3

Key.4

+3.3V

C/BE0

AD14

GND

AD12

AD10

M66EN

Key.7

Key.8

AD8

B46

B47

B48

B49

B52

B53

PCI_P_AD12

PCI_P_AD10

PCI_P_AD8

PCI_P_AD7

A61

A62

A56

A60

A54

A55

A57

A58

A59

+5V

AD6

+3.3V

AD7

+3.3V

B54

+5V

AD4

AD2

AD0

GND

+V I/O

REQ64

PCI Connector

AD5

AD3

GND

AD1

+V I/O

ACK64

+5V

+5V

B60

B55

B56

B57

B58

B59

B61

B62

PCI_P_AD5

PCI_P_AD3

PCI_P_AD1

3

4

5

D D

C C

B B

A A

A-25

Spectrum Digital, Inc

1

2

C375

22uF

C384

4.7uF

VCC_3V3VCC_5V

3

VCC_1V8

C374

0.33uF

C383

0.33uF

C373

470pF

C382

470pF

C386

0.33uF

C381

0.33uF

C394

470pF

C380

470pF

C372

22uF

C378

22uF

C392

0.33uF

C377

0.33uF

C385

C371

0.33uF

C405

470pF

C376

470pF

0.33uF

C379

470pF

C393

470pF

C

Revision:

Sheet o f

1

509102-0001

VLYNQ_RESET 12,32

TMS320DM6437 Evaluation Module

DWG NO

BTH_WLAN_CONNECTOR

SPECTRUM DIGITAL INCORPORATED

2

1

3

5

VCC_3V3

U67

4

C171

0.1uF

SN74LVC1G06DBVRG4

R394

NO-POP

CC_3V3
V

R419

1K

CC_1V8
V

VLYNQ_RXD2 22,32

VLYNQ_RXD3 22,32

VLYNQ_TXD2 23,32

VLYNQ_RXD0 22,32

VLYNQ_RXD1 22,32

VLYNQ_TXD0 22,32

VLYNQ_SCRUN 22,32

WLAN_RSTn

VLYNQ_CLOCK 22,32

VLYNQ_TXD1 23,32

VLYNQ_TXD3 23,32

Wednesday, December 06, 2006 25 34

B
Size:

Date:

Title:

Page Contents:

2

3

4

19

28

31

40

63

97

1

103

2

VBAT

5V_97

D1_5V

5V_103

89

111

70

3_3V_70

D3_3V_19

D3_3V_28

D3_3V_31

D3_3V_40

D3_3V_63

D

D3_3V_8888D3_3V_89

Power Supplies

3

18

115

D1_8V

VIOXIO_3V

in the host)
(Do not connect
Debug Signals

4

5

6

26

7

PM_EN

WLAN_/INTR

SLP_CLK_ EN

WLAN_/RESET

OSC32_768KHz

WLAN_ELP_REQ

To_Host_VLYNQ_SDIO_VIO

CTLs
WLAN

mPCI_Host_W LAN_CONNECTOR

5

WLAN_RS232_TXD

WLAN_RS232_RXD

WLAN_UART_TXD

WLAN_UART_RXD

J20

117

118

120

122

D D

BG_I2C_SDA

JTAG_WLAN_TDO

JTAG_WLAN_TRSTN10JTAG_WLAN_TDI11JTAG_WLAN_TMS12JTAG_WLAN_TCK

13

RESERVED_15

DBG_EE_WP

D

DBG_I2C_SCL

DBG_I2C_SA2

8

15

105

107

108

106

GND_9

GND_14

DBG_JTAG_WLAN_3V

GND_20

GND_23

GND_25

DBG_GPIO_3V

RESERVED_55

RESERVED_57

DBG_RS232_3V

9

14

17

20

23

25

39

55

57

27

123

C C

GND_27

38

29

1.8V_BTH_/SHUTDWN

GND_3232GND_3333GND_3434GND_35

109

30

71

104

113

116

1.8V_BTH_/INTR
.8V_BTH_UART_RXD

1.8V_BTH_UART_TXD

1.8V_BTH_UART_RTS

1.8V_BTH_UART_CTS

1

1.8V_BTH_ELP_WKUP

CTLs
BTH

ND_42

GND_37

GND_4141G

GND_4444GND_4545GND_46

35

37

42

46

21

22

73

75

77

1.8V_BTH_PCM_FS

1.8V_BTH_PCM_CLK

1.8V_BTH_PCM_TXD

1.8V_BTH_PCM_RXD

UART

PCM

BTH

BTH

GND_48

GND_50

GND_52

48

50

52

54

36

16

24

WLAN_VLYNQ_TD1/SDIO_D3

WLAN_VLYNQ_CLK/SDIO_CLK

WLAN_VLYNQ_TD0/SDIO_CMD

WLAN_VLYNQ_SCRUN/SDIO_D0

GND_54

GND_56

GND_58

GND_60

GND_62

GND_64

GND_66

GND_6868GND_69

56

58

60

62

64

66

69

B B

98

100

124

43

93

WLAN_VLYNQ_RD0/SDIO_D2

WLAN_VLYNQ_RD1/SDIO_D1

SDIO
VLYNQ

GND_72

GND_74

GND_76

72

74

76

112

WLAN_VLYNQ2_CLK

WLAN_VLYNQ2_TXD0

WLAN_VLYNQ2_TXD1

WLAN_VLYNQ2_SCRUN

VLYNQ2

GND_7878GND_79

GND_81

GND_83

GND_85

GND_87

GND_9090GND_9191GND_92

79

81

83

85

87

92

59

WLAN_VLYNQ2_RXD1

GND_9494GND_9595GND_96

61

65

67

49

51

53

80

47

BT_FREQ

BT_RF_SD

GND_99

96

99

101

82

84

86

BT_PRI_ DATA

BT_PA_ON_OR_RX

WLAN_VLYNQ_TD2

WLAN_VLYNQ_TD3

WLAN_VLYNQ_RD2

WLAN_VLYNQ_RD3

WLAN_VLYNQ2_TD2

WLAN_VLYNQ2_TD3

WLAN_VLYNQ2_RD2

Check your

Layout Lib

GND_101

GND_102

GND_110

GND_114

GND_119

HOLE1

HOLE2

GND_PAD1

GND_PAD2

102

110

114

119

125

126

127

128

A A

121

WLAN_VLYNQ2_RXD0

4

WLAN_VLYNQ2_RD3

5

Check the layout libr ary regarding pins 125-128.

SILKSCREEN: MINI PCI

mPCI_HOST_WLAN_CONNECTOR

A-26 DM6437 EVM Technical Reference

Spectrum Digital, Inc

C

SPECTRUM DIGITAL INCORPORATED

digital GNDs at single

location in the ground

plane

0.1uF

U62

53

Revision:

Sheet o f

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

AIC33

Wednesday, December 06, 2006 26 34

B
Size:

Date:

Title:

Page Contents:

GND_AIC

L16

BLM41P750SPT

SPDIF_OUT 27

R356 33

4

SN74LVC1G32

1

2

C231

0.1uF

VCC_3V3

L19

1

BLM21PG221SN1D

C229

0.1uF

C230

+

10uF

0.1uF

0.1uF

0.1uF

0.1uF

GND_AIC

C233

0.1uF

C232

0.1uF

H1

DRVDD.1C1DRVDD.2

U43

DVDDH9DVSSD9IOVDD

C9

C228

C227

C226

2

0.1uF

0.1uF

10uF

0.1uF

0.1uF

VCC_1V8

C225

C223

C222

+

C221

C220

L18

3

BLM21PG221SN1D

CC_3V3
V

C219

C2

B1

AVDD_ADC

AVSS_ADC.1

A6

GND_AIC

GND_AIC

G2

H2

J1

AVDD_DAC

AVSS_DAC.1

AVSS_ADC.2D2AVSS_DAC.2

LINE1R+B7LINE1R-B6LINE2L+A4LINE2L-B5MICBIAS

LINE1L-A5LINE1L+

R1990

P12

Headphone Out

342

1

GND_AIC

BLM21PG221SN1D

L21

+

C240 33uF,6.3V

D1

E1

HPLOUT

HPLCOM

R2000

20K

R204

R203

20K

BLM21PG221SN1D

L22

+

C243 33uF,6.3V

GND_AIC

J5

J3

F1

F2

J2

J4

G1

HPROUT

DRVSS.1E2DRVSS.2

HPRCOM

A2

A3

EFT_LO+

LEFT_LO-

L

MONO_LO-

MONO_LO+

MIC3RA1LINE2R+B4LINE2R-

MIC3L

RESET

MICDET

8

B3

B2

H

P13

Line Out

342

1

ND_AIC
G

GND_AIC

ND_AIC
G

BLM21PG221SN1D

+

C245

J6

J7

RIGHT_LO+

RIGHT_LO-

MFP0B8MFP1

B9

MPF2A8MCLK

MFP3

A9

TP15

TP-30

J8

J9

GPIO2

GPIO1

BCLK

G8

G9

TP16

TP-30

L23

10UF,6.3V

WCLKF9DOUT

20K

R211

GND_AIC GND_AIC

R210

20K

TP17

TP-30

BLM21PG221SN1D

L24

R212

10UF,6.3V

TP18

+

C247

C8

D8

SCL

DIN

F8

E9

TP-30

SDA

TVL320AIC33IZQE

SELECT

E8

R222

R221

I2C_DATA 5,12,13,17,28,31

I2C_CLK 5,12,13,17,28,31

20K

R217

20K

Isolate analog and

C191

10K

10K

VCC_3V3

1

2

3

R209 10

C235

0.1uF

C241

C236

C224

220pF

GND_AIC

C234

5.6K

R194

4

R193

5.6K

342

1

P10

Line In

5

D D

220pF

R196

5.6K

R195

5.6K

L20

GND_AIC

342

P11

C237

0.1uF

GND_AIC

BLM21PG221SN1D

GND_AIC

1

Mic In

C244

0.1uF

0.1uF

C238

R198

330

R197

47K

C239

0.1uF

GND_AIC

R202

330

0.1uF

10K

R201

GND_AIC

C242

0.1uF

GND_AIC

SYS_RESETn3,17,19,28,30,33

220pF

C C

R182 no-pop

R219 10

R218 10

R215 10

R214 10

R213 10

R216 10

R207 NO-POP

R208 10K

R205 10K

R206 NO-POP

AUDIO_CLK11,31

ALT_AIC33_CLK

B_FSR1_AFSR0

B_CLKX1_ACLKX0

B_CLKR1_ACLKR0

B_FSX1_AFSX0

B_DX1_AXR0[0]

B_DR1_AXR0[1]

VCC_3V3

C246

0.1uF

VCC_3V3

24

1B121B251B361B491B5102B1152B2162B3192B4202B5

VCC

U75

1A131A241A371A481A5112A1142A2172A3182A4212A5

DX15,31

FSX15,31

CLKX15,31

DR0 <--> AFSR0

DX0 <--> AXR0[1]

CLKX0 <--> ACLKR0

CLKR15,31

CLKX1 <--> ACLKX0

FSR1 <--> AXR0[0]

DX1 <--> AFSX0

B B

12

23

1OE12OE

22

13

DR15,31

DX05,17,31

CLKX05,17,31

DR05,17,31

McBSP_ONn13

R20

10K

CC_3V3
V

SPDIF_ONn13

C207

0.1uF

VCC_3V3

14

11

7

1B32B63B84B

GND

VCC

U76

1A22A53A94A

SN74CBTLV3384PW

FSR15,31

McASP_ONn13

GND

1OE12OE43OE104OE

12

13

SN74CBTLV312 5PWRG4

SPDIF_ONn13

McASP_ONn13

McBSP_ONn13

A A

A-27

4

5

Spectrum Digital, Inc

C

Revision:

SILKSCREEN:

SPDIF OUT

RCA JACK

0.1uF

2

J10

1

R225

100

R224 220

C250

0.1uF

42

R226 0

1
3 5

U46

74LVC1G125DCKRG4

1

C249

2

3

VCC_3V3

SILKSCREEN:

SPDIF OUT

P14

2

C253

0.1uF

VCC_3V3

C252

VCC_3V3

MP2

5

MP1

4

GND1VCC

IN

3

TOTX141P

SPECTRUM DIGITAL INCORPORATED

0.1uF

42

R228 0

1
3 5

U49

74LVC1G125DCKRG4

SPDIF_OUT26

PCLK 6

DC3_PCLK 30

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

SPDIF/TVP5146-Switch

Wednesday, December 06, 2006 27 34

B
Size:

Date:

Title:

Page Contents:

2

3

HD 6,30

YI0 6,30

YI1 6,30

C248

0.1uF

4

5

VCC_3V3

D D

24

VCC

U45

TVP5146YIN0

TVP5146YIN[7:0]28

1B121B251B361B491B5102B1152B2162B3192B4202B5

1A131A241A371A481A5112A1142A2172A3182A4212A5

TVP5146YIN1

TVP5146YIN2

VD 6,30

YI2 6,30

YI3 6,30

YI4 6,30

YI5 6,30

YI6 6,30

YI7 6,30

C251

0.1uF

12

23

22

VP5146YIN4

TVP5146YIN3

T

TVP5146YIN5

TVP5146YIN6

TVP5146YIN7

TVP5146_HS28

TVP5146_VS28

C C

VCC_3V3

GND

1OE12OE

SN74CBTLV3 384

13

5

VCC

U48

B B

R348 0

4

3

B

GND

A

OE

2

1

SN74CBTLV1G125

R186

10K

TVP5146_PCLK28

TVP5146_ENABLEn30

A A

4

5

A-28 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

R230

2.2K

R232

NO-POP

3V3D_DEC

1

TVP5146YIN[7:0] 27

R231

Y_9

3V3D_DEC

RN33

RPACK8-33

69

C_1/GPIO

C_0/GPIO70C_2/GPIO66C_4/GPIO

65

C_3/GPIO

64

4.7K

60

58

C_5/GPIO63C_7/GPIO59C

C_6/GPIO

57

C_8/GPIO

VP5146YIN2

TVP5146YIN0

T

TVP5146YIN1

TVP5146YIN3

TVP5146YIN4

TVP5146YIN6

TVP5146YIN5

TVP5146YIN7

2

1 16

2 15

3 14

4 13

5 12

6 11

7 10

3V3D_DEC3V3A_DEC

38

48

61

IOVDD

IOVDD

U50

8 9

31

41

55

67

54

VDD

D

DVDD

DVDD

DVDD

IOVDD

43

46

51

Y_844Y_745Y_6

Y_547Y_450Y_3

Y_252Y_153Y_0

R237

NO-POP

R240

2.2K

3V3D_DEC

TP58

TP-30

TP19

TP-30

R242

2.2K

TVP5146_PCLK 27

TVP5146_HS 27

TVP5146_VS 27

TP20

TP-30

I2C_DATA 5,12,13,17,26,31

I2C_CLK 5,12,13,17,26,31

SYS_RESETn 3,17,19,26,30,33

R234 33

R235 33

R236 33

72

73

_9/GPIO

HS/CS/GPIO

36

34

37

35

29

28

33

40

71

PWDN

RESETB

FID/GPIO

DATACLK

FSS/GPIO

AVID/GPIO

GLCO/I2CA

VS/VBLK/GPIO

68

56

42

32

27

30

62

49

39

SCL

SDA

DGND

DGND

DGND

DGND

DGND

IOGND

IOGND

INTREQ

IOGND

THERMAL_LAND

81

Revision:

Sheet of

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

TVP5146

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 28 34

B
Size:

Date:

Title:

Page Contents:

1

2

H4_A33VDD

CH1_A33VDD4CH2_A33VDD

CH2_A18VDD11A18VDD_REF

CH3_A18VDD

CH3_A33VDD20C

CH4_A18VDD

5

14

21

25

3

4

1V8A_DEC

L26

3V3D_DEC

5

L25

VCC_3V3 VCC_1V8

1V8D_DEC

L28

BLM41P750SPT

3V3A_DEC VCC_1V8

BLM41P750SPT

L27

VCC_3V3

78

1V8A_DEC 1V8D_DEC

BLM41P750SPT

BLM41P750SPT

VI_1_C2VI_1_B1VI_1_A

PLL_A18VDD76CH1_A18VDD

80

12

C259

0.1uF

C258

0.1uF

C255

0.1uF

R229

75

C257

330pF

C254

680pF

L30 2.7uH

GND_DENC GND_DENC GND_DENCGND_DENC

C256

330pF

L29 2.7uH

21

P2749181-1

5 6

3 4

S-VIDEO IN

D D

C C

I_3_B

VI_4_A

VI_3_C18V

VI_3_A

VI_2_C9VI_2_B8VI_2_A

7

GND_DENC GND_DENC

23

17

16

C268

0.1uF

C267

0.1uF

C266

0.1uF

C265

0.1uF

C264

0.1uF

C270

0.1uF

R233

75

C260

0.1uF

C263

330pF

C262

680pF

L32 2.7uH

GND_DENC

L31 2.7uH

C261

330pF

GND_DENC GND_DENC GND_DENC GND_DENC

XTAL2

XTAL1

74

R238

100K

GND_DENCGND_DENCGND_DENCGND_DENCGND_DENC

Y4

14.31818MHz

C26933pF

L34 2.7uH

L33 2.7uH

1

J5

RCA JACK

VIDEO IN

B B

CH1_A33GND

CH2_A33GND

CH2_A18GND

A18GND_REF

CH3_A18GND

CH3_A33GND

CH4_A33GND

CH4_A18GND

AGND

CH1_A18GND

75

10

26

79

R241 0

C27433pF

R239

75

C273

330pF

C272

680pF

C271

330pF

2

GND_DENC GND_DENC GND_DENC GND_DENC GND_DENC

PLL_A18GND

TVP5146M2

3

6

13

15

19

22

24

77

GND_DENC

L15

at a single location in

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

BLM41P750SPT

the ground plane.

GND_DENC

GND_DENC

C291

0.1uF

C290

0.1uF

C289

0.1uF

C288

0.1uF

1V8D_DEC

C287

0.1uF

GND_DENC

C286

0.1uF

C285

0.1uF

C284

0.1uF

3V3A_DEC

A A

Isolate digital and

analog GNDs and connect

C283

C282

C281

C280

C279

C278

1V8A_DEC

C277

C276

C275

3V3D_DEC

A-29

3

4

5

Spectrum Digital, Inc

DAC A

OUTPUT

DAC B

OUTPUT

A

DAC C

OUTPUT

DAC D

OUTPUT

Revision:

1

2

3

J1

NO-POP

C297

10pF

L37 1uH

C296

10pF

R243 75

J2

RCA JACK

10pF

L40 1uH

C300

10pF

GND_DAC GND_ DAC GND_DAC

R245 75

3

J

RCA JACK

GND_DAC

GND_DACGND_DAC

L41 1uH

GND_DACGND_DACGND_DAC

C304

10pF

C303

10pF

R250 75

S-VIDEO OUT

21

P1749181-1

5 6

3 4

J4

RCA JACK

10pF

C308

C307

10pF

L46 1uH

GND_DAC GND_DAC GND_DAC

ND_DAC
G

R255 75

SPECTRUM DIGITAL INCORPORATED

L14

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

Video Out

Wednesday, December 06, 2006 29 34

B
Size:

Date:

Title:

Page Contents:

2

GND_DAC

BLM41P750SPT

3

C403

C401

0.1uF

DAC_3V3

4

DAC_3V3

C293

0.01uF

C292

0.1uF

10uF

+ C294

3V3A_VOUT

5

L35 BLM41P750SPT

VCC_3V3

GND_DAC

GND_DAC

4

2

6

V+

OUT

GND

OPA361AIDCKT

IN+

ENABLE

U103

DAC_3V3

GND_DAC

D D

RSET

1

5

3

R445

0

R444 NO-POP C301

DAC_RBIAS8

DAC_IOUT_A8

C402

0.1uF

AC_3V3
D

GND_DAC

GND_DAC

GND_DAC

4

2

6

V+

OUT

GND

OPA361AIDCKT

IN+

ENABLE

U104

DAC_3V3

C C

RSET

1

5

3

R441

NO-POP

R446 0

DAC_RBIAS8

DAC_IOUT_B8

0.1uF

AC_3V3
D

GND_DAC

ND_DAC
G

GND_DAC

4

2

6

V+

OUT

GND

OPA361AIDCKT

IN+

ENABLE

U105

DAC_3V3

RSET

1

5

3

R443

0

R442 NO-POP

DAC_RBIAS8

DAC_IOUT_C8

B B

C404

0.1uF

DAC_3V3

GND_DAC

GND_DAC

4

2

6

V+

OUT

GND

OPA361AIDCKT

IN+

ENABLE

U106

DAC_3V3

GND_DAC

RSET

1

5

3

R448

0

R447 NO-POP

DAC_RBIAS8

DAC_IOUT_D8

A A

4

GND_DAC

5

A-30 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

VIDEO DC Conn.

SPECTRUM DIGITAL INCORPORATED

B.EM_A09 16,17,22

B.EM_A11 16,17,22

B.EM_A12 16,17,22

2

YI4 6,27

YI6 6,27

YI5 6,27

YI7 6,27

C_FIELD 6,15

B.CI4 15,22

B.CI6 15,22

B.CI5 15,22

B.CI7 15,22

HD 6,27

VSYNC 6

HSYNC 6

YI4_(CCD4)_GP[40]

YI7_(CCD7)_GP[43]

C_FIELD_EM_A[21]_GP[34]

CI4_(CCD12)_EM_A[16]_EM_D[3]_GP[48]

CI6_(CCD14)_EM_A[14]_EM_D[1]_GP[50]

CI5_(CCD13)_EM_A[15]_EM_D[2]_GP[49]

CI7_(CCD15)_EM_A[13]_EM_D[0]_GP[51]CI0_(CCD8)_EM_A[20]_EM_D[07]_GP[44]

HSYNC_EM_CS5n_GP[33]

YI5_(CCD5)_GP[41]

YI6_(CCD6)_GP[42]

VSYNC_EM_CS4n_GP[32]

COUT6 6,15

COUT5 6,15

COUT4 6,15

COUT7 6,15

YOUT6 6,10

YOUT4_FASTBOOT 6,10

YOUT5 6,10

YOUT7 6

COUT6_EM_D[6]_GP[20]

COUT5_EM_D[5]_GP[19]

COUT4_EM_D[4]_GP[18]

COUT7_EM_D[7]_GP[21]

YOUT6_GP[28]

YOUT4_G P[26]_FAST BOOT

YOUT5_GP[27]

YOUT7_GP[29]

B.EM_A10 16,17,22

EM_A02_CLE 6,16,17

EM_A04 6,10,16,17

EM_A00 6,10,16,17

LCD_OE 6

DC_EM_CS2n 15

0_EM_CS2n_GP[ 12]

EM_A[9]_GP[92]

EM_A[10]_GP[91]

LCD_OE_EM_CS3n_GP[13]

G

B1_EMA[2]_(CLE)_GP[8]_(AEAW0)

R0_EM_A[4]_GP[10]_(AEAW2)

R1_EM_A[0]_GP[7]_(AEM2)R2_EM_BA[0]_GP[6]_(AEM1)

I2C_INT_ENABLEn 5

READ_OE 6,16,17

PWM1 5,11

CLK_OUT 5,6,11

CC_3V3

VCC_1V8VCC_1V8

P[4]_PWM1
G

I2C_INT_ENABLEn

CLK_OUT_PWM2_GP[84]

EM_A11_GP[90]

EM_A[12]_GP[89]

EM_OEn

VCC_5V

V

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1

2

3

2

4

6

8

10

12

14

16

18

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

72

74

76

78

2

1

DC_P1

1

3

R265NO-POP

4

PCLK_GP[54] RESERVED

PLL_PCLK11

5

20

4

6

8

0

10

12

14

16

18

2

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

3

DC3_PCLK27

9

5

7

9

11

13

15

17

1

21

23

25

27

29

31

33

35

37

39

41

43

45

5

7

9

19

11

13

15

17

21

23

25

27

29

31

C_WE_RNW_GP[35]

YI0_(CCD0)_GP[36]

YI1_(CCD1)_GP[37]

YI2_(CCD2)_GP[38]

YI3_(CCD3)_GP[39]

TVP5146_ENABLEn

YI36,27

TVP5146_ENABLEn27

CI1_(CCD9)_EM_A[19]_EM_D[06]_GP[45]

CI2_(CCD10)_EM_A[18]_EM_D[05]_GP[46]

CI3_(CCD11)_EM_A[17]_EM_D[04]_GP[47]

VD_GP[53] HD_GP[52]

VCLK_GP[31]

VD6,27

YI06,27

YI16,27

YI26,27

VCLK6

B.CI115,22

B.CI315,22

B.CI015,22

B.CI215,22

C_WEN6

47

33

35

37

39

41

43

45

47

YOUT2_GP[24]_BOOTMODE2

YOUT0_GP[22]_BOOTMODE0

YOUT1_GP[23]_BOOTMODE1

YOUT3_GP[25]_BOOTMODE3

VPBECLK_GP[30]

VPBECLK6

YOUT2_BOOTMODE26,10

YOUT1_BOOTMODE16,10

YOUT0_BOOTMODE06,10

YOUT3_BOOTMODE36,10

64

49

51

53

55

57

59

61

63

49

51

53

55

57

59

61

63

65

2_EM_BA[1]_GP[6]_(AEM0)

B

B0_LCD_FIELD_EM_A[3]_GP[11]

G1_EM_A[1]_(ALE)_GP[9]_(AEAW1)

COUT0_EM_D[0]_GP[14[

COUT1_EM_D[1]_GP[15]

COUT2_EM_D[2]_GP[16]

COUT3_EM_D[3]_GP[17]

COUT06,15

COUT16,15

COUT26,15

COUT36,15

EM_A036,16,17

EM_BA06,10,16,17

EM_A01_ALE6,16,17

82

70

0

66

68

7

72

74

76

78

8080909088888686848482

9

65

67

6

71

73

75

77

79

69

67

71

73

75

77

79

EM_A[5]_GP[96]

EM_A[6]_GP[95]

EM_A[7]_GP[94]

EM_A[8]_GP[93]

EM_WEn

EM_WAIT_(RDY/BSYn)

EM_BA16,10,16,17

B.EM_A0516,17,22

B.EM_A0616,17,22

B.EM_A0716,17,22

B.EM_A0816,17,22

WRITE_WE6,16,17

WAIT_BSYn6,16

818183838585878789

ESETn
R

CI_EMA_ENABLEn

MEM_EMD7-0_ENABLEn

CI_EMA_ENABLEn15

MEM_EMD7-0_ENABLEn15

89

SYS_RESETn

RESETn3,4,22

SYS_RESETn3,17,19,26,28,33

98

92929494969698

919193939595979799

100

100

99

CONNECTOR 50 X 2

VCC_5V

VCC_3V3

3

4

5

D D

C C

B B

A A

A-31

Spectrum Digital, Inc

1

A

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

EMAC/MCBSP DC Conn.

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 31 34

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Page Contents:

2

B.GP[0 0] 23

B.GP[0 2] 23B.GP[03]23

AIC33_ENABLEn 13

USER_I2C_IO.A1P0 13USER_I2C_IO.A1P113

USER_I2C_IO.A1P2 13USER_I2C_IO.A1P313

USER_I2C_IO.A0P6 12

B.TXD1 18, 23

B.TXD3 18, 23

B.MDC 18,23

B.RXD3 18,23

B.TXEN 18,23

USER_I2C_IO.A1P0

USER_I2C_IO.A1P2

USER_I2C_IO.A0P6USER_I2C_IO.A0P7

HD13_TXD1_GP[71]

HCNTL1_TXEN_GP[75]

3

69

71

73

75

77

79

89

909088888686848482

CONNECTOR 45 X 2

4

USER_I2C_IO.A1P3

USER_I2C_IO.A1P1

1
7

73

75

77

79

818183838585878789

2

7

74

76

78

80

70

72

74

76

78

80

82

ENET_ENABLEn

HD15_TXCLK_GP[73]

HD14_TXD0_GP[72]

HD12_TXD2_GP[70] HD11_TXD3_GP[69]

B.RXD1 18,23

B.RXDV 18,23

B.CRS 18,23

DS1n_RXD1_GP[79]

H

HINTn_RXD3_GP[82]

HHWIL_RXDV_GP[74]

HD10_CRS_GP[68]

53

55

57

59

61

63

65

67

53

55

57

59

61

63

65

67

69

54

56

58

60

62

64

66

68

70

54

56

58

60

62

64

66

68

DS2n_RXD0_GP[78]

HASn_MDIO_GP[83] HCSn_MDC_GP[81]

H

HRDYn_RXD2_GP[80]

HRNW_RXCLK_GP[77]

HD09_COL_GP[67]

I2C_CLK 5,12,13,17,26,28I2C_DATA5,12,13,17,26,28

CLKX1 5,26

DR1 5,26

FSR1 5,26

RESET_OUTn 3 , 22

ACLKX0_CLKX1_GP[106]

AMUTE0_DR1_GP[110]

AXR0_FSR1_GP[106]

AIC33_ENABLEn

RESET_OUTn

I2C_CLKI2C_DATA

35

37

39

41

43

45

47

49

51

51

52

52

HCNTL0_MRXER_GP[76]

35

37

39

41

43

45

47

49

36

38

40

42

44

46

48

50

36

38

40

42

44

46

48

50

AMUTEIN0_FSX1_GP[109]

AFSX0_DX1_GP[107]

AHCLKX0_CLKR1_GP[108]

UTXD0 5,21

RS232_ENABLEn 21

DR0 5,17,26

CLKR0 5

AUDIO_CLK 11,26

FSR0 5

UDIO_CLK
A

R270NO-POP

AFSR0_DR0_GP[100]

AHCLKR0_CLKR0_GP[101]

AXR0[3]_FSR0_GP[102]

AUDIO_CLK

23

25

27

29

31

33

23

25

27

29

31

33

24

26

28

30

32

34

24

26

28

30

32

34

AN_ENABLEn

AXR0[1]_DX0_GP[104]

ACLKR0_C LKX0_GP[99]

AXR0[2]_FSX0_GP[103]

HECC_TX_TOUT1L_UTXD1_GP[55] HECC_RX_ T I NP1L_URXD1_GP[56]

C

VIC_TINP0L_ENABLEn 11

URXD0 5,21

VCC_3V3

URXD0_GP[85]

UTXD0_GP[86]UCTS0_GP[87]

B.GP[00]

B.GP[02]B.GP[03]

CLKS1_TINP0L_GP[98]

RS232_ENABLEn

VIC_TINP0L_ENABLEn

11

13

15

17

19

21

22

5

7

9

1

7

9

11

13

15

17

19

2

2

8

10

12

14

16

18

20

2

6

8

10

12

14

16

18

20

URTS0_PWM0_GP[88]

B.GP[01]

CLKS0_TOUT 0L_ GP[97]

VCC_5V

1

3

1

3

5

DC_P2

2

4

6

2

4

VCC_3V3

VCC_5V

2

3

4

DX15,26

DX05,17,26

FSX15,26

B.COL18,23

B.TXD018,23

B.TXD218,23

B.MDIO18,23

B.RXD018,23

B.RXD218,23

B.TXCLK18,23

ENET_ENABLEn18

USER_I2C_IO.A0P712

5

D D

B.RXER18,23

B.RXCLK18,23

FSX05,17

CLKX05,17,26

UCTS05

CLKR15,26

C C

URTS05

TOUT1L5,20,21 TINP1L 5,20,21

TOUT0L5 TINP0L 5,11

B.GP[01]23

CAN_ENABLEn20

5

B B

A A

A-32 DM6437 EVM Technical Reference

Spectrum Digital, Inc

A

Revision:

Sheet of

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

VLYNQ/EMIF DC Conn.

SPECTRUM DIGITAL INCORPORATED

VLYNQ_TXD1 23,25

VLYNQ_TXD0 22,25

VLYNQ_CLOCK 22,25

VLYNQ_TXD2 23,25

VLYNQ_TXD3 23,25

2

HD06_VLYNQ_TXD1_GP[64]

HD05_VLYNQ_TXD0_GP[63]

VLYNQ_CLOCK_GP[57]HD00_VLYNQ_SCRUN_GP[58]

HD07_VLYNQ_TXD2_GP[65]

HD08_VLYNQ_TXD3_GP[66]

Wednesday, December 06, 2006 32 34

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2

3

3

2468101214161820

VCC_1V8VCC_3V3 VCC_3V3

DC_P3

13579

VCC_3V3

4

HD01_VLYNQ_RXD0_GP[59]

HD02_VLYNQ_RXD1_GP[60]

VLYNQ_RXD022,25

VLYNQ_RXD122,25

VLYNQ_SCRUN22,25

5

1113151719

HD03_VLYNQ_RXD2_GP[61]

HD04_VLYNQ_RXD3_GP[62]

VLYNQ_RXD222,25

VLYNQ_RXD322,25

HEADER 10X2

VCC_5V VCC_5V

R267

NO-POP

1K

R266

C177

0.1uF

4

SN74LVC1G06DBVRG4

U15

3

5

2

1

VLYNQ_RESET12,25

4

5

D D

C C

B B

A A

A-33

Spectrum Digital, Inc

1

ORE_PWR_OK 34
C

TP21

TP-30

R278

10K

CORE_VDD_SELECT 13

2

272
R

0

CORE_VDD_SELECT function:

0: 1.05V

C312

3

R273

Q4BSS123

D

G

S

4

5

V8_PWR_OK
1

4
3

VCC_5V

1: 1.2V

The FET and res istor in series with it can be

removed if voltag e scaling is not desired.

NO-POP

56.0K 1%
R274

3V3_PWR_OK34

R277

107 1%

R279

C317

3300pF

10K 0.1%

0.01uF

C313

56.0K 1%
R276

1.65K 1%

C316

560pF

C318

3

2

5

1

4

AGND

COMP

WRGD
P

VSENSE

AGND

3.3 sq in AGND,

min thermal pad

Connect

at pin

1

R275

C315

C314

R349

0

R344

NO-POP

BIAS

SS/ENA18SYNC19RT20POWERPAD

U55

17

21

71.5K 1%

0.039uF

0.1uF

L49

VCC_5V

B

Revision:

TP30

TP-60

TP29

TP-60

TP28

TP-60

TP27

EMU_SYS_RESETn

C319

NO-POP

C325

100 uF

+

DSP_CORE_VDD

TP23

TP-60

R280

0.025

TP22

TP-60

C324

1000pF

C323

100uF 4V

+

L50

2.7 uH

0.047uF

10

PH16PH27PH38PH49PH5

BOOT

PGND111PGND212PGND313VIN114VIN215VIN316V

TPS54310PWP

101338-0001

C322

0.1uF

C321

+

10uF LESR

BLM41P750SPT

C320

0.1uF

SYS_RESETn 3,17,19,26,28,30

R281

1K

VCC_3V3

C326

0.1uF

VCC_3V3

1

2

6

VDD

RESET

U56

5

C327

R283

10K 1%

R282 9.09K 1%

VCC_1V8

R314 0

Reset Threhold 0.84 Volts

Reset Threhold 0.84 Volts

13

GND

D10

TPS3808G09DBVRG4

MR3CT4SENSE1

NO-POP

TP-60

TP26

TP-60

TP25

TP-60

R284

10K

VCC_3V3

C328

0.1uF

VCC_3V3

6

VDD

BAS16-7-F

U57

5

R285 20K 1%

VCC_3V3

GND Test Points

Reset Threhold 0.84 Volts

1

2

RESET

C329

R287

10K 1%

VCC_3V3 VCC_3V3

GND

TPS3808G09DBVRG4

MR3CT4SENSE1

NO-POP

VCC_3V3

SPECTRUM DIGITAL INCORPORATED

R288

10K

C330

0.1uF

1

2

6

VDD

GND

RESET

U58

MR3CT4SENSE1

5

C331

R290

10K 1%

R2890

DSP_CORE_VDD

C368

R345

10K

R34633

B

1

2

JP4

nPOR

SW5

PUSHBUTTON SW

A

HEADER 2 NO-POP

AA BB

Sheet o f

1

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

RESET SUPERVISOR

Wednesday, December 06, 2006 33 34

B
Size:

Date:

Title:

Page Contents:

2

Reset Threhold 0.84 Volts

TPS3808G09DBVRG4

3

NO-POP

4

1uF

5

D D

C C

B B

A A

A-34 DM6437 EVM Technical Reference

Spectrum Digital, Inc

B

TP36

TP-30

TP32

TP-30

1

VCC_5V

2

Sets

Voltage

C332

8200pF

R291

3.74K 1%
R293

2K 1%

3

AGND

3.3 sq in AGND,

Connect

at pin

1

R294

4

R393

R292

1V8_PWR_OK

3V3_PWR_OK

10K

R295

VCC_5V

C338

NO-POP

C346

100 uF

+

VCC_3V3

TP34

TP-60

R298

0.025

R296 10 7 1%

R29710K 1%

C336 3300pF

C335

470pF

min thermal pad

U59

21

71.5K 1%

C334

0.039uF

C333

0.1uF

NO-POP

NO-POP

TP31

L52

C337

0.047uF

3

2

4

5

1

OOT
B

AGND

COMP

PWRGD

VSENSE

C342

L51

BLM41P750SPT

VCC_5V

TP-30

C345

+

C344

C343

+

3.3 uH

PH16PH27PH38PH49PH5

C339

0.1uF

+

10uF LESR

C341

0.1uF

47uF

C340

+

R299

220

3.3V @1.5Amp Max

TP33

TP-60

100 uF 4V

1000pF

100uF 4V

10

PGND111PGND212PGND313VIN114VIN215VIN316VBIAS17SS/ENA18SYNC19RT20POWERPAD

TPS54310PWP

101338-0001

3V3_PWR_OK 33

DS5

GREEN

1V8_PWR_OK 33

Sets

Voltage

C347

8200pF

R300

10.2K 1%
R302

2K 1%

GND
A

3.3 sq in AGND,

Connect

at pin

1

R301

3V3_PWR_OK

R439

R438

1V8_PWR_OK

10K

R304

C353

NO-POP

C359

100 uF

R306

L54

2.7 uH

PH16PH27PH38PH49PH5

C356

C355

+

BLM41P750SPT

C354

+

TP38

TP-60

1

TP37

TP-60

C358

1000pF

C357

100uF 4V

+

10

PGND111PGND212PGND313VIN114VIN215VIN316VBIAS17SS/ENA18SYNC19RT20POWERPAD

TPS54310PWP

101338-0001

0.1uF

10uF LESR

0.1uF

VCC_1V8

0.025

R303 107 1%

R305 10K 1%

C351 3300pF

C352

C350

470pF

0.047uF

4

2

5

1

3

BOOT

AGND

COMP

PWRGD

VSENSE

min thermal pad

U60

21

71.5K 1%

C349

0.039uF

C348

0.1uF

0

L53

NO-POP

VCC_5V

Revision:

Sheet of

509102-0001

TMS320DM6437 Evaluation Module

DWG NO

POWER

SPECTRUM DIGITAL INCORPORATED

Wednesday, December 06, 2006 34 34

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Size:

Date:

Title:

Page Contents:

1

2

3

4

5

SILKSCREEN:

ENTER

SLEEVE

SHUNT

C

J16

2.5 MM JACK

5V IN

RASM712

C C

CORE_PWR_OK33

B B

A A

CORE_PWR_OK33

D D

A-35

5

Spectrum Digital, Inc

A-36 DM6437 EVM Technical Reference

Appendix B

Mechanical Information

This appendix contains the mechanical information about the DM6437
EVM produced by Spectrum Digital.

B-1

Spectrum Digital, Inc

THIS DRAWING IS NOT TO SCALE

B-2 DM6437 EVM Technical Reference

Printed in U.S.A., December 2006

509105-0001 Rev C