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SPECTRUM DIGITAL, INC.
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Contains the mechanical information about the TMS320C6416 DSK
About This Manual
This document describes the board level operations of the TMS320C6416 DSP
Starter Kit (DSK) module. The DSK is based on the Texas Instruments
TMS320C6416 Digital Signal Processor.
The TMS320C6416 DSK is a table top card to allow engineers and software
developers to evaluate certain characteristics of the TMS320C6416 DSP to determine
if the processor meets the designers application requirements. Evaluators can create
software to execute onboard or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The TMS320C6416 DSK will sometimes be referred to as the DSK.
Program listings, program examples, and interactive displays are shown is a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Chapter One provides a description of the TMS320C6416 DSK along
with the key features and a block diagram of the circuit board.
Topic Page
1.1Key Features 1-2
1.2Functional Overview1-3
1.3Basic Operation 1-4
1.4Memory Map 1-5
1.5Configuration Switch Settings1-6
1.6Power Supply1-6
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Spectrum Digital, Inc
1.1 Key Features
The C6416 DSK is a low-cost standalone development platform that enables users to
evaluate and develop applications for the TI C64xx DSP family. The DSK also serves
as a hardware reference design for the TMS320C6416 DSP. Schematics, logic
equations and application notes are available to ease hardware development and
reduce time to market.
Mem ory Exp
8
CPLD
Flash
Periph eral Exp
LEDDIP
32
648
SDRAM
Host Port Int
0 1 2 30 1 2 3
Voltage
Reg
JP4
5V
PWR
MIC I N
LINE IN
LINE OUT
AIC23
Codec
JP1 1.4V
JP2 3.3V
JTAG
Embedded
JTAG
USB
HP OUT
McB SPs
MUX
EMIFA
EMIFB
6416
MUX
Ext.
JTAG
DSP
ENDIAN
132
HPI
BOOTM 1
BOOTM 0
PLL_SELECT
Config
SW 3
4
Figure 1-1, Block Diagram C6416 DSK
The DSK comes with a full compliment of on-board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments TMS320C6416 DSP operating at 600 or 720 MHz.
• An AIC23 stereo codec
• 16 Mbytes of synchronous DRAM
• 512 Kbytes of non-volatile Flash memory
• 4 user accessible LEDs and DIP switches
• Software board configuration through registers implemented in CPLD
• Configurable boot options and clock input selection
• Standard expansion connectors for daughter card use
• JTAG emulation through on-board JTAG emulator with USB host
interface or external emulator
• Single voltage power supply (+5V)
1-2 TMS320C6416 DSK Module Technical Reference
Spectrum Digital, Inc
1.2 Functional Overview of the TMS320C6416 DSK
The DSP on the 6416 DSK interfaces to on-board peripherals through one of two
busses, the 64-bit wide EMIFA and the 8-bit wide EMIFB. The SDRAM, Flash and
CPLD are each connected to one of the busses. EMIFA is also connected to the
daughtercard expansion connectors which is used for third party add-in boards.
An on-board AIC23 codec allows the DSP to transmit and receive analog signals.
McBSP1 is used for the codec control interface and McBSP2 is used for data. Analog
I/O is done through four 3.5mm audio jacks that correspond to microphone input, line
input, line output and headphone output. The codec can select the microphone or the
line input as the active input. The analog output is driven to both the line out (fixed
gain) and headphone (adjustable gain) connectors. McBSP1 and McBSP2 can be
re-routed to the expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that ties
the board components together. The CPLD also has a register based user interface
that lets the user configure the board by reading and writing to the CPLD registers.
The DSK includes 4 LEDs and 4 position DIP switch as a simple way to provide the
user with interactive feedback. Both are accessed by reading and writing to the CPLD
registers.
An included 5V external power supply is used to power the board. On-board switching
voltage regulators provide the 1.4V DSP core voltage and 3.3V I/O supplies. The
board is held in reset until these supplies are within operating specifications. A
separate regulator powers the 3.3V lines on the expansion interface.
Code Composer communicates with the DSK through an embedded JTAG emulator
with a USB host interface. The DSK can also be used with an external emulator
through the external JTAG connector.
1 -3
Spectrum Digital, Inc
1.3 Basic Operation
The DSK is designed to work with TI’s Code Composer Studio development
environment and ships with a version specifically tailored to work with the board.
Code Composer communicates with the board through the on-board JTAG emulator.
To start, follow the instructions in the Quick Start Guide to install Code Composer.
This process will install all of the necessary development tools, documentation and
drivers.
After the install is complete, follow these steps to run Code Composer. The DSK must
be fully connected to launch the DSK version of Code Composer.
1) Connect the included power supply to the DSK.
2) Connect the DSK to your PC with a standard USB cable (also included).
3) Launch Code Composer from its icon on your desktop.
Detailed information about the DSK including a tutorial, examples and reference
material is available in the DSK’s help file. You can access the help file through Code
Composer’s help menu. It can also be launched directly by double-clicking on the file
c6416dsk.hlp in Code Composer’s docs\hlp subdirectory.
1-4 TMS320C6416 DSK Module Technical Reference
Spectrum Digital, Inc
1.4 Memory Map
The C64xx family of DSPs has a large byte addressable address space. Program code
and data can be placed anywhere in the unified address space. Addresses are always
32-bits wide.
The memory map shows the address space of a generic 6416 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
Each EMIF (External Memory Interface) has 4 separate addressable regions called
chip enable spaces (CE0-CE3). The SDRAM occupies CE0 of EMIFA while the CPLD
and Flash are mapped to CE0 and CE1 of EMIFB respectively. Daughtercards use
CE2 and CE3 of EMIFA.
Generic 6416
Address
0x00000000
0x00100000
Address Space
Internal Memory
Reserved Space
or
Peripheral Regs
6416 DSK
Internal
Memory
Reserved
or
Peripheral
0x60000000
0x64000000
0x68000000
EMIFB CE0
EMIFB CE1
CPLD
Flash
EMIFB CE2
0x6C000000
EMIFB CE3
0x80000000
SDRAM
0x90000000
0xA0000000
EMIFA CE0
EMIFA CE1
EMIFA CE2
Daughter
0xB0000000
Card
EMIFA CE3
Figure 1-2, Memory Map, C6416 DSK
1 -5
Spectrum Digital, Inc
1.5 Configuration Switch Settings
The DSK has 3 configuration switches that allows users to control the operational state
of the DSP when it is released from reset. The configuration switch block is labeled
SW3 on the DSK board, next to the reset switch.
Configuration switch 1 controls the endianness of the DSP while switches 2 and 3
configure the boot mode that will be used when the DSP starts executing. By default all
switches are off which corresponds to EMIFB boot (out of 8-bit Flash) in little endian
mode. The figure below shows these settings.
The DSK operates from a single +5V external power supply connected to the main
power input (J5). Internally, the +5V input is converted into +1.4V and +3.3V using a
dual voltage regulator. The +1.4V supply is used for the DSP core while the +3.3V
supply is used for the DSP's I/O buffers and all other chips on the board. The power
connector is a 2.5mm barrel-type plug.
There are three power test points on the DSK at JP1, JP2 and JP4. All 6416 I/O
current passes through JP2 while all core current passes through JP1. All system
current passes through JP4. Normally these jumpers are closed. To measure the
current passing through remove the jumpers and connect the pins with a current
measuring device such as a multimeter or current probe.
The DSK provides +3.3V, up to 1A for the daughter card. The +3.3V supply is derived
from the +5V power source via the main +3.3 volt regulator. It is also possible to
provide the daughter card with +12V and -12V when the external power connector (J6)
is used.
1-6 TMS320C6416 DSK Module Technical Reference
Chapter 2
Board Components
This chapter describes the operation of the major board components on
the TMS320C6416 DSK.
Topic Page
2.1CPLD (Programmable Logic)2-2
2.1.1 CPLD Overview2-2
2.1.2 CPLD Registers2-3
2.1.3 USER_REG Register2-3
2.1.4 DC_REG Register2-4
2.1.5 Version Register2-4
2.1.6 MISC Register2-5
2.2AIC23 Codec2-6
2.3Sychronous DRAM2-7
2.4Flash Memory2-7
2.5LEDs and DIP Switches2-7
2.6Daughter Card Interface2-8
2 -1
Spectrum Digital, Inc
2.1 CPLD (Programmable Logic)
The C6416 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic
Device (CPLD) device to implement:
• 4 Memory-mapped control/status registers that allow software
control of various board features.
• Address decode and memory access logic.
• Control of the daughter card interface and signals.
• Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview
The CPLD logic is used to implement functionality specific to the DSK. Your own
hardware designs will likely implement a completely different set of functions or take
advantage of the DSPs high level of integration for system design and avoid the use
of external logic completely.
The CPLD implements simple random logic functions that eliminate the need for
additional discrete devices. In particular, the CPLD aggregates the various reset
signals coming from the reset button and power supervisors and generates a global
reset.
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides
128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is
EEPROM-based and is in-system programmable via a dedicated JTAG interface
(a 10-pin header on the DSK). The CPLD source files are written in the industry
standard VHDL (Hardware Design Language) and included with the DSK.
2-2 TMS320C6416 DSK Module Technical Reference
Spectrum Digital, Inc
2.1.2 CPLD Registers
The 4 CPLD memory-mapped registers allows users to control CPLD functions in
software. On the 6416 DSK the registers are primarily used to access the LEDs and
DIP switches and control the daughter card interface. The registers are mapped into
EMIFB data space at address 0x60000000. They appear as 8-bit registers with a
simple asynchronous memory interface. The following table gives a high level
overview of the CPLD registers and their bit fields:
The table below shows the bit definitions for the 4 registers in CPLD.
USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or
off to allow the user to interact with the DSK. The DIP switches are read by reading the
top 4 bits of the register and the LEDs are set by writing to the low 4 bits.
Table 2: CPLD USER_REG Register
BitNameR/WDescription
7USER_SW3RUser DIP Switch 3(1 = Off, 0 = On)
6USER_SW2RUser DIP Switch 2(1 = Off, 0 = On)
5USER_SW1RUser DIP Switch 1(1 = Off, 0 = On)
4USER_SW0RUser DIP Switch 0(1 = Off, 0 = On)
3USER_LED3R/WUser-defined LED 3 Control (0 = Off, 1 = On)
2USER_LED2R/WUser-defined LED 2 Control (0 = Off, 1 = On)
1USER_LED1R/WUser-defined LED 1 Control (0 = Off, 1 = On)
0USER_LED0R/WUser-defined LED 0 Control (0 = Off, 1 = On)
2 -3
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