SoundTraxx DSD-150DSX Technical Reference
Scope
This section of the manual is designed to provide the advanced user with additional insight into the operation and
capabilities of the SoundTraxx Digital Sound Decoder . By necessity, it is somewhat technical in nature and assumes
a working knowledge of the NMRA DCC Standards and RPs as well as a familiarity with binary and hexadecimal
number systems.
The novice user should not be dissuaded from studying this section as it will help add to his knowledge of DCC
technology and enable him to take greater advantage of its capabilities.
Copies of the NMRA DCC Standards and Recommended Practices may be obtained by contacting:
Technical Department
NMRA Headquarters
4121 Cromwell Road
Chattanooga, TN 37421 USA
Phone: (615) 892-2846
As always, our Technical Support staff will be happy to answer any specific questions you may have regarding the
SoundTraxx DSD.
Applicable Standards
The SoundTraxx DSD has been designed to meet the requirements of the following NMRA Standards and RPs as
defined by September, 1996:
Standard S-9.1 DCC Electrical Standard
Standard S-9.2 DCC Communication Standard
RP-9.1.1 Electrical Interface and Wire Color Code
RP-9.2.1 DCC Extended Packet Format
RP-9.2.2 DCC Configuration Variable
RP-9.2.3 (Tentative) DCC Service Mode
RP-9.2.4 DCC Fail-Safe Operating Characteristics
Bit Timing
The DSD uses a quartz cr ystal timing reference and will recognize DCC packet bits that fall within the following
timing constraints: “1” Bit, 52µS to 64µS
“0” Bit, 90µS to 12000µS
Packets containing bits that fall outside of this range will be rejected.
Addressing Modes
The DSD recognizes the following address modes and ranges as defined by RP-9.2.1:
Broadcast Address 00
Decoder Addresses 01-127
Consist Addresses 01-127
Extended Addresses 0xC000 - 0xE7FF
Packets contain addresses outside of these ranges will be ignored.
Command Instructions
The DSD will process valid packets containing the following instruction codes as defined by RP-9.2.1:
000 Decoder and Consist Control
All currently defined forms of this instruction are processed except 00000110b, Set Advanced Acknowledgment. This instruction is ignored.
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001 Advanced Operation Instructions
The DSD will process only the 128 Speed Step Control form (00111111b) of this instruction.
All other sub-instructions will be ignored.
010 Reverse Speed and Direction Instruction
The DSD will process all forms of this instruction.
011 Forward Speed and Direction Instruction
The DSD will process all forms of this instruction.
100 Function Group One
The DSD will process all forms of this instruction.
101 Function Group two
The DSD will process all forms of this instruction.
110 Reserved Instruction
The DSD will process all forms of this instruction.
111 Configuration Variable Access
The DSD will parse both the short form and long form of this instruction.
Only short form instructions formatted as 11110010b (CV 23 access) or 11110011b (CV 24 access) will be processed. All other short form instruction will be ignored.
All long form instructions will be processed. Ho wever, attempts to write to the following CVs in operations mode will
be ignored:
CV 1 Primary Address
CV 7 Mfg. Version ID
CV 8 Mfg. ID
CV 17 Extended Address MSB
CV 18 Extended Address LSB
Write operations to other CVs may be ignored if an attempt is made to write illegal values. See individual CV
descriptions for details on illegal values.
The DSD will send a basic acknowledgment upon successfully processing an operations mode CV access instruction provided the locomotive is stopped. Otherwise, no acknowledgment is sent.
Programming Modes
The DSD will supports all six programming modes defined in RP-9.2.1 and RP-9.2.3:
Address Mode
Register Mode
Service Mode
Direct Mode
Ops Mode Long Form
Ops Mode Short Form
Not all CVs can be programmed using all modes. Table A lists all CVs supported by the DSD, their applicable
programming mode address as well as the factory default values.
When entering service mode, the DSD will turn off all auxiliary functions and sounds to reduce its current draw to as
low a level as possible.
If the DSD receives an instruction packet to read or write a CV not listed in Table A, the instruction packet will be
ignored and no acknowledgment will be generated.
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Digital Sound Decoder Technical Reference
Upon completion of a paged mode operation, the DSD will reset the page register to 01.
The address query instruction is
not
supported by the DSD.
Miscellaneous Operating Notes
Consist operation is enabled whenev er the consist address (CV 19, bits 0:6) is loaded with a non-zero v alue . Per the
NMRA standard, when the consist address is enabled, the DSD will no longer parse speed/direction pack ets sent to
its primary address. Additionally, the DSD will ignore long form CV access instructions sent to its consist address.
Because the DSD instruction parser assigns a higher priority to the consist address, this can cause unexpected
behavior under certain conditions:
When the DSD is set up for 14 speed step mode with the consist address active, the DSD outputs will no longer
respond to FL function commands sent to the primary address. This may be remedied by using a different speed
step mode or enabling FL consist functions (see CV 22).
If the consist address is set to the same value as the primary address, the DSD will no longer process long form
operations mode CV access instructions sent to the primary address. As a result, the user will be required to use
service mode CV access instructions to clear the consist address. If the extended address is enabled (see CV 29),
this will not be a problem.
Analog Mode Operation
The DSD does
not
support Analog Mode operation and will remain inoperative when placed on a conventional DC
track.
CVs Support
The following table lists all CVs used by the DSD. Details regarding each CV can be found on subsequent pages.
Table A.
CVs Used by the Digital Sound Decoder
Program Mode Address
CV# Name Default Direct Register Paged Mode
Value Mode Mode Page:Register
1 Primary Address 3 01 (0x01) 0 1:0
2 Vstart 7 02 (0x02) 1 1:1
3 Acceleration Rate 0 03 (0x03) 2 1:2
4 Braking Rate 0 04 (0x04) 3 1:3
7 Version ID 06 07 (0x07) 6 2:3
8 Manufacturer ID 141 (0x8D) 08 (0x08) 7 3:0
9 Motor PWM Period 180 (0xB4) 09 (0x09) 3:1
11 Time Out Period 0 11 (0x0B) 3:3
17 Extended Address MSB 192 (0xC0) 17 (0x11) 5:1
18 Extended Address LSB 03 18 (0x12) 5:2
19 Consist Address 0 19 (0x13) 5:3
21 Consist Func. Active 0 21 (0x15) 6:1
22 Consist FL Active 0 22 (0x16) 6:2
23 Consist Acceleration 0 23 (0x17) 6:3
24 Consist Deceleration 0 24 (0x18) 7:0
25 Speed Table Select 0 25 (0x19) 7:1
29 Configuration Data #1 02 29 (0x1D) 4 8:1
30 Error Information 0 30 (0x1E) 8:2
33 FL(f) Output Location 1 33 (0x21) 9:1
(Note 1)
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CV# Name Default Direct Register Paged Mode
Value Mode Mode Page:Register
34 FL(r) Output Location 2 34 (0x22) 9:2
35 F1 Output Location 4 35 (0x23) 9:3
36 F2 Output Location 8 36 (0x24) 10:0
37 F3 Output Location 2 37 (0x25) 10:1
38 F4 Output Location 4 38 (0x26) 10:2
39 F5 Output Location 8 39 (0x27) 10:3
40 F6 Output Location 16 (0x10) 40 (0x28) 11:0
41 F7 Output Location 4 41 (0x29) 11:1
42 F8 Output Location 128 (0x80) 42 (0x2A) 11:2
49 Hyperlight Config. 0 49 (0x31) 13:1
50 Sound V olume 8 50 (0x32) 13:2
51 Background Snd Config 190 (0xBE) 51 (0x33) 13:3
52 Foreground Snd Config 70 (0x46) 52 (0x34) 14:0
53 Snd Config. Byte #3 0 53 (0x35) 14:1
54 Auto Exhaust Rate 94 (0x5E) 54 (0x36) 14:2
55 Exhaust Tone 08 55 (0x37) 14:3
56 Exhaust V olume 255 (0xFF) 55 (0x38) 15:0
66 Forward Trim 128 (0x80) 66 (0x42) 17:1
67 Speed Step 1 0 (0x00) 67 (0x43) 17:2
68 Speed Step 2 9 (0x09) 68 (0x44) 17:3
69 Speed Step 3 18 (0x12) 69 (0x45) 18:0
70 Speed Step 4 28 (0x1C) 70 (0x46) 18:1
71 Speed Step 5 37 (0x25) 71 (0x47) 18:2
72 Speed Step 6 47 (0x2F) 72 (0x48) 18:3
73 Speed Step 7 56 (0x38) 73 (0x49) 19:0
74 Speed Step 8 66 (0x42) 74 (0x4A) 19:1
75 Speed Step 9 75 (0x4B) 75 (0x4B) 19:2
76 Speed Step 10 85 (0x55) 76 (0x4C) 19:3
77 Speed Step 11 94 (0x5E) 77 (0x4D) 20:0
78 Speed Step 12 103 (0x67) 78 (0x4E) 20:1
79 Speed Step 13 113 (0x71) 79 (0x4F) 20:2
80 Speed Step 14 122 (0x7A) 80 (0x50) 20:3
81 Speed Step 15 132 (0x84) 81 (0x51) 21:0
82 Speed Step 16 141 (0x8D) 82 (0x52) 21:1
83 Speed Step 17 151 (0x97) 83 (0x53) 21:2
84 Speed Step 18 160 (0xA0) 84 (0x54) 21:3
85 Speed Step 19 170 (0xAA) 85 (0x55) 22:0
86 Speed Step 20 179 (0xB3) 86 (0x56) 22:1
87 Speed Step 21 188 (0xBC) 87 (0x57) 22:2
88 Speed Step 22 198 (0xC6) 88 (0x58) 22:3
89 Speed Step 23 207 (0xCF) 89 (0x59) 23:0
90 Speed Step 24 217 (0xD9) 90 (0x5A) 23:1
91 Speed Step 25 226 (0xE2) 91 (0x5B) 23:2
92 Speed Step 26 236 (0xEC) 92 (0x5C) 23:3
93 Speed Step 27 245 (0xF5) 93 (0x5D) 24:0
94 Speed Step 28 255 (0xFF) 94 (0x5E) 24:1
95 Reverse Trim 128 (0x80) 95 (0x5F) 24:2
105 User Indentifier #1 0 105 (0x69) 27:1
106 User Indentifier #2 0 106 (0x6A) 27:2
Register Mode Ops Mode Short Form
Paged Mode Ops Mode Long Form
Address Mode Direct Mode
Program Mode Address
(Note 1)
Note1: Paged mode address is shown as PP:RR where PP is the page number and RR is the data register 0-3.
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Address Mode Direct Mode
CV 1
PRIMARY ADDRESS
■■
Register Mode Ops Mode Shor t Form
■❐
Paged Mode Ops Mode Long Form
■❐
CONTROL
Description
Contains the decoder’s primary address between 1 and 127:
bit 7 bit 0
0 A6A5A4A3A2A1A0
Bit 0-6: A0-A6, Decoder Address
Bit 7: Not used. Must be set to 0!
The decoder will process all valid instruction packets containing an address that matches the
value contained in this register when CV 29, bit 5 is set to 0.
Programming this register with a new value will automatically clear the Consist Address (CV 19)
to 0 and clear the Extended Address Enable bit in CV 29 (bit 5).
The decoder will ignore commands that attempt to program this register with values outside the
range of 1 to 127.
Note that this CV cannot be changed in operations mode.
Default V alue:03
Related CVs: See also CV 29, Consist Address, Extended Address
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❐■
CV 2
VSTART
Description
Vstart defines the initial voltage level applied to the motor at speed step 1 as a fraction of
available supply voltage:
bit 7 bit 0
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7: Motor Start Voltage
Vstart may contain any value from 0 to 255 (0 - 0xFF).
The starting voltage applied to the motor may be computed as:
Address Mode Direct Mode
■❐
Register Mode Ops Mode Short Form
■■
Paged Mode Ops Mode Long Form
Starting Voltage = Supply Voltage X ——
where CV 2 is the contents of the Vstart register. A value of 0 corresponds to a zero starting
voltage and 255 corresponds to the maximum available voltage.
For speed steps greater than 1, the DSD will continue to sum the initial starting voltage level
into the throttle computations which has the effect of offsetting all points on a given speed
curve by the level set by Vstar t as illustrated in the figure below.
100%
75%
50%
25%
MOTOR VOLTAGE
0%
CV2
255
VSTART = 20
VSTART = 0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
Default value:07
6
SPEED STEP
Digital Sound Decoder Technical Reference
Address Mode Direct Mode
CV 3
BASELINE
❐■
Register Mode Ops Mode Shor t Form
■❐
Paged Mode Ops Mode Long Form
■■
ACCELERATION
RATE
Description
Contains a value between 0 and 255 (0 - 0xFF) that sets the decoder’s acceleration rate:
bit 7 bit 0
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7: Baseline Acceleration Rate
Acceleration rate may be computed as:
seconds/speed step = ———————————
Number of Speed Steps
When this CV is set to 0, the locomotive speed will respond nearly instantly to
throttle setting. When set to 255, it will take approximately 3.8 minutes to acceler ate to full speed
from a standing stop.
It is recommended that this CV be set to a nonzero value when operating the DSD in 14 or 28
speed step modes as the throttle will interpolate between speed steps during acceleration to
produce a smoother overall response. The Dynamic Digital Exhaust sound effect will also be
more prevalent with higher acceleration settings.
CV 3 * 0.896
increases
in the
Default value:0
Related CVs: See also Baseline Braking Rate, Consist Acceleration Rate,
Consist Brake Rate.
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CV 4
BASELINE
Address Mode Direct Mode
❐■
Register Mode Ops Mode Short Form
■❐
Paged Mode Ops Mode Long Form
■■
BRAKING RATE
Description
Contains a value between 0 and 255 (0 - 0xFF) that sets the decoder’s braking rate:
bit 7 bit 0
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7: Baseline Braking Rate
Braking rate may be computed as:
seconds/speed step = ———————————
Number of Speed Steps
When this CV is set to 0, the locomotive speed will respond nearly instantly to
throttle setting. When set to 255, it will tak e appro ximately 3.8 min utes to brak e to a stop from full
speed.
It is recommended that this CV be set to a nonzero value when operating the DSD in 14 or 28
speed step modes as the throttle will interpolate between speed steps during braking to produce
a smoother over all response. The Dynamic Digital Exhaust sound eff ect will also be more pre v alent with higher braking rates.
CV 4 * 0.896
decreases
in the
Default value:0
Related CVs: See also Baseline Acceleration, Consist Acceleration Rate,
Consist Brake Rate.
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Digital Sound Decoder Technical Reference
Address Mode Direct Mode
CV 7
MANUFACTURER
❐■
Register Mode Ops Mode Shor t Form
■❐
Paged Mode Ops Mode Long Form
■■
VERSION ID (Read Only)
Description
Contains 8 bit software version identifier.
bit 7 bit 0
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7: Version Code
06 = DSD-050 Steam Decoder, Release 1.2
07 = DSD-150 Steam Decoder, Release 1.2
09 = DSD-150 Diesel Decoder, Release 1.0
11 = DSD-150 Diesel Decoder, Release 1.1
14 = DSD-150 Diesel Decoder, Release 1.2
This CV is read only and cannot be modified.
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Address Mode Direct Mode
CV 8
MANUFACTURER ID
(Read Only)
Description
Contains the NMRA issued Manufacturer ID code assignment
for Throttle Up!:
bit 7 bit 0
100011 01
This value is read only and fixed at 141 (0x8D).
❐■
Register Mode Ops Mode Short Form
■❐
Paged Mode Ops Mode Long Form
■■
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Digital Sound Decoder Technical Reference
Address Mode Direct Mode
CV 9
PWM PERIOD
Description
Determines the PWM period of the motor dr ive signals:
bit 7 bit 0
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7: PWM Period
The motor PWM period in microseconds is computed as:
Period = (255 - CV9) * 204.8
This CV may be programmed with an y v alue between 0 and 230 corresponding to a PWM period
range of 52.2µS to 5.12µS. The motor drive frequency can be found by taking the reciprocal of
the period. The drive frequency can thus be programmed from 19.1 Hz to 195 Hz.
❐■
Register Mode Ops Mode Shor t Form
❐❐
Paged Mode Ops Mode Long Form
■■
The decoder will ignore commands that attempt to program this register with v alues greater than
230.
The correct value f or this register will v ary depending upon the locomotive the DSD is installed in
and it may tak e some e xperimentation to find the optimal value . Generally, the selected value will
require a trade-off decision between motor torque and audible noise. Lower numbers will produce more torque but ma y cause the motor and driveline to resonate and b uzz loudly. On smaller
engines that lack traction, sufficient torque can be produced to cause the drive wheels to slip.
Higher numbers, on the other hand, will tend to reduce the buzzing noise b ut there ma y be some
loss in power, especially at low speeds. The following values are provided as a guide line to help
establish a starting point for determining the best PWM period value:
Scale CV9 Value
N, HOn3 180-200
HO, S 175-185
O 160-175
G 120-160
Note: CV 9 also affects the modulation period of the Hyperlight effects. When using the Hyperlight effects, it is recommended that CV 9 be programmed with values greater than 155 as an annoying flicker
may otherwise result.
Default V alue:180 (0xB4), Corresponds to 65Hz dr ive frequency.
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❐■
CV 11
P ACKET TIME OUT
Address Mode Direct Mode
❐❐
Register Mode Ops Mode Short Form
■■
Paged Mode Ops Mode Long Form
VALUE
Description
Contains a value between 0 and 255 corresponding to the time period that is allowed to elapse
between receipt of a valid packet addressed to the DSD before a throttle shutdown occurs.
bit 7 bit 0
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7: Pack et Time-out Value
The time out period is computed in seconds as:
Time Out Period = CV11 X 10
A CV value of 0 disables the time out period and the locomotive will run indefinitely without
receiving another packet.
For all other values, the DSD maintains an internal timer which is reset every time the DSD
receives a valid broadcast address packet or other valid packet whose address matches its
primary address or, if enabled, the extended address or consist address.
In the event no valid packets are received within the prescribed time period, the DSD will br ing
the locomotive to a stop at the rate set by CV 4 and CV 24. The state of the auxiliary function
outputs will remain unchanged.
Default value:00
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Digital Sound Decoder Technical Reference
Address Mode Direct Mode
CV 17,18
EXTENDED
❐■
Register Mode Ops Mode Shor t Form
❐❐
Paged Mode Ops Mode Long Form
■❐
ADDRESS
Description
CV 17 and 18 make up a ‘paired’ CV, meaning that the two CV registers taken together hold one piece of
data, in this case, the 14 bit extended decoder address:
CV 17 Extended Address MSB
bit 7 bit 0
A15 A14 A13 A12 A11 A10 A09 A08
CV 18 Extended Address LSB
bit 7 bit 0
A7 A6 A5 A4 A3 A2 A1 A0
A0-A15: Extended Address Value
The extended address allows the decoder to be assigned one of 10,179 addresses r anging from 0xC000 to 0xE7FF
(Note however, that most command stations will only recognize addresses 0000 through 9999.). The extended
address will only be recognized by the decoder when CV 29, bit 5 is set to 1. Once this bit is set, the decoder will no
longer recognize its primary address until CV 29, bit 5 is cleared.
CV 17 contains the most significant byte and must be loaded with v alues within the range of 0xC0 and 0xE7. CV 18
contains the least significant byte and may contain any value.
To determine the extended address value, add the desired four digit address to the number 49152. Divide this
number by 256 and record the quotient and the remainder . CV 17 is then programmed with the quotient v alue and CV
18 is programmed with the remainder value .
Example: Compute CV 17 and 18 register values for extended address 7152.
Note: Most command stations will handle these computations automatically when setting the extended address.
However, it’s still nice to know how to derive them.
Because CV 17 and 18 make up a paired CV, programming order is important. CV 17 m ust be written to first, followed
by a write CV 18. The decoder will ignore commands that attempt to program these register out of order or with
values outside the allowed range of 0xC000 to 0XE7FF
1. Add 7152 to 49152: Sum = 56304.
2. Divide 56304 by 256: Quotient = 219 Remainder = 240
3. Program CV 17 to 219 (0xDB)
4. Program CV 18 to 240 (0xF0)
Note that these CVs cannot be changed in operations mode.
Default V alue: 0xC003
Related CVs: See also Primary Address, CV 29, Consist Address.
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❐■
CV 19
CONSIST ADDRESS
Address Mode Direct Mode
❐❐
Register Mode Ops Mode Short Form
■■
Paged Mode Ops Mode Long Form
Description
Contains address and direction data for consist operation:
bit 7 bit 0
CDIRA6A5A4A3A2A1A0
Bit 0-6: A0-A6, Consist Address Value
Bit 7: CDIR, Consist Direction
0 = Normal Direction
1 = Reverse Direction
The CDIR bit defines orientation of the locomotive within a consist and specifies whether the direction bit
in a speed/direction data packet should be inver ted.
Bits A0-A6 assigns the consist address from 0 to 127 (0-0x7F).
If A0-A6 = 00, consist commands are ignored. Otherwise, if the decoder receives a valid command
packet whose address matches the consist address, the packet will be processed as any other packet
with the following exceptions:
Long Form CV Access instructions will be ignored.
The direction bit in a speed/direction or advanced operation packet is inverted if CDIR = 1.
Only the auxiliary functions enabled in CV 21 and CV 22 are allowed to change.
When the consist address is active, speed/direction and adv anced operations packets sent to the decoder’s
primary address (or extended address, if enabled) will be ignored. All other instruction packets sent to the
decoder’s primary (or extended) address including CV access and function control will continue to be
processed as normal.
In summary, setting CV 19 to 00 or 128 (0x80) disables consist addressing. Setting CV to a value between 1 and 127 (0x01-0x7F) enables consist addresses 1 to 127 (0x01-0x7F) with the locomotive
oriented facing
consist addresses 1 to 127 with the locomotive oriented facing
forward
in the consist. Setting CV to a value between 129 and 255 (0x81-0xFF) enables
backwards
in the consist.
Default V alue:00
Related CVs: See also Primary Address, Consist Function Active, Consist FL Function Active.
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Digital Sound Decoder Technical Reference
❐■
CV 21
CONSIST FUNCTION
Address Mode Direct Mode
❐❐
Register Mode Ops Mode Shor t Form
■■
Paged Mode Ops Mode Long Form
ACTIVE
Description
Defines which functions may be controlled by packets sent to the decoder’s consist address.
Disabled functions may be controlled only from decoder’s primary or extended address:
bit 7 bit 0
F8 F7 F6 F5 F4 F3 F2 F1
Bit 0: F1, Consist Function 1 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
Bit 1: F2, Consist Function 2 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
Bit 2: F3, Consist Function 3 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
Bit 3: F4, Consist Function 4 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
Bit 4: F5, Consist Function 5 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
Bit 5: F6, Consist Function 6 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
Bit 6: F7, Consist Function 7 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
Bit 7: F8, Consist Function 8 Enable Bit
0 = function is disabled for consist operation.
1 = function is enabled for consist operation.
This register is useful for diff erentiating the lead engine in the consist from the other engines. F or e xample, by setting
this register in the lead locomotive to 02 and the same register in all other engines to 00, only the whistle on the lead
locomotive will blow when the command to turn on Function 2 is sent to the consist.
Default V alue:00
Related CVs: See also Consist Address, Consist FL Function Active.
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