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Lt:
LIST
PARTS LIST of SECTION 7 in accordance
for
15.5
OF
This
service
Redraw
GDM
Change
to
DIFFERENT
manual
the
CIRCUIT DIAGRAM of SECTION 5, EXPLODED
-1602.
the H period
21
/J.
sec
and
POINTS
has
been
in
the
the
voltage from
(GDM
prepared
waveform
+B145
-1601/1602)
for GDM
with
diagram
-160l.
the
list of different points
in
to 120
VIEWS
the
CIRCUIT DIAGRAM of SECTION 5
V.
of SECTION
when
6,
using
and
ELECTRICAL
this
manual
from
L Board
--------
C41
POWER BLOCK
ASSY
G
Board
IC51 1-235-843-11 POWER MODULE (DM-28) 1-235-844-11 POWER MODULE
Part
A-1235-013-A
1-136-091-00
Part
GDM-1601
No. Description
L BOARD COMPLETE A-1235-011-A L BOARD COMPLETE
FILM
0.0068MF
No. A-1477-875-A
2KV 1-136-139-00 FILM 0.012MF
3%
Part
Part
No.
No.
GDM-1602
A-1477-873-A
Description
3%
CDM-32)
2KV
-1-
D
Board
-----
C110
C211
C219 1-136-121-00 FILM
C220 1-136-103-00
C224 1-130-908-00 FILM
C310
The A board consists
amplifiers
pedestal clamp circuit,
blanking circuit. In
and
on
the
mounted
fier and clamp circuit. The
on
the
c'ontrol pulse generators.
3-'
-2. Contrast Amplifier (AA Board)
The
amplifier for
circuit
tracking
fier gain can be
ment
following signal process. A reference pulse is inserted
on
the
buffer
that
various
contrast
control
A board. Each
on
the
A board, includes a sync signal
control
current
to
obtain
between
for
contrast
back
QI).
of
three
channels
include a
A board, consists
wide frequency response and
channels.
continuously
control.
porch
contrast
output
addition,
pulse generators are also
of
AB
amplifier utilizes a differential
balance
of
control
In
This is achieved with
the
input
control
amplifier (main),
a sync signal
the three AA boards,
of a contrast
board, also
and a feedback
this circuit,
changed by
signal
video signal
of
video signal
separator
located
mounted
separator
the
DC
(output
circuit,
and
ampli-
and
good
ampli-
adjust-
the
of
I
t
sync
pulse
Fig. 3-1 Reference Pulse
The signal
sisting
differential amplifier, Q3
balance
preamplifiers. The amplified signal is
by
QI4
15
Q
and
mined by the
RV401
IC I (2/2)
that
that
(2/2)
level becomes equal
tween
changed
is
then
input
to
the
conttast
of
Q2
thru
Q7. The gain
and
of
the collector currents. Q8
and
input
to
a sampling circuit for feedback.
samples
charges C I
the
'at pin G). By feeding back
to
(R-DRV),
outputs
sampled
the
the
two
by
RV4
the
magnitude
O.
Meanwhile, a
contrast
is
a DC voltage
voltage
contrast
inputs
on
the
of
control
input
at
pin
to
at
pin ® is
amplifier,
to
the
potential
of
IC I
(2/2).
H board, as explained.
amplifier con-
is
determined
Q4, by altering
thru
Q 13 are
then
buffered
the
reference pulses
DC
voltage, deter-
VR
(H
board)
G)
of
IC1
the
base
of
compared
the
output
the
reference pulse
difference be-
Contrast
of
can
in
the
the
via
(2/2).
Q6 so
with
ICI
be
3-'
-3. Pedestal Clamp (AA Board)
This circuit
ration
video amplifier
at
the
the
(black)
power
DC
The
emitter
from
reference voltage (DC) is
and
a feedback voltage
final video stage
the
detected
background
voltages
level
voltages.
performs
of
the
collector
input
signal
of
the
supply
IC I (1/2),
and
of
the
collector
pedestal clamping for DC resto-
input
signal since
is
AC coupled. Altering
of
Q4 restores
and
stabilizes
signal
at
the
CRT
to
regulate a bias voltage
voltage
pulse. IC 1
of
Q5 is
which is a high gain
provided
subtracted
is
at pin
(}).
voltage
the
at
RIl1
output,
of
Q4
(1/2)
thru
the
the
the
cathode.
controlled
Q 17 samples
activating
compares
Q5,
so as
to
input
DC
component
pedestal level
by
DC
'lmplifier. A
at
pin ® of
by
QI7
the
the
controls
equalize
3-1-4. Sync Separator and Pulse Generator
(AB
Board)
The sync
guishes
signal
sync (HD)
sync signals are
signals are directly
(X
sync pulses
and
lines Y2
VD pulses are
board.
Meanwhile,
trigger IC2
background
HD, and
time, IC2
and generates
3-'-5.
The video signals
input
composed
and Q I
response
mized
(Ll
sate for
I)
02),
and
of
XI.
to
separator,
the
separates
and
IC 1,
and
If
no
and Y I,
the
(1/2), a monostable
is
output
(2/2)
Video
the
of
02
and
of
±3 dB
with
parallel
and
the
high
consisting
sync
portion
vertical
input
the
data
automatically
external
internal
then
pulses
pulse is
is triggered by
the
contrast
Output
from
base
of
a cascade amplifier consisting
has a gain
from
emitter
frequency
of
the
sync pulses
sync
to
the
input
to
selector.
sync pulses are
sync,
sent
to
output
generated,
thru
Q6
control
Amplifier
the
AA
QI01.
The
of
60
Hz
peaking
peaking (Q I 0
response.
of
QI
thru
the
composite
into
(VD). When
monitor,
pins
selects data lines X2
are selected. HD
the D board
from
and
the
board
20
(Ll 0 I),
the
(})
(X2)
IC I detects
detected,
pin @ of
multivibrator.
synchronized
Q7.
At
background
pulse.
preamplifier are
video
output
dB.
The
to
100 MHz is
series peaking
I),
which
stage
of
the
the
DC
bias
of
Q5 acts as a
to
Q4.
the
output
IC
from
the
and
holds
gate
by
two
input
the
DC
the
input
Q3,
distin-
video
horizontal
external
two
sync
and ®
external
data
and
via
the
IC
with
the
same
pulse
stage
of
Q I 0 I
frequency
opti-
compen-
1:
a
B
I
A
is
3-1
3-1-6. Blanking Amplifier
Blanking signals are
B
board,
to
the
is
switched
of
approximately
Q404.
specific
G 1 grids
clamping levels can be varied by
RV40S (B-BKG),
for
background
3-2. B BOARD
The B board
the
A board
All signal
to
suppress
Q 1 acts as a fade
monitor
turned
a
minimum.
switched
to
the
3-3. C BOARD
The C board
to
the
mounted
are
charge (flash-over)
3-4. D
3-4-1.
The
horizontal
vertical
are processed
The
from
and
phase by a
circuit. Meanwhile,
a voltage divider
and
delayed H sync
compared
AFC
with
delay
horizontal
deflection
The
signal
puts
pin
Ii§>
off
The
DC
levels
of
the
and
I/O,
RFI.
is
powered
on
and
off,
normal
relays
CRT
electrodes.
BOARD
DA
Board
DA
board
phase
synchronization
horizontal
the A board,
Q]
of
IC
PHASE
triggers a SAW
in
circuit synchronizes
the
HD
signal. RV20S (H-PHASE)
time
of
position
is
driven
vertical oscillator
and
locked
two
vertical rate pulses, a V drive pulse from
and
a V blanking pulse from pin
input
from
base
of
Q403
when
Q403
is
60
Vp-p appears
blanking pulses are
and
supplied
CRT
via
the
C board.
with
respect
level
adjustment.
is an
interface
the
as well as
control
up. When
clamps
C2 is gradually charged up
returning
level.
the
on
the
current
(Deflection
performs
locked
and
controlled
and
vertical sync (HD, VD) signals
positive
1.
The
SHIFTER
the
(C22S,
signal
the
AFC
the
PHASE
of
by
at a frequency
card
D, H, and power
DC
power
for
the
contrast
the
contrast
bias voltages and video signals
Spark
board
to
chassis
the
loop,
functions. These
by
true,
H sync signal
horizontal
C226),
TOOTH
and
the
circuit. The
the
SHIFTER
the
display image.
the
output
is
triggered by
the
D board, via
to
switch
it
on, and a blanking pulse
at
the
then
clamped
to
each
of
Two
RV404
to
the
power
gaps
to
return
and
horizontal
vertical oscillator,
IC
are
and is
is
GENERATOR.
(G-BKG)
the
Red channel,
for signals
supply
I/O,
contain
picture
is applied,
control
control
and
neon
the
ground.
HV
Regulation)
I.
input
to
is
then
input
to
retrace pulse,
fed back
sawtooth
horizontal
at
of
to
output
controls
and
adjusts
Horizontal
pin 0 .
the
60
Hz. IC 1
Qj)
the
on.
Q404
emitter
individual
when
voltage
and
oscillator,
functions
delayed in
of
at
the
three
and
between
boards.
filters
the
Ql
to
Q 1
voltage
lamps
CRT
dis-
and
pins
CD
an AFC
thru
pin ®
The
wave are
from
the
scanning
the
the
VD sync
out-
.
is
is
DB
3-4-2.
The
tooth
ICI
a vertical
capacitor
sawtooth
tor
and
diodes D 1
sawtooth
circuit via
Miller
period
output
tion
output
is
input
correction.
component
allow
at
the
the V -sawtooth
other
3-4-3.
The
from
board
Th~
positive and negative
are varied
IC I
waves
and
forms a similar
the
Meanwhile,
triggers a phase
after
Q4
phase shift is varied by
(j)
ments
correction.
(1/2)
switch
ingly, a
Q4,
sawtooth
inverted by IC2
Board
DB
board
generates waveforms, including a saw-
wave, for S-correction
(1/2),
configured
period
sawtooth
C2
control
wave.
The
bias
is
supplied from IC2
the
peaks
of
the
and
DS. The resulting zero-crossing
wave
is
input
RVIOI
integrator,
parabolic wave. IC 1
from IC2
wave (similar
is
amplitude
to
adjustment
top
and
correction
DC
Board
DC
board
T203
and generates a
sawtooth
by
(l
/2)
to
modulate
bottom
starting
passing
of
ICI
for
both
is
input
QS
activated
horizontal
is
generated
wave
(V-SIZE)
IC2
(1/2)
to
adjusted
the
vertical deflection circuit for linearity
RVI03
to
(HOT)
sums
pincushion
point
the
(2/2)
The
(V-LINE BALAj\lCE) adds a
the V sawtooth
of
the
bottom
and
circuits
receives
and
complex
is
input
RV104,
the
the
function
of
H retrace pulse is inverted by Q 1 and
control
thru
Q2.
and allows individual phase adjust-
top
and
output
to
Miller
by
sawtooth
and
output
(1/2)
and
half
is
of
vertical deflection.
as a Miller
the
(2/2)
waveform are
(I/2),
and
a sine wave)
balance
of
V -sine waves are supplied
on
the
the
to
RVIOS,
amplitude
horizontal
correction.
for phase
the
shifter
the
bottom
voltage from pin
integrator
the
amplitude
from IC 1
is
integrator,
wave. Transistor Q 1
rise
and
fall times
current
to
Dl,
waves,
The
of
the
ramp
to
pin @
the
and
also
generates a vertical
(2/2)
generates an S-correc-
by
RVI02
wave
the
display. Additionally,
the
D board.
horizontal
V-sawtooth
"butterfly"
02,
and
RVI06,
tamp
horizontal
composed
magnitude
output
pincushion
of
determined
vertical
of
and D3, split
adjusted
control
deflection
input
to
integrates
at
pin (j). This
(V-LIN)
at
IC2
vertical linearity
retrace pulse
from
waveform.
the
amplitudes
and
signals for
ICl
(2/2)
by altering
ramp signals.
of
of
voltage from pin
distortion
sawtooth
CD
IC2
(2/2)
with
collector
signal,
input
of
Q4.
synchronized
modulated
(1/2).
This signal
to
QI03.
generates
of
genera-
ICI
another
(1/2)
the
RVI07.
Q3 and
the pulse
of
Accord-
by the
and
the
(1/2)
by
the
and
DC
to
to
DB
into
top
per-
IC 1
reset
by
is
3-2
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