Sony ICX262AQF Datasheet

ICX262AQF

Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras

Description

The ICX262AQF is a diagonal 8.933mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/4.28 second.

Also, number of vertical pixels decimation allows output of 30 frames per second in high frame rate readout mode.

R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology.

This chip is suitable for applications such as electronic still cameras, etc.

Features

• Supports frame readout

• High horizontal and vertical resolution

• Supports high frame rate readout mode: 30 frames/s,

AF1 mode: 60 frames/s, 50 frames/s,

AF2 mode: 120 frames/s, 100 frames/s

• Square pixel

• Horizontal drive frequency: 18MHz

• No voltage adjustments (reset gate and substrate bias are not adjusted.)

• R, G, B primary color mosaic filters on chip

• High sensitivity, low dark current

• Continuous variable-speed shutter

• Excellent anti-blooming characteristics

• Exit pupil distance recommended range –20 to –100mm

• 20-pin high-precision plastic package Device Structure

• Interline CCD image sensor

• Total number of pixels: 2140 (H) × 1560 (V) approx. 3.34M pixels

• Number of effective pixels: 2088 (H) × 1550 (V) approx. 3.24M pixels

• Number of active pixels: 2080 (H) × 1542 (V) approx. 3.21M pixels diagonal 8.933mm

• Number of recommended record pixels: 2048 (H) × 1536 (V) approx. 3.15M pixels diagonal 8.832mm

aspect ratio 4:3

• Chip size: 8.10mm (H) × 6.64mm (V)

• Unit cell size: 3.45µm (H) × 3.45µm (V)

• Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels

Vertical (V) direction: Front 8 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 28

Vertical 1 (even fields only)

• Substrate material: Silicon

– 1 –

E00112-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

20 pin SOP (Plastic)

A

Pin 1

V

4

48

2

8

Pin 11

H

Optical black position

(Top View)

∗

Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor

AAA AAA AAA

– 2 –

ICX262AQF

V

OUT

GND

TEST

Vφ

1B

Vφ

1A

Vφ

2

Vφ

3B

Vφ

3A

Vφ

4

V

DD

φRG

Hφ

2

Hφ

1

GND

φSUB

C

SUB

V

L

Hφ

1

Hφ

2

B

Gr

B

Gr

B

Gr

Gb

R

Gb

R

Gb

R

B

Gr

B

Gr

B

Gr

Gb

R

Gb

R

Gb

R

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

1

17

18

19

20

Note) : Photo sensor

Note)

Horizontal register

Vertical register

Block Diagram and Pin Configuration

(Top View)

Pin No. Symbol Description Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10

Vφ4 Vφ3A Vφ3B Vφ2 Vφ1A Vφ1B TEST TEST GND VOUT

Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Test pin

∗1

Test pin

∗1

GND Signal output

11 12 13 14 15 16 17 18 19 20

VDD φRG Hφ2 Hφ1 GND φSUB CSUB VL Hφ1 Hφ2

Supply voltage Reset gate clock Horizontal register transfer clock Horizontal register transfer clock GND Substrate clock Substrate bias

∗2

Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock

Pin Description

∗1

Leave this pin open.

∗2

DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF.

– 3 –

ICX262AQF

Against φSUB

Against VL

Between input clock pins

Storage temperature Guaranteed temperature of performance Operating temperature

Absolute Maximum Ratings

–40 to +12

–50 to +15 –50 to +0.3 –40 to +0.3 –25 to –0.3 to +22

–10 to +18 –10 to +6.5 –0.3 to +28 –0.3 to +15

to +15

–6.5 to +6.5

–10 to +16

–30 to +80

–10 to +60

–10 to +75

V V V V V V V V V V V V

V °C °C °C

VDD, VOUT, φRG – φSUB Vφ1A, Vφ1B, Vφ3A, Vφ3B – φSUB Vφ2, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND Hφ1, Hφ2 – GND Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4

Item Ratings Unit

Remarks

∗1

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply.

∗1

– 4 –

ICX262AQF

Clock Voltage Conditions

Item

Readout clock voltage

VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2,

VVL3, VVL4 VφV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL VφH VHL VCR VφRG VRGLH – VRGLL VRGL – VRGLm VφSUB

14.55 –0.05

–0.2 –8.0

6.8 –0.25 –0.25

4.75

–0.05

0.8

3.0

21.5

15.0 0 0

–7.5

7.5

5.0 0

2.5

3.3

22.5

15.45

0.05

0.05 –7.0

8.05

0.1

0.6

0.9

0.5

5.25

0.05

5.25

0.4

0.5

23.5

V V V

V V

V V V V V V V V V V V V V

1 2 2

2 2

2 2 2 2 2 2 3 3 3 4 4 4 5

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

High-level coupling High-level coupling Low-level coupling Low-level coupling

Cross-point voltage

Low-level coupling Low-level coupling

Horizontal transfer clock voltage

Reset gate clock voltage

Substrate clock voltage

Vertical transfer clock voltage

Symbol Min. Typ.

Max.

Unit

Remarks

Bias Conditions

Item Supply voltage Protective transistor bias Substrate clock Reset gate clock

VDD VL

φSUB φRG

14.55

15.0

∗1 ∗2 ∗2

15.45

V

Symbol Min. Typ. Max. Unit Remarks

DC Characteristics

Item

Supply current

IDD

2.0

4.5

7.0

mA

Symbol Min. Typ. Max. Unit Remarks

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power supply for the V driver should be used.

∗2

Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.

Waveform diagram

– 5 –

ICX262AQF

RGND

CφV1B3B

R1B

CφV41B

Vφ1B

CφV4

CφV41A

CφV1B

CφV1B3A

CφV1A1B

CφV1A

CφV1B2

R1A

Vφ1A

CφV1A2

Vφ2

R2

CφV24

CφV1A3A

CφV23A

CφV23B

R3A

Vφ3A

CφV2 CφV3A

CφV3A3B

CφV1A3B

CφV3B

R3B

Vφ3B

CφV3A4

CφV3B4

Vφ4

R4

Vertical transfer clock equivalent circuit

Hφ1

RφH

CφH1 CφH2

RφH

CφHH

Hφ2

RφH

Hφ1 Hφ2

RφH

Horizontal transfer clock equivalent circuit

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer clock and GND

CφV1A, CφV3A CφV1B, CφV3B CφV2, CφV4 CφV1A2, CφV3A4 CφV1B2, CφV3B4 CφV23A, CφV41A CφV23B, CφV41B CφV1A3A CφV1B3B C

φ

V1A3B, C

φ

V1B3A

CφV24 C

φ

V1A1B, C

φ

V3A3B

CφH1, CφH2

CφHH

CφRG

CφSUB R1A, R1B, R2,

R3A, R3B, R4 RGND RφH

1500 5600 2700

390 470 120 180

39

220

62 75 68

36.5

88.5

8

1000

62 18

15

pF pF pF pF pF pF pF pF pF pF pF pF

pF

Ω Ω

Ω

Capacitance between vertical transfer clocks

Capacitance between horizontal transfer clock and GND

Capacitance between horizontal transfer clocks

Capacitance between reset gate clock and GND

Capacitance between substrate clock and GND

Vertical transfer clock series resistor Vertical transfer clock ground resistor

Horizontal transfer clock series resistor

Symbol Min. Typ. Max. Unit Remarks

– 6 –

ICX262AQF

Drive Clock Waveform Conditions (1) Readout clock waveform

(2) Vertical transfer clock waveform

II

100%

90%

10%

0%

tr twh tf

φM

0V

φM

2

Vφ1A, Vφ1B Vφ3A, Vφ3B

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

II

VVT

– 7 –

ICX262AQF

twh

tf

tr

90%

10%

V

HL

twl

Hφ1

two

Hφ2

VRGL

VRGLL

VRGLH

twl

V

RGH

RG waveform

VRGLm

tr twh tf

V

CR

(3) Horizontal transfer clock waveform

(4) Reset gate clock waveform

VφH

2

Point A

VφRG

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

VSUB

90%

100%

10%

0%

tr twh tf

φM

2

(A bias generated within the CCD)

VφSUB

Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

– 8 –

ICX262AQF

1.0

0.8

0.6

0.4

0.2

0

400 450 500 550 600 650 700

Wave Length [nm]

Relative Response

B

R

G

Clock Switching Characteristics (Horizontal drive frequency: 18MHz)

Item

Readout clock

Vertical transfer clock

Reset gate clock

Substrate clock

VT Vφ1A, Vφ1B,

Vφ2, Vφ3A, Vφ3B, Vφ4

Hφ1 Hφ2 Hφ1 Hφ2

φRG

φSUB

2.63

14 14

7

1.7

2.83

19.5

6.67

10

3.06

141419.5

19.5

5.56 37

0.5

8.5

0.01

0.01 4

14 14

0.5

15

0.5

8.5

0.01

0.01 5

250

14 14

0.5

µs

ns

µs

ns

µs

During readout

When using CXD3400N

tf ≥ tr – 2ns

During drain charge

Symbol

twh

Min. Typ.

Max.

Horizontal transfer clock

Hφ1, Hφ2 12 19.5 ns

Item

Symbol

two

Unit

Remarks

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

Min. Typ.

Max.

twl tr tf

Unit Remarks

Horizontal

transfer clock

During imaging

During parallel-serial conversion

Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)

– 9 –

ICX262AQF

Image Sensor Characteristics (Horizontal drive frequency: 18MHz) (Ta = 25°C)

Item

G sensitivity Sensitivity

comparison Saturation signal

Smear

Video signal shading

Dark signal Dark signal shading Line crawl G Line crawl R Line crawl B Lag

Sg Rr Rb Vsat

Sm

SHg

Vdt ∆Vdt Lcg Lcr Lcb Lag

220

0.3

0.35 450

270

0.45

0.50

–89.1 –73.6

0.6

0.65

–81.2 –65.6

20 25 12

6

3.8

0.5

mV

dB

%

mV mV

% % % %

1 1 1 2

3

4

5 6 7 7 7 8

1/30s accumulation

Ta = 60°C Frame readout mode,

∗1, ∗2

High frame rate readout mode,

∗2

Zone 0 and I

Zone 0 to II' Ta = 60°C, 4.28 frame/s Ta = 60°C, 4.28 frame/s,

∗3

Symbol

Min. Typ. Max. Unit

Measurement

method

Remarks

4

1550 (V)

44

2088 (H)

V

10

H 8

V

10

Effective pixel region

Ignored region

Zone 0, I

Zone II, II'

R B

Measurement System

CCD

C.D.S

S/H

AMP

CCD signal output [∗A]

Gr/Gb channel signal output [∗B]

S/H

R/B channel signal output [∗C]

Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.

∗1

After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation.

∗2

No electronic shutter

∗3

Excludes vertical dark signal shading caused by vertical register high-speed transfer.

Zone Definition of Video Signal Shading