Sony ICX259AL Datasheet

ICX259AL
Diagonal 6mm (Type 1/3) CCD Image Sensor for CCIR B/W Video Cameras
Description
The ICX259AL is an interline CCD solid-state image sensor suitable for CCIR B/W video cameras with a diagonal 6mm (Type 1/3) system. Compared with the current product ICX059CL, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically from visible light region to near infrared light region through the adoption of EXview HAD CCDTMtechnology.
This chip features a field period readout system and an electronic shutter with variable charge-storage time.
Features
Sensitivity in near infrared light region
(+8dB compared with the ICX059CL, λ = 945nm)
High sensitivity (+7dB compared with the ICX059CL, no IR cut filter)
Low smear (–20dB compared with the ICX059CL)
High D range (+5dB compared with the ICX059CL)
High S/N
High resolution and low dark current
Excellent antiblooming characteristics
Continuous variable-speed shutter
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
Reset gate: 5V drive
Horizontal register: 5V drive
Device Structure
Interline CCD image sensor
Image size: Diagonal 6mm (Type 1/3)
Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels
Total number of pixels: 795 (H) × 596 (V) approx. 470K pixels
Chip size: 6.00mm (H) × 4.96mm (V)
Unit cell size: 6.50µm (H) × 6.25µm (V)
Optical black: Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction : Front 12 pixels, rear 2 pixels
Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
Substrate material: Silicon
– 1 –
E99526A99
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
A
A
A
Pin 1
V
3
40
2
12
Pin 9
H
Optical black position
(Top View)
EXview HAD CCD is a trademark of Sony Corporation. EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of HAD (Hole-Accumulation-Diode) sensor.
TM
16 pin DIP (Plastic)
AAA AAA AAA
– 2 –
ICX259AL
Block Diagram and Pin Configuration
(Top View)
6
7
NC
Vφ
1
Vφ
2
Vφ
3
Vφ
4
V
DD
GND
φSUB
V
L
φRG
Hφ
2
2
3
4
GND
8
1
V
OUT
NC
10
11
12
14
9
16
13
15
NC
5
Hφ
1
Note)
Horizontal Register
Vertical Register
Note) : Photo sensor
Pin No.
1 2 3 4 5 6 7 8
Vφ4 Vφ3 Vφ2 Vφ1 GND NC NC VOUT
Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND
Signal output
9 10 11 12 13 14 15 16
VDD GND φSUB VL φRG NC Hφ1 Hφ2
Supply voltage GND Substrate clock Protective transistor bias Reset gate clock
Horizontal register transfer clock Horizontal register transfer clock
Symbol Description Pin No. Description
Pin Description
Symbol
Absolute Maximum Ratings
1
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Against φSUB
Against GND
Against VL
Between input clock pins
Storage temperature Operating temperature
–40 to +8
–50 to +15 –50 to +0.3 –40 to +0.3 –0.3 to +20
–10 to +18
–10 to +6 –0.3 to +28 –0.3 to +15
to +15
–6 to +6 –14 to +14 –30 to +80 –10 to +60
V V V V V V V V V V V
V °C °C
VDD, VOUT, φRG – φSUB Vφ1, Vφ3 φSUB Vφ2, Vφ4, VL φSUB Hφ1, Hφ2, GND – φSUB VDD, VOUT, φRG – GND Vφ1, Vφ2, Vφ3, Vφ4 – GND Hφ1, Hφ2 – GND Vφ1, Vφ3 – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4
Item Ratings Unit Remarks
1
– 3 –
ICX259AL
Bias Conditions
Clock Voltage Conditions
Item
Readout clock voltage
VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2,
VVL3, VVL4 VφV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL VφH VHL
VφRG VRGLH – VRGLL
VRGL – VRGLm VφSUB
14.55 –0.05
–0.2 –8.0
6.3 –0.25 –0.25
4.75
–0.05
4.5
21.0
15.0 0 0
–7.0
7.0
5.0 0
5.0
22.0
15.45
0.05
0.05 –6.5
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.4
0.5
23.5
V V V
V V
V V V V V V V V
V V
V V
1 2 2
2 2
2 2 2 2 2 2 3 3
4 4
4 5
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2 VφV
= VVHn – VVLn (n = 1 to 4)
High-level coupling High-level coupling Low-level coupling Low-level coupling
Input through 0.1µF capacitance
Low-level coupling Low-level coupling
Horizontal transfer clock voltage
Reset gate clock voltage
Substrate clock voltage
Vertical transfer clock voltage
Symbol Min.
Typ. Max.
Unit
Waveform
diagram
Remarks
DC Characteristics
Item
Supply current
IDD 4 6 mA
Symbol Min. Typ. Max. Unit Remarks
Item
Supply voltage Protective transistor bias Substrate clock Reset gate clock
VDD VL
φSUB φRG
14.55
15.0
122
15.45 V
Symbol Min. Typ. Max. Unit Remarks
1
VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.
– 4 –
ICX259AL
RφH
RφH
Hφ2
Hφ1
CφH1 CφH2
CφHH
Vφ1
CφV12
Vφ2
Vφ4
Vφ3
CφV34
CφV23CφV41
CφV13
CφV24
CφV1 CφV2
CφV4 CφV3
RGND
R4
R1
R3
R2
Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
RφRG
RGφ
Cφ
RG
Reset gate clock equivalent circuit
Item
Capacitance between vertical transfer clock and GND
CφV1, CφV3 CφV2, CφV4 CφV12, CφV34 CφV23, CφV41 CφV13 CφV24
CφH1, CφH2
CφHH
CφRG
CφSUB R1, R3
R2, R4 RGND RφH RφRG
1200 1000
680 330 100 100
75
30
5
270
82 120 100
15
50
pF pF pF pF pF pF
pF
pF
pF
pF
Ω Ω Ω Ω Ω
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor Horizontal transfer clock series resistor Reset gate clock series resistor
Symbol Min. Typ. Max. Unit Remarks
Clock Equivalent Circuit Constant
– 5 –
ICX259AL
Drive Clock Waveform Conditions (1) Readout clock waveform
(2) Vertical transfer clock waveform
II II
100%
90%
10%
0%
VVT
tr twh tf
φM
0V
φM
2
Vφ1 Vφ3
Vφ2 Vφ4
VVHH
VVH
VVHL
VVHH
VVHL
VVH1
VVL1
VVLH
VVLL
VVL
VVHH
VVH3
VVHL
VVH
VVHH
VVHL
VVL3
VVL
VVLL
VVLH
VVHH VVHH
VVH
VVHL
VVHL
VVH2
VVLH
VVL2
VVLL
VVL
VVHH VVHH
VVHL
VVH4
VVHL
VVH
VVL
VVLH
VVLL
VVL4
VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)
– 6 –
ICX259AL
tr twh tf
90%
10%
twl
Vφ
H
VHL
(3) Horizontal transfer clock waveform
Point A
twl
Vφ
RG
VRGH
VRGL
VRGLH
RG waveform
V
RGLL
Hφ1 waveform
twhtr tf
Vφ
H/2 [V]
VRGLm
(4) Reset gate clock waveform
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr twh tf
φM
φM
2
VφSUB
(A bias generated within the CCD)
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