Sony CXP921064A Datasheet

Description

The CXP921064A is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, I2C bus interface, timer, real-time pulse
generator, clock prescaler, remote control receive
circuit, and as well as basic configurations like a 16­bit CPU, ROM, RAM, and I/O port.

This LSI also provides the sleep/stop functions that
enable lower power consumption.

Features

• An efficient instruction set as a controller

— Direct addressing, numerous abbreviated forms,

multiplication and division instructions

• Instruction sets for C language and RTOS

— Highly quadratic instruction system, general-

purpose register of eigth 16-bit × 16-bank
configuration

• Minimum instruction cycle 100ns at 20MHz operation (2.7 to 3.3V)

61µs at 32kMHz operation (2.2 to 3.3V)

• Incorporated ROM capacity 256K bytes

• Incorporated RAM capacity 10K bytes

• Peripheral functions

— A/D converter 8-bit 12 analog input, 2 channels successive approximation system,

automatic scanning function, (Conversion time: 3.4µs at 20MHz)

— Serial interface 128 -byte buffer RAM, 3 channels

8-stage FIFO, 1 channel (supports special mode master/slave)

—I2C bus interface 64-byte buffer RAM , 2 channels

(supports master/slave and automatic transfer mode)

— Timers 8-bit timer/counter, 2 channels (with timing output)

16-bit timer, 3 channels
— Real-time pulse generator 5-bit output, 1 channel (2-stage FIFO)
— Clock prescaler
— Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO

• Interruption 30 factors, 30 vectors, multi-interruption and priority selection possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP/LQFP

104-pin plastic LFLGA

• Piggy/evaluation chip CXP921000A

•

FLASH EEPROM incorporated version

CXP921F064A

Structure

Silicon gate CMOS IC

CMOS 16-bit Single Chip Microcomputer

– 1 –

E99707-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP921064A

100 pin QFP (Plastic) 100 pin LQFP (Plastic)

104 pin LFLGA (Plastic)

– 2 –

CXP921064A

Block Diagram

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE7

PF0 to PF3

PF4 to PF7

PG0 to PG7

PH6, PH7

PH0 to PH5

PI0 to PI7

PJ0 to PJ7

CS0

SO0

SI0

SCK0

SI1

CS1

SCK1

SO1

CS2

SO2

SI2

SCK2

TO

TMO

EC

RMC

PORT A

BUFFER

RAM

I

2

C BUS

INTERFACE

UNIT (CH1)

BUFFER

RAM

I

2

C BUS

INTERFACE

UNIT (CH0)

FIFO

SERIAL

INTERFACE

UNIT (CH3)

BUFFER

RAM

SERIAL

INTERFACE

UNIT (CH2)

BUFFER

RAM

SERIAL

INTERFACE

UNIT (CH1)

BUFFER

RAM

SERIAL

INTERFACE

UNIT (CH0)

8

8

PORT B

8

PORT C

8

PORT D

8

PORT E

8

PORT F

4

4

2

8

6

PORT G

8

PORT HPORT IPORT J

8

SPC950

CPU CORE

CLOCK GENERATOR/

SYSTEM CONTROLLER

ROM

256K BYTES

RAM

10K BYTES

PRESCALER/

TIME-BASE TIMER

SO3

SI3

SCK3

SCL0

SDA0

SCL1

SDA1

INT0

to INT7

KS0

to KS15

NMI

RST

TEX

TX

EXTAL

XTAL

V

DD

VSS

5

A/D

CONVERTER

(CH1)

A/D

CONVERTER

(CH0)

12 12

REMOCON

FIFO

16-BIT TIMER (CH2)

16-BIT TIMER (CH1)

16-BIT TIMER (CH0)

INTERRUPT CONTROLLER

AN0

to AN11

AN12

to AN23

RTO0

to RTO4

AV

REF0

AVSS

AVREF1

AVDD

XOUT

8-BIT TIMER/COUNTER (CH0)

8-BIT TIMER (CH1)

3

2

2

2

REALTIME PULSE

GENERATOR

FIFO

CLOCK PRESCALER

16

– 3 –

CXP921064A

Pin Assignment 1 (Top View) 100-pin QFP package

31 32 33 34 35 36 37 38 39 40 41 42 43 44 454647 48 49 50

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81828384858687888990919293949596979899

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

PE7

PF0

PF1/EC

PF2/CS0

PF3/SI0

PF4/SO0

PF5/SCK0

PF6/TO

PF7/TMO

RST

V

SS

XTAL

EXTAL

V

DD

PG0/CS1

PG1/SI1

PG2/SO1

PG3/SCK1

PG4/CS2

PG5/SI2

PJ0/AN4/KS8
AV

DD

AVREF1
AVREF0
AVss
AN3
AN2
AN1
PI7/AN0
PI6/NMI
PI5/INT7
PI4/INT6
PI3/INT5
PI2/INT4
PI1/INT3
PI0/INT2
PH7/INT1
PH6/INT0
PH5/XOUT
PH4/RTO4
PH3/RTO3
PH2/RTO2
PH1/RTO1
PH0/RTO0
Vss

51

52

53

54

55

56

TX
TEX
V

DD

PG7/SCK2
PG6/SO2

PB2/AN22
PB3/AN23

PB4/SI3

PB5/SO3

PB6/SCK3

PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1

PC4
PC5
PC6
PC7

V

SS

PD0/KS0
PD1/KS1
PD2/KS2
PD3/KS3
PD4/KS4
PD5/KS5
PD6/KS6
PD7/KS7

PE0

25
26
27
28
29

PE1
PE2
PE3
PE4
PE5

30

PE6

PB1/AN21

PB0/AN20

PA7/AN19

PA6/AN18

PA5/AN17

PA4/AN16

PA3/AN15

PA2/AN14

PA1/AN13

PA0/AN12

VSSVDD

NC

PJ7/AN11/KS15

PJ6/AN10/KS14

PJ5/AN9/KS13

PJ4/AN8/KS12

PJ3/AN7/KS11

PJ2/AN6/KS10

PJ1/AN5/KS9

100

Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM

incorporated version.

2. Vss (Pins 15, 41, 56 and 90) must be connected to GND.

3. VDD (Pins 44, 53 and 89) must be connected to VDD.
– 4 –

CXP921064A

Pin Assignment 2 (Top View) 100-pin LQFP package

31 32 33 34 35 36 37 38 39 40 41 42 43 44 454647 48 49 50

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81828384858687888990919293949596979899

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

PE7

PF0

PF1/EC

PF2/CS0

PF3/SI0

PF4/SO0

PF5/SCK0

PF6/TO

PF7/TMO

RST

V

SS

XTAL

EXTAL

V

DD

PG0/CS1

PG1/SI1

PG2/SO1

PG3/SCK1

PG4/CS2

PG5/SI2

PJ0/AN4/KS8

AVDDAVREF1

AVREF0
AVss
AN3
AN2
AN1
PI7/AN0
PI6/NMI
PI5/INT7
PI4/INT6
PI3/INT5
PI2/INT4
PI1/INT3
PI0/INT2
PH7/INT1
PH6/INT0
PH5/XOUT
PH4/RTO4
PH3/RTO3
PH2/RTO2
PH1/RTO1
PH0/RTO0
Vss

51

52

53

54

55

56

TX
TEX
V

DD

PB4/SI3

PB5/SO3

PB6/SCK3

PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1

PC4
PC5
PC6
PC7

V

SS

PD0/KS0
PD1/KS1
PD2/KS2
PD3/KS3
PD4/KS4
PD5/KS5
PD6/KS6
PD7/KS7

PE0

25

26 27 28 29

PE1
PE2
PE3

30

PE4

PE5

PE6

PB1/AN21

PB2/AN22

PB3/AN23

PB0/AN20

PA7/AN19

PA6/AN18

PA5/AN17

PA4/AN16

PA3/AN15

PA2/AN14

PA1/AN13

PA0/AN12

V

SS

VDD

NC

PJ7/AN11/KS15

PJ6/AN10/KS14

PJ5/AN9/KS13

PJ4/AN8/KS12

PJ3/AN7/KS11

PJ2/AN6/KS10

PJ1/AN5/KS9

100

PG7/SCK2

PG6/SO2

Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM

incorporated version.

2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.

3. VDD (Pins 42, 51 and 87) must be connected to VDD.

– 5 –

CXP921064A

Pin Assignment 3 (Top View) 104-pin LFLGA package

1

23

4

5

678

9

10

11

12

13 14

15 16 17

18 19 20

21

22

23 24

25

26

272829

30

31

32

33

34

353637

383940

41

42

43

44

45

464748

49

50

51

52 53

54 55

56 57 58

59 60 61

62 6364

656667

686970

7172

7374

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1 2 3 4 5 6 7 8 9 10 11 12 13

PB1 PA7 PA4 PA1 V

SS NC PJ5 PJ2 PJ0

AA

PB2 PB0 PA5 PA2 VDD PJ7 PJ4 PJ1 AVDD

BB

PB6 PB5 PB3 PA6 PA3 PA0 PJ6 PJ3 AVREF1 AVSS AN3

CC

PC0 PB7 PB4 AVREF0 AN2 AN1

DD

PC3 PC2 PC1 PI7 PI6 PI5

EE

PC6 PC5 PC4 PI4 PI3 PI2

FF

V

SS PC7 PD0 PI1 PH7 PI0

GG

PD1 PD2 PD3 PH4 PH5 PH6

HH

PD4 PD5 PD6 PH1 PH2 PH3

JJ

PD7 PE0 PE3 V

DD VSS PH0

KK

PE1 PE2 PE4 PF1 PF4 VSS VDD PG2 PG7 TEX TX

LL

PE5 PE7 PF2 PF5 PF7 EXTAL PG1 PG4 PG6

MM

PE6 PF0 PF3 PF6

RST

XTAL PG0 PG3 PG5

NN

1 2 3 4 5 6 7 8 9 10 11 12 13

Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM

incorporated version.

2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.

3. VDD (Pins 42, 51 and 87) must be connected to VDD.

– 6 –

CXP921064A

Pin Functions

Symbol

I/O

Functions

PA0/AN12
to PA7/AN19

Output / Input

(Port A)
8-bit output port.
(8 pins)

Output / Input
Output / Input

Output / Output
Output / I/O
Output / Input
I/O / I/O
I/O / I/O
I/O / I/O
I/O / I/O
I/O

(Port B)
8-bit output port.
(8 pins)

PB0/AN20
to PB3/AN23

PB4/SI3
PB5/SO3
PB6/SCK3
PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PC4 to PC7

PF0
PF1/EC
PF2/CS0

PF3/SI0
PF4/SO0
PF5/SCK0
PF6/TO
PF7/TMO

Input
Input / Input
Input / Input

Input / Input
Output / Output
Output / I/O
Output / Output
Output / Output

(Port C)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not

through program in 1-bit units.

(8 pins)

(Port D)
8-bit I/O port.
I/O can be specified in 1-bit units.
Can drive 5mA sink current
(VDD = 2.7 to 3.3V).
(8 pins)

PD0/KS0
to PD7/KS7

PE0 to PE7

I/O / Input

(Port E)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)

(Port F)
8-bit port.
Lower 4 bits are for input;
upper 4 bits are for output.
(8 pins)

I/O

Standby release input function can be
specified in 1-bit units.
(8 pins)

Analog input for A/D converter.
(12 pins)

Serial data (CH3) input.
Serial data (CH3) output.
Serial clock (CH3) I/O.
Remote control receive circuit input.
Data I/O of I2C bus interface (CH0).
Clock I/O of I2C bus interface (CH0).
Data I/O of I2C bus interface (CH1).
Clock I/O of I2C bus interface (CH1).

External event input for 8-bit
timer/counter.

Serial chip select (CH0) input.
Serial data (CH0) input.
Serial data (CH0) output.
Serial clock (CH0) I/O.
8-bit timer/counter output.
16-bit timer (CH0) output.

– 7 –

CXP921064A

Symbol

I/O

Functions

(Port G)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)

(Port J)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)

Standby release input
function can be specified in
1-bit units.
(8 pins)

I/O / Input
I/O / Input
I/O / Output
I/O / I/O
I/O / Input
I/O / Input
I/O / Output
I/O / Output

Output / Output
Output / Output
Input / Input

Input / Input
Input / Input

Input / Input
Input

I/O / Input /
Input

PG0/CS1
PG1/SI1
PG2/SO1
PG3/SCK1
PG4/CS2
PG5/SI2
PG6/SO2
PG7/SCK2
PH0/RTO0

to PH4/RTO4
PH5/XOUT
PH6/INT0

to PH7/INT1
PI0/INT2

to PI5/INT7
PI6/NMI
PI7/AN0

AN1 to AN3
PJ0/AN4/

KS8
to PJ7/AN11/
KS15

RST
AVDD
AVREF0
AVREF1
AVSS

VDD

VSS

NC

Input

Input
Input

(Port H)
8-bit port.
Lower 6 bits are for output;
upper 2 bits are for input.
(8 pins)

(Port I)
8-bit input port.
(8 pins)

Serial chip select (CH1) input.
Serial data (CH1) input.
Serial data (CH1) output.
Serial clock (CH1) I/O.
Serial chip select (CH2) input.
Serial data (CH2) input.
Serial data (CH2) output.
Serial clock (CH2) output.
Real-time pulse generator output.

(5 pins)
Clock output for clock prescaler buzzer.

External interrupt input.
(8 pins)

Non-maskable external interrupt input.

Analog input for A/D converter.
(12 pins)

Connects a crystal for main clock oscillation.
(When the clock is supplied externally, input it to EXTAL and input an
opposite phase clock to XTAL.)

Connects a crystal for sub clock oscillation.
(When the clock is supplied externally, input it to TEX and input an
opposite phase clock to TX.)

System reset. Active at "L" level.
Positive power supply for A/D converter.
Reference voltage input for A/D converter (CH0).
Reference voltage input for A/D converter (CH1).
GND for A/D converter.
Positive power supply.

(Connect all three VDD pins to positive power supply.)
GND

(Connect all four Vss pins to GND.)
NC.

(NC is used for FLASH EEPROM incorporated version.)

EXTAL
XTAL
TEX
TX

Input

Input

– 8 –

CXP921064A

I/O Circuit Format for Pins

Pin Circuit format After a reset

PA0/AN12
to PA7/AN19

Hi-Z

Internal data bus

Input protection
circuit

IP

RD

PA register

"0" after a reset

PASL register

"0" after a reset

A/D converter

Input multiplexer

PB0/AN20
to PB3/AN23

Hi-Z

Internal data bus

IP

RD

PB register

"0" after a reset

PBSL register

"0" after a reset

A/D converter

Input multiplexer

PB4/SI3
PB7/RMC

Hi-Z

Internal data bus

IP

RD

PB register

"0" after a reset

PBSL register

"0" after a reset

SI3, RMC

CMOS Schmitt input

– 9 –

CXP921064A

PB5/SO3

Hi-Z

PB register

"0" after a reset

SO3

MPX

PBSL register

"0" after a reset

SO3 output enable

Internal data bus

RD

0

1

PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1

Hi-Z

PC register

Underfined after a reset

PULC register

"0" after a reset

SDA0, SCL0, SDA1, SCL1

PCSL register

"0" after a reset

PCD register

"0" after a reset

SDA0, SCL0
SDA1, SCL1

CMOS Schmitt input

∗

Pull-up transistor

approximately 15kΩ (V

DD = 2.7 to 3.3V)

IP

MPX

Internal data bus

RD

∗

1
0

PB6/SCK3

Hi-Z

PB register

"0" after a reset

SCK3

MPX

PBSL register

"0" after a reset

SCK3 output enable

SCK3

Internal data bus

RD

CMOS Schmitt input

IP

0

1

Pin Circuit format After a reset

– 10 –

CXP921064A

PD0/KS0
to PD7/KS7

Hi-Z

PE0 to PE7

Hi-Z

IP

PD register

Underfined after a reset

PDD register

"0" after a reset

∗

Large current drive

5mA (V

DD = 2.7 to 3.3V)

Internal data bus

Standby release

RD

∗

IP

PE register

Underfined after a reset

PED register

"0" after a reset

Internal data bus

RD

Pin Circuit format After a reset

PC4 to PC7

Hi-Z

PC register

Underfined after a reset

PULC register

"0" after a reset

PCD register

"0" after a reset

∗

Pull-up transistor

approximately 15kΩ (V

DD = 2.7 to 3.3V)

IP

Internal data bus

RD

∗