Sony CXP88860, CXP88852 Datasheet

CXP88852/88860

CMOS 8-bit Single Chip Microcomputer

Description

The CXP88852/88860 is a CMOS 8-bit micro­computer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, VISS/ VASS circuit, 32kHz timer/counter,
remote control receiving circuit, VSYNC separator
and the measurement circuit which measure signals
of capstan FG amplifier and drum FG/PG amplifier
and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.

Also, CXP88852/88860 provides sleep/stop function
which enables to lower power consumption.

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation

122µs at 32kHz operation

• Incorporated ROM capacity 52K bytes (CXP88852)

60K bytes (CXP88860)

• Incorporated RAM capacity 1600 bytes (including PPG RAM)

• Peripheral function

— A/D converter 8 bits, 14 channels, successive approximation system

(Conversion time of 20µs/16MHz)

— Serial interface Incorporated 8-bit, 8-stage FIFO for data

(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel

— Timer 8-bit timer/counter, 2 channels

19-bit time base timer
32kHz timer/counter

— High precision timing pattern generation PPG 19 pins 32-stage programmable circuit

RTG 5 pins, 1 channel

— PWM/DA gate output 12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)

DA gate pulse output, 13 bits, 2 channels

— Analog signal input circuit Capstan FG amplifier circuit

Drum FG amplifier circuit
Drum PG amplifier circuit

PBCTL amplifier circuit
— CTL write/rewrite circuit Recording current control circuit
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1 channel
— VISS/VASS circuit Pulse duty auto detection circuit
— 32kHz timer/event counter 32kHz oscillation circuit, ultra-low speed instruction mode
— Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
— Tri-state output PPG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit

• Interruption 20 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP

• Piggyback/evaluation chip CXP88800 100-pin ceramic QFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Structure

Silicon gate CMOS IC

5-bit, 8-satge FIFO (RECCTL control), 1channel

100 pin QFP (Plastic)

– 1 –

E96515-ST

CXP88852/88860

Vss
V

DD

MP
RST

TX
TEX

XTAL
EXTAL

INT2
INT1/NMI

INT0

2

PA0 to PA7
8

PORT A

CLOCK

SPC700

NMI

2

GENERATOR/

CPU CORE

PB0 to PB7

8

PC0 to PC7
8

PORT B

SYSTEM CONTROL

PD0 to PD7

PE0, 1, 6, 7

PE2 to PE5
4

4

8

PORT C

PORT D

RAM

1600 BYTES

ROM

52K/60K BYTES

INTERRUPT CONTROLLER

2

2

PORT E

2

PF4 to PF7

PF0 to PF3

4

4

PORT F

PRESCALER/

TIME BASE TIMER

3

PG0, 1

2

PORT G

32kHz

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PH0 to PH7

8

PORT H

2

PI0 to PI7
8

PORT I

CH1

FIFO

GENERATOR

REALTIME PULSE

CH0

RAM

PATTERN

GENERATOR

PROGRAMABLE

4

2

5

19

RTO3 to RTO7

PPO0 to PPO18

5

AVss

AV

REF

AV

DD

A/D CONVERTER

14

AN0 to AN13

Block Diagram

FIFO

(CH0)

SERIAL

INTERFACE UNIT

SI0

CS0

SO0

SCK0

(CH1)

8 BIT TIMER/COUNTER1

8 BIT TIMER/COUNTER 0

SERIAL INTERFACE UNIT

EC

SELECT

TO

SO1

SCK1

EC

SYNC

SI1

CONTROL

SERVO INPUT

V SYNC SEPARATOR

GAIN

AMP

CONTROL

DFG

CFG

EXI0

EXI1

DPG

– 2 –

FIFO

REMOCON INPUT

RMC

CTLAMP

COUNTER

PULSE WIDTH

14 BIT PWM GENERATOR

VISS/VASS

DDO

PWM

PWM0

CTL R/W CONTROL

12 BIT PWM GENERATOR CH0

12 BIT PWM GENERATOR CH1

PSEUDO HSYNC GENERATOR

2

ADJ

HGO

DAA1

DAA0

PWM1

CTLCIN

RECCTL

AMPV

SS

AMPV

DD

Pin Assignment (Top View)

PA0/PPO0/HGO

PB7/PPO15

PB6/PPO14

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA6/PPO6

PA5/PPO5

PA4/PPO4

DD

PA7/PPO7

V

NC

CXP88852/88860

SS

TX

V

PE0/SCK1

TEX

PE1/SO1

PE3/SYNC

PE2/SI1

PE4/EXI0

PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PI7
PI6
PI5
PI4
PI3
PI2

PI1/EC/INT2

PI0/INT0

PD7/SI0

PD6/SO0

PD5/SCK0

PD4/CS0

PD3/TO/DDO/ADJ/SRVO

PD2/PWM

PD1/RMC

PD0/INT1/NMI

10

12
13
14
15
16

19

18

20

23
24

26

29
30

11

17

21
22

25

27
28

100

99

98

1

2
3
4

5
6
7
8
9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

41

90

89

42

88

43

44

87

86

45

46

85

47

84

48

83

82

49

81

50

80

78
77
76
75
74

70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

79

73
72
71

PE5/EXI1
PE6/PWM0/DAA0
PE7/PWM1/DAA1
CFG
DFG
DPG
VREFOUT

SS

AMPV
CTLSAMPI
CTLFAMPO
CTLAG
CTLAMP (+)
CTLAMP (–)
CTLCIN (–)
CTLCIN (+)
RECCTL (+)
RECCTL (–)

DD

AMPV
RECCAP

DD

V
AN0/ANOUT
AN1
AN2
AN3
PF0/AN4
PF1/AN5

DD

AV
AVREF
AVSS
PF2/AN6

SS

MP

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

V

XTAL

Note) 1. NC (Pin 90) is always connected to VDD.

2. VDD (Pins 61 and 89) are both connected to VDD

3. Vss (Pins 41 and 88) are both connected to GND.

4. MP (Pin 39) must be connected to GND.

– 3 –

EXTAL

PG1/AN13

PF6/AN10

PF7/AN11

PG0/AN12

PF4/AN8

PF5/AN9

PF3/AN7

Pin Description

Symbol I/O Description

CXP88852/88860

PA0/PPO0
/HGO

PA1/PPO1

to

PA7/PPO7

PB0/PPO8

to

PB7/PPO15

PC0/PPO16

to

PC2/PPO18

PC3/RTO3

to

PC7/RTO7
PD0/INT1/

NMI
PD1/RMC
PD2/PWM
PD3/TO

DDO/ADJ
SRVO

PD4/CS0

Output/Real-time
output/Output

Output/
Real-time output

Output/
Real-time output

I/O/
Real-time output

I/O/
Real-time output

I/O/Input/Input
I/O/Input

I/O/Output
I/O/Output/Output/

Output/Output

I/O/Input

(Port A)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
(8 pins)

(Port B)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
Tri-state control is possible.
(8 pins)

(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data is gated with PPO or
RT contents by OR-gate
and they are output.
(8 pins)

(Port D)
8-bit I/O port. I/O can be
set in a unit of single bits.
(8 pins)

Pseudo HSYNC output pin.

Programmable pattern generator (PPG)
output. Functions as high precision real­time pulse output port.

(19 pins)

PA0 can be tri-state controlled with PPG.

Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
(5 pins)

Input pin to request external interruption
and non-maskable interruption.

Remote control receiving circuit input pin.
14-bit PWM output pin.
Timer/counter, CTL duty detector, 32kHz

oscillation adjustment and servo amplifier
output pin.

Serial chip select (CH0) input pin.

PD5/SCK0
PD6/SO0

PD7/SI0
PE0/SCK1
PE1/SO1

PE2/SI1
PE3/SYNC
PE4/EXI0

PE5/EXI1
PE6/PWM0/

DAA0
PE7/PWM1/

DAA1

I/O/I/O
I/O/Output

I/O/Input
Output/I/O
Output/Output

Input/Input
Input/Input
Input/Input

Input/Input
Output/Output

Output/Output

(Port E)
8-bit port. Bits 2, 3, 4 and 5
are for inputs; bits 0, 1, 6
and 7 are for outputs.
(8 pins)

– 4 –

Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.

Serial data (CH0) input pin.
Serial clock (CH1) I/O pin
Serial data (CH1) output pin

Serial data (CH1) input pin
Composite sync signal input pin.

External input pin for FRC capture unit.
(2 pins)

PWM output pin.
(2 pins)

DA gate pulse
output pin.
(2 pins)

CXP88852/88860

Description I/O
AN0/ANOUT
AN1 to AN3

Input/Output
Input

PF0/AN4

to

Input/Input

PF3/AN7
PF4/AN8

to

Output/Input

PF7/AN11
PG0/AN12

PG1/AN13

PH0 to PH7

PI0/INT0

PI1/EC/
INT2

Input/Input

Output

I/O/Input

I/O/Input/Input

Description

Analog circuit internal
waveform output pin.

(Port F)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits are standby release input
pins.
(8 pins)

Analog input pin for
A/D converter.
(14 pins)

(Port G)
2-bit input port.
(2 pins)

(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)

(Port I)
8-bit I/O port. I/O can be

Input pin to request external interruption.
Active when falling edge.

set in a unit of single bits.
Function as standby
release input can be set in
a unit of single bits.
(8 pins)

External event input
pin for timer/counter.

Input pin to request
external interruption.
Active when falling

edge.
PI2 to PI7
CFG
DFG
DPG
RECCTL (+)

RECCTL (–)
CTLCIN (+)

CTLCIN (–)
CTLAMP (+)

CTLAMP (–)
CTLFAMPO
CTLSAMPI

RECCAP

VREFOUT
CTLAG

AMPVSS

I/O
Input
Input
Input

I/O

Output

Input
Output

Input
I/O

Output
Output

Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
RECCTL signal output pin.

(2 pins)

PBCTL signal input pin.
(2 pins)

Connected to RECCTL (+) and RECCTL (–) with the internal switch for
playback. (2 pins)

Input PBCTL signal with capacitor coupled.
(2 pins)

PBCTL signal 1st amplifier output.
PBCTL signal 2nd amplifier input.
Capacitor connecting pin for the slope setting of the CTL writing

trapezoidal wave.
Capacitor connecting pin for the VREF level smoothing of DPG, DFG

and CFG.
Capacitor connecting pin for the CTL and AGND smoothing.
Analog signal input circuit GND pin.

AMPVDD

Analog signal input circuit power supply pin.

– 5 –

CXP88852/88860

Symbol I/O
EXTAL
XTAL

TEX
TX

RST

Input
Output

Input
Output

Input

NC
MP

Input

AVDD
AVREF

Input

AVSS
VDD
VSS

Description

Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input it to EXTAL pin and input the opposite phase
clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open.
(In this time, feedback resistor is not removed.)

System reset pin; Low level active.
NC pin. Connect this pin to VDD for normal operation.
Test mode input pin. Always connect to GND.
Positive power supply pin for A/D converter.
Reference voltage input pin for A/D converter.
GND pin for A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.

– 6 –

Input/Output Circuit Formats for Pins

A

A

AAA

AAA
A

CXP88852/88860

PA0/PPO0/
HGO

1 pin

PA1/PPO1

1 pin

Circuit format

Port A

HOUT
PPO0

PA0

Data bus

RD (Port A)

HOUTE

Output becomes active from high impedance by
data writing to port.

PPO1

PPG control status register bit 0
Tri-state control selection

PPO1

PA1

Data bus

HSEL

A

MPX

A

When resetPin

Hi-Z

MPX

Hi-Z

PA2/PPO2

to

PA7/PPO7

6 pins

PB0/PPO8

to

PB7/PPO15

RD (Port A)

Output becomes active from high impedance by data
writing to port.

Port A

PPO data

Port A data

Data bus

RD (Port A)

Port B

PPO data

Port B data

Data bus

Hi-Z

Output becomes active from high impedance
by data writing to port.

Hi-Z

RD (Port B)

Port B tri-state
control

8 pins

– 7 –

CXP88852/88860

A

AA

PC0/PPO16

to

PC2/PPO18

PC3/RTO3

to

PC7/RTO7

8 pins

PD0/INT1/
NMI
PD1/RMC
PD4/CS0
PD7/SI0

Port C

Data bus

Port D

PPO, RTO data

Port C data

Port C direction

RD (Port C)

RD (Port C direction)

Data bus

Circuit format

Port D data

Port D direction

Input protection circuit

IP

IP

When resetPin

Hi-Z

Hi-Z

4 pins

PD2/PWM
PD3/TO/
DDO/ADJ/
SRVO

PD1: Remote control circuit
PD0: Interruption circuit
PD4, 7: Serial CH0

Port D



PD2: 14-bit PWM
PD3:  Timer/counter, CTL duty
 detection circuit,
 32kHz timer, 
 amplifier circuit

Port D direction

Data bus

RD (Port D)

RD (Port D)

Port D function
select

Port D data

MPX

A

Schmitt input

Hi-Z

IP

2 pins

– 8 –

CXP88852/88860

PD5/SCK0
PD6/SO0

2 pins

PE0/SCK1

Port D

Data bus

Port E

Port D function
select

SIO CH0

Port D data

Port D direction

RD (Port D)

Port/SCK output
select

SIO CH1

Port E data

Circuit format

MPX

SIO CH0

MPX

MPX

Note)
PD5 is schmitt input
PD6 is inverter input

When resetPin

Hi-Z

IP

Hi-Z

1 pin

PE1/SO1

1 pin

PE2/SI1
PE3/SYNC
PE4/EXI0
PE5/EXI1

Port E

Data bus

Port E

Data bus

RD (Port E)

Port E function
select

SIO CH1

Port E data

RD (Port E)

IP

Schmitt input

SIO CH1

MPX

Hi-Z control

Hi-Z control

PE2: SIO CH1
PE3
PE4 Servo input
PE5

Data bus

IP

Hi-Z

Hi-Z

4 pins

RD (Port E)

Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected

with the mask oprion.

– 9 –

CXP88852/88860

Pin

PE6/PWM0/
DAA0
PE7/PWM1/
DAA1

2 pins

AN0/ANOUT

1 pin

Port E

Data bus

Port E

Port/DA/PWM
select

DA gate output or
PWM output

Port E data

RD (Port E)

Analog output control

Circuit format

MPX

Input multiplexer

IP

When reset

High level

Hi-Z control

A/D converter

Hi-Z

From amplifier circuit

AN1

to

AN3

3 pin

PFO/AN4

to

PF3/AN7

4 pins

PF4/AN8

to

PF7/AN11

Port F

Port F

Port F data

Data bus

RD (Port F)

Input multiplexer

IP

Input multiplexer

IP

A/D converter

A/D converter

Hi-Z

Hi-Z

Data bus

RD (Port F)

IP

Hi-Z

4 pins

Port/AD select

Input multiplexer

A/D converter

– 10 –