Sony CXP881P60 Datasheet

Description

The CXP881P60 is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface,
timer/counter, time base timer, high precision timing
pattern generation circuits, PWM output, PWM for
tuner, VISS/VASS circuit, 32kHz timer counter,
remote control reception circuit, fluorescent display
panel (FDP) controller/driver, VSYNC separator and
the measurement circuit which measures signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, PROM, RAM and I/O port. They are integrated
into a single chip.

Also, CXP881P60 provides sleep/stop function
which enables to lower power consumption and
ultra-low speed instruction mode in 32kHz operation.

The CXP881P60 is the PROM-incorporated
version of the CXP88160 with built-in mask ROM.
This provides the additional feature of being able to
write directly into the program. Thus, it is most suit­able for evaluation use during system development
and for small-quantity production.

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation

122µs at 32kHz operation

• Incorporated PROM capacity 60K bytes

• Incorporated RAM capacity 1296 bytes (including fluorescent display area)

• Peripheral function

— A/D converter 8 bits, 8 channels, successive approximation system

(Conversion time of 20µs/16MHz)

— Serial interface Incorporated 8-bit 8-stage FIFO for data

(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel

— Timer 8-bit timer/counter, 2 channel

19-bit time base timer
32kHz timer/counter

— High precision timing pattern generator PPG 8 pins, 21-stage programmable circuit

RTG 5 pins, 2 channels

— PWM/DA gate output 12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)

DA gate pulse output, 13 bits, 4 channels
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14 bits, 1 channel
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
— Fluorescent display panel controller/driver Maximum 144-segment display possible

Hardware key scan function (Maximum 16 x 3 key matrix available)

Dimmer function

High voltage drive output (40V)

Incorporated pull-down resistor (mask option)
— Tri-state output PPG 1 pin, RTG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit

• Interruption 22 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP

– 1 –

CXP881P60

100 pin QFP (Plastic)

E95325-ST

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Structure

Silicon gate CMOS IC

– 2 –

CXP881P60

SO1

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE1

PE2 to PE7

PF0 to PF3

PF4 to PF7

PG0 to PG7

PI1 to PI7

Vss
V

DD

XTAL
EXTAL

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

1296 BYTES

SPC700

CPU CORE

PROM

60K BYTES

INTERRUPT CONTROLLER

2

2

32kHz

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PROGRAMABLE

PATTERN

GENERATOR

RAM

2

5

8

AVss

AV

REF

AV

DD

2

A/D CONVERTER

SERIAL

INTERFACE UNIT

(CH0)

FIFO

8 BIT TIMER/COUNTER 0

V SYNC SEPARATOR

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

SERVO INPUT

CONTROL

CAPSTAN

DRUM

CTL

2

3

2

12 BIT PWM GENERATOR CH1

DAB1

DAA1

PWM1

DAB0

DAA0

PWM0

PWM

RMC

PBCTL

DPG

DFG

CFG

EXI1

EXI0

SYNC1

SYNC0

TO/DDO

EC0

SCK1

SI1

SCK0

SO0

SI0

CS0

AN0 to AN7

REALTIME

PULSE

GENERATOR

INT2

INT0

INT1/NMI

8

4

PORT A

8

PORT B

8

PORT C

8

PORT D

6

2

PORT E

4

4

PORT F

8

PORT G

3

PORT H

7

PORT I

PH0 to PH2

TEX

TX

MP

PRESCALER/

TIME BASE TIMER

VISS/VASS

REMOCON INPUT

FIFO

SERIAL INTERFACE UNIT

(CH1)

CH0

CH1

PPO0 to PPO7

RTO3 to RTO7

8 BIT TIMER/COUNTER1

EC

SELECT

FDP

CONTROLLER

/DRIVER

RST

4

RAM

8
88

S0 to S7

T0 to T7

V

FDP

T8/S15

T15/S8

to

PSEUDO HSYNC GENERATOR

HGO

Vpp

ADJ

2

4

EC1

EC2

Block Diagram

– 3 –

CXP881P60

Pin Configuration (Top View)

PB0
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3

PC2

PC1

PC0
PA7/PPO7

(HAMP) PA6/PPO6

(ROTA) PA5/PPO5

(RF-PLS) PA4/PPO4

PA3/PPO3
PA2/PPO2
PA1/PPO1

HGO/PA0/PPO0

PF7

SI1/PF6

SO1/PF5

SCK1/PF4

PF3/AN7
PF2/AN6
PF1/AN5
PF0/AN4

AN3

AN2

AVREF

AVSS
AVDD

PI6/SO0
PI7/SI0
VFDP
PD0/S0
PD1/S1
PD2/S2
PD3/S3
PD4/S4
PD5/S5
PD6/S6
PD7/S7
S8/T15
S9/T14
S10/T13
S11/T12
S12/T11
S13/T10
S14/T9
S15/T8
T7
T6
T5
T4
T3
T2
T1
T0
PE0/INT0 (ENV-DET)
PE1/EC0/INT2
PWM0/PE2

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PH0/KR0

PH1/KR1

PH2/KR2

Vpp

V

DD

V

SS

TX

TEX

PI1/RMC

PI2/PWM

PI3/TO/DDO/ADJ

PI4/INT1/NMI/CS0

PI5/SCK0

AN1

AN0

PG7/EXI1

PG6/EXI0

PG5/SYNC1

PG4/SYNC0/EC2

PG3/PBCTL/EC1

PG2/DPG

MP

RST

V

SS

XTAL

EXTAL

PG1/DFG

PG0/CFG

DAB1/PE7

DAB0/PE6

PE5/DAA1

PE4/DAA0

PE3/PWM1

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70
69
68
67

63

64

65

66

61

62

71

72

73

74

75

76

77

78

79

80

2

3

4

5
6
7
8
9

10

11
12
13
14
15
16
17

18
19

20

21

22

23

24
25

26

27

28
29
30

1

81

82

83

84

88

87

86

85

89

90

100

99

98

97

96

95

94

91

92

93

Note) 1. Vpp (Pin 90) is always connected to VDD.

2. VSS (Pins 41 and 88) are both connected to GND.

3. MP (Pin 39) must be connected to GND.

– 4 –

CXP881P60

Analog input pins to A/D converter. (8 pins)

(Port F)
Lower 4 bits are for
inputs; upper 4 bits are
for I/O. I/O can be set
in a unit of single bits.
(8 pins)

Output/Real time
output/Output

I/O/
Real time output

Output/
Real time output

Output
I/O

I/O/
Real time output

Output

Output/Output

Output/Output

Input/Input

Input/Input/Input

Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input

Input/Input

I/O/I/O
I/O/Output
I/O/Input
I/O

(Port A)
PA0 and PA5 to PA7 are
for outputs; PA1 to PA4
are for I/O. I/O can be
set in a unit of single bits.
Data is gated with PPO
content by OR-gate and
they are output.
(8 pins)

8-bit output port. Tri-state can be controlled.
(8 pins)

(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data is gated with RTO
content by OR-gate and
they are output. (8 pins)

FDP timing signal output pin. (8 pins)
Output pins for FDP timing signal and segment signal.

(8 pins)
(Port D)

8-bit output port.
(8 pins)

(Port E)
8-bit port.
Lower 2 bits are for
inputs; upper 6 bits are for
outputs.
(8 pins)

Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.

Trigger pulse
input pin for head
switching output.

External event
input pin for
timer/counter.

Input pin to request
external interruption.
Active when falling edge.

Input pin to request
external interruption.
Active when falling edge.

FDP segment signal output pin. (8 pins)

PWM output pins.
(2 pins)

DA gate pulse output pins.
(4 pins)

Programmable pattern generator (PPG)
output. Functions as high precision real­time pulse output port.
(8 pins)

Head switching
output pins. (2 pins)

Pseudo HSYNC
output pin.

Real-time pulse generator (RTG) output.
Functions as high precision real-time pulse
output port.
(5 pins)

Symbol I/O Description

PA0/PPO0/
HGO

PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7

PB0 to PB7
PC0 to PC2

PC3/RTO3

to

PC7/RTO7

T0 to T7
T8/S15

to

T15/S8
PD0/S0

to

PD7/S7

PE0/INT0

PE1/EC0/
INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4

to

PF3/AN7
PF4/SCK1
PF5/SO1
PF6/SI1
PF7

Pin Description

– 5 –

CXP881P60

PG0/CFG
PG1/DFG
PG2/DPG

PG3/
PBCTL/EC1

PG4/
SYNC0/EC2

PG5/SYNC1
PG6/EXI0
PG7/EXI1

PH0/KR0

to

PH2/KR2
PI1/RMC

PI2/PWM
PI3/TO/

DDO/ADJ
PI4/INT1/

NMI/CS0
PI5/SCK0

PI6/SO0
PI7/SI0

EXTAL
XTAL
TEX
TX

RST
MP

VFDP
AVDD

AVREF
AVss
VDD

Vpp
Vss

Input/Input
Input/Input
Input/Input

Input/Input/Input

Input/Input/Input

Input/Input
Input/Input
Input/Input

I/O/Input

I/O/Input
I/O/Input
I/O/Output/

Output/Output

I/O/Input/
Input/Input

I/O/I/O
I/O/Output
I/O/Input

Input
Output
Input
Output

Input
Input

Input

Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.

Playback CTL input pin.

Composite sync signal input pins.

External input pins for FRC capture unit.

Key return input signal for key scanning at FDP
segment signal. (3 pins)

External event
input pin for
timer/counter.

External event
input pin for
timer/counter.

(Port G)
8-bit input port.
(8 pins)

(Port H)
3-bit I/O port.
(3 pins)

Remote control reception circuit input pin.
14-bit PWM output pin.
Timer/counter, CTL duty detection, 32kHz oscillation

adjustment output pin.
Input pin to request external interruption,

non-maskable interruption and for serial chip select
(CH0). Active when falling edge.

Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.

(Port I)
7-bit I/O port.
I/O can be
set in a unit of
single bits.
(7 pins)

Connecting pin of crystal oscillator for system clock.
When supplying the external clock, input the external clock to EXTAL
pin and input opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock.
When used as event counter, input to TEX pin and leave TX pin open.
(In this time, feedback resistor is not removed.)

System reset pin of active "L" level.
Test mode pin. Always connect to GND.
FDP voltage supply pin when specifying internal resistor by mask

option.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
Positive power supply pin for incorporated PROM writing connect to

VDD during normal operation.
GND pin. Connect both Vss pins to GND.

Symbol I/O Description

– 6 –

CXP881P60

A

Port A

1 pin

1 pin

Hi-Z

Hi-Z

Hi-Z

When reset

PA0/PPO0/
HGO

PA1/PPO1

PA2/PPO2

to

PA4/PPO4

Port A

3 pins

3 pins

Hi-Z

PA5/PPO5

to

PA7/PPO7

Input/Output Circuit Formats for Pins

Port A

Pin

Circuit format

Data bus

RD
(Port A)

PA0

Data bus

RD (Port A)

PA1 direction

PA1

IP

PPO1

PPG control status
register bit 0
Tri-state control selection

PPO1

MPX

MPX

PPO0

HOUT

HSEL

HOUTE

HSEL

Output becomes active from high impedance
by data writing to port register.

PPO data

Data bus

Output becomes active from high impedance
by data writing to port register.

Port A data

RD (Port A)

Data bus

PPO data

Port A data

Port A direction

RD (Port A)

IP

– 7 –

CXP881P60

Port C

1 pin

8 pins

Hi-Z

Hi-Z

Hi-Z

PB0

to

PB7

PC4/RTO4

PC0

to

PC2

Port C

3 pins

1 pin

Hi-Z

PC3/RTO3

Port B

Data bus

RD (Port C)

PC3 direction

PC3

IP

RTO3

Data bus

RD (Port C)

PC4 direction

PC4

IP

RTO4

RTG interruption
control register bit 7
Tri-state control selection

RTO4

Data bus

RD (Port C)

Port C direction

Port C data

IP

When resetPin

Circuit format

Data bus

Port B tri-state
control

Port B data

RD (Port B)

– 8 –

CXP881P60

Port D

8 pins

3 pins

Hi-Z

Hi-Z

Hi-Z

PC5/RTO5

to

PC7/RTO7

T8/S15

to

T15/S8

PD0/S0

to

PD7/S7

8 pins

8 pins

Hi-Z

T0 to T7

Port C

Output selection control signal
("0" when reset)

Timing output data

VFDP

Pull-down resistor

High voltage drive
transistor

Output selection control signal
("0" when reset)

Timing output data

VFDP

Pull-down resistor

High voltage drive
transistor

Segment output data

Output selection control signal
("0" when reset)

Data bus

RD (Port D)

Port D data

Segment output data

High voltage drive
transistor

When resetPin

Circuit format

Data bus

Port C data

Port C direction

RD (Port C)

RTO data

IP