Sony CXL5514P, CXL5514M Datasheet
CMOS-CCD 1H Delay Line for PAL
CXL5514M/P
Description
The CXL5514M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL signals including
the external lowpass filter.
Features
• Single 5V power supply
• Low power consumption
• Built-in peripheral circuit
• Built-in tripling PLL circuit
• Sync tip clamp mode
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD +6 V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5514M 350 mW
CXL5514P 480 mW
Recommended Operating Range (Ta = 25°C)
VDD 5V ± 5%
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.
• Clock frequency fCLK 4.433619MHz
• Input clock waveform Sine wave
CXL5514M CXL5514P
8 pin SOP (Plastic) 8 pin DIP (Plastic)
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 575mVp-p (Max.)
(at internal clamp condition)
Functions
• 848-bit CCD register
• Clock driver
• Auto-bias circuit
• Sync tip clamp circuit
• Sample and hold circuit
• Tripling PLL circuit
• Inverted output
Structure
CMOS-CCD
)
Block Diagram and Pin Configuration (Top View)
V
DD VCO OUT VCO IN CLK
8
Auto-bias circuit
Clamp circuit
1
IN AB OUT V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
7
CCD
(848 bit)
Output circuit
(S/H 1 bit)
2
6
3
5
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
4
SS
– 1 –
E94903-ST
Pin Description
Pin No. Symbol I/O Description Impedance
CXL5514M/P
1
2
3
4
5
6
7
8
IN
AB
OUT
VSS
CLK
VCO IN
VCO OUT
VDD
Electrical Characteristics
Item
Symbol
Supply current
IDD
I
O
O
—
O
—
Signal input
Auto-bias DC output
Signal output
GND
I
Clock input (fsc)
I
VCO input
VCO output (3fsc)
5V power supply
>10KΩ
40 to 500Ω
>10KΩ
(Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p, sine wave)
See “Electrical Characteristics Test Circuit”.
SW conditions
Conditions
Min.
Typ.
Max. Unit
NOTE
12
—
a — 10 15 20 mA 1
Low frequency gain
Frequency response
Differential gain
Differential phase
S/H pulse coupling
S/N ratio
GL
fR
DG
DP
CP
SN
200kHz
500mVp-p
Sine wave
200kz ←→ 4.434MHz
150mVp-p Sine wave
5-staircase wave
(See Note 4.)
5-staircase wave
(See Note 4.)
No signal input
50% white video signal
(See Note 6.)
a b –2 0 2 dB 2
b ←→ c
b –2.7 –1.7 –0.7 dB 3
dc035%4
d c 0 3 5 degree 4
f a — — 350 mVp-p 5
e d 52 56 — dB 6
– 2 –
NOTE
1. This is the IC supply current value during clock and signal input.
2. GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
CXL5514M/P
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
3. Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at OUT pin when a
150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p,
4.434MHz sine wave is fed to the same, calculation is made according to the following formula.
fR = 20 log
OUT pin output voltage (4.434MHz) [mVp-p]
[dB]
OUT pin output voltage (200kHz) [mVp-p]
4. In Fig. below, the differential gain (DG) and the differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
150mV
350mV
500mV
150mV
1H 64µs
5. Leakage of internal clock components and related high frequency component to the output signal, during
no signal input, is tested.
Test value
[mVp-p]
– 3 –
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