Sony CXL5512P, CXL5512M Datasheet
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5512M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for NTSC signals including
the external lowpass filter.
Features
• Single 5 V power supply
• Low power consumption
• Built-in peripheral circuit
• Built-in tripling PLL circuit
• Sync tip clamp mode
CXL5512M/P
CXL5512M CXL5512P
8 pin SOP (Plastic) 8 pin DIP (Plastic)
Input Signal Amplitude
VSIG 500mVp-p (typ.), 572 mVp-p (max.)
(at internal clamp condition)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VDD +6 V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5512M 350 mW
CXL5512P 480 mW
Recommended Operating Range (Ta=25 ˚C)
VDD 5 V±5 %
Recommended Clock Conditions (Ta=25 ˚C)
• Input clock amplitude VCLK 400mVp-p (Typ.)
• Clock frequency fCLK 3.579545 MHz
• Input clock waveform Sine wave
Block Diagram and Pin Configuration
VDD CLK VCO IN
VCO OUT
Functions
• 680-bit CCD register
• Clock driver
• Auto-bias circuit
• Sync tip clamp circuit
• Sample and hold circuit
• Tripling PLL circuit
• Inverted output
Structure
CMOS-CCD
5678
Auto-bias circuit
Clamp circuit
1 2 3 4
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CCD
(680bit)
Output circuit
(S/H 1 bit)
—1—
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
VSS OUTABIN
E93Y19-TE
Pin Description
Pin No. Symbol I/O Description Impedance
1
2
3
4
5
6
7
8
IN
AB
OUT
VSS
CLK
VCO IN
VCO OUT
VDD
I
Signal input
O
Auto-bias DC output
O
Signal output
–
GND
I
Clock input (fsc)
I
VCO input
O
VCO output (3fsc)
–
5 V power supply
>10 KΩ
40 to 500 Ω
>10 KΩ
Electrical Characteristics
(Ta=25°C, VDD=5 V, fCLK=3.579545 MHz, VCLK=400mVp-p, sine wave)
See “Electrical Characteristics Test Circuit”.
CXL5512M/P
Item Symbol Conditions
Supply current
Low frequency gain
Frequency response
Differential gain
Differential phase
S/H pulse coupling
IDD
GL
fR
DG
DP
CP
———
200kHz
500mVp-p
Sine wave
200kz ↔ 3.57 MHz
150mVp-p Sine wave
5-staircase wave
(See Note 4.)
5-staircase wave
(See Note 4.)
No signal input
SW conditions
Min. Typ. Max. Unit Note
12
a–61220mA1
a b -2 0 2 dB 2
b ↔ c b –2.5 –1.5 –0.5 dB 3
dc035%4
d c 0 3 5 degree 4
f a — — 350 mVp-p 5
S/N ratio
SN
50 % white video signal
(See Note 6.)
—2—
e d 52 56 — dB 6
NOTE
1 This is the IC supply current value during clock and signal input.
2 GL is the output gain of OUT pin when a 500 mVp-p, 200 kHz sine wave is fed to IN pin.
CXL5512M/P
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
3 Indicates the dissipation at 3.58 MHz in relation to 200 kHz. From the output voltage at OUT pin when a
150 mVp-p, 200 kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150 mVp-p,
3.58 MHz sine wave is fed to the same, calculation is made according to the following formula.
fR = 20 log
OUT pin output voltage (3.58 MHz) [mVp-p]
[dB]
OUT pin output voltage (200 kHz) [mVp-p]
4 In Fig. below, the differential gain (DG) and the differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
143mV
357mV
500mV
143mV
1H 63.56µS
5 Leakage of internal clock components and related high frequency component to the output signal, during
no signal input, is tested.
Test value
(mVp-p)
—3—
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