Sony CXG1015N Datasheet
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E97749-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VDD 6V
•Voltage between gate and source
Vgs0 1.5 V
• Drain current IDD 550 mA
• Power dissipation PD 3W
•Channel temperature Tch 150 °C
• Operating temperature Topr –35 to +85 °C
• Storage temperature Tstg –65 to +150 °C
Description
The CXG1015N is a power amplifier/antenna
switch MMIC for PHS. This is designed using the
Sony’s GaAs J-FET process and operates at a
single positive power supply.
Features
• Single positive power supply 3.0 V
• Output power 20.2 dBm
(Antenna switch transfer output pin power)
• Low current consumption 160 mA
(Output power of 20.2 dBm)
• High power gain 39 dB Typ.
(Output power of 20.2 dBm)
• Low insertion loss 0.5 dB Typ.
• Small mold package 20-pin SSOP
(Pin interval of 0.5 mm pitch)
Structure
GaAs J-FET MMIC
Applications
• Power amplifiers for PHS
• Antenna switches for PHS
Power Amplifier/Antenna Switch for PHS
20 pin SSOP (Plastic)
CXG1015N
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CXG1015N
Electrical Characteristics
Power Amplifier + Antenna Switch Transfer Block
VDD=3.0 V, VCTL=2.0 V, f=1.90 GHz (Ta=25 °C)
∗ Current consumption
∗ Gate voltage adjustment value
Output power
(Power Amplifier + Antenna Switch Transfer Block)
∗ Power gain
∗ Adjacent channel leak power ratio
(600 kHz±100 kHz)
Item Symbol Min. Typ. Max. Unit
IDD 160 mA
VGG2 0 0.25 0.7 V
POUT 20.2 dBm
GP 35.5 39 42 dB
ACPR600 –59 –54 dBc
∗ Values where VGG1 and VGG2 are adjusted so that IDD becomes 160 mA when the power amplifier output
pin and the antenna switch transfer input pin are connected on the Sony’s recommended evaluation board
and the output power on the antenna switch transfer output pin is 20.2 dBm.
Antenna Switch Receive Block
VCTL(L)=0 V, VCTL(H)=3.0 V (Ta=25 °C)
Insertion loss
Isolation
Control pin current
Item Symbol Min. Typ. Max. Unit
IL 0.5 0.8 dB
ISO 20 24 dB
ICTL 40 100 µA
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CXG1015N
Block Diagram
PAIN
VDD1 VDD2
V
GG1 VPCTL VGG2
V
DD3 RX
TXPAOUT
ANT
VCTL2
V
CTL1
Pin Configuration Antenna Switch Operation
1
PAIN
GND
V
DD1
GND
V
DD2
GND
V
DD3
GND
R
X
VCTL2
20
VGG1
VP
CTL
GND
V
GG2
GND
PA
OUT
GND
T
X
VCTL1
ANT
Recommended Current Adjustment Method
(1)VGG2/PIN separate adjustment
(VGG2 adjustment 1) (PIN adjustment 1) (VGG2 adjustment 2) (PIN adjustment 2)
When the RF input
(PIN) off, the current
consumption (IDD) is
adjusted to 160 mA.
The output power
(POUT) is adjusted
to 20.2 dBm.
The current
consumption (IDD)
is finely adjusted to
160 mA.
The output power
(POUT) is finely
adjusted to 20.2 dBm.
Variation of IDD and
POUT due to adjustment
IDD=160±20 mA
POUT=20.2 dBm
IDD=160 mA
POUT=20.2±0.2 dBm
IDD=160±5 mA
POUT=20.2 dBm
(2)Simple adjustment
(IDD read) (VGG2 setting) (PIN adjustment)
When the RF input (PIN)
is off, the gate voltage
(VGG2) is set to 0.4 V
and IDD is read.
The formula∗where
VGG2=f (IDD: VGG2=0.4 V)
is used to set VGG2.
The output power (POUT)
is adjusted to 20.2 dBm.
∗ e.g. VGG2=a-b × IDD IDD=160±5 mA
POUT=20.2 dBm
VCTL1=3 V
VCTL2=0 V
VCTL1=0 V
VCTL2=3 V
ANT-TX ON
ANT-RX OFF
ANT-TX OFF
ANT-RX ON
Gate Bias Circuit of Power Amplifier Block
1kΩ
V
GG2
V
GG1
Gate voltage
adjustment pin
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