Sony CXD8302Q Datasheet
PLL for CCD Cameras
For the availability of this product, please contact the sales office.
Description
The CXD8302Q has the functions needs to
configure a PLL circuit with a timing generator and
external sync signals for a CCD of 480K pixels (EIA,
effective pixels) and 570K pixels (CCIR, effective
pixels).
Features
• EIA and CCIR compatible
• Compatible with component digital and composite
digital recording format
• Both SYNC and VD/HD signals can be used for
external sync signals
CXD8302Q
44 pin QFP (Plastic)
Applications
CCD cameras
Absolute Maximum Ratings
• Supply voltage VDD VSS – 0.3 to +7 V
• Input voltage VI VSS – 0.3 to VDD+0.3 V
• Storage temperature Tstg –40 to +125 °C
Recommended Operating Conditions
• Supply voltage VDD 4.5 to 5.5 V
•
Operating temperature
Topr 0 to 70 °C
Block Diagram
EXTSYNC
EXTHD
EXTVD
MODE1
MODE2
EIA/CCIR
15
14
13
V latch
26
31
Latch
32
Separation
of fH and fV
65 Clocks
Delay
Frequency Division
Frequency Division
Structure
Silicon gate CMOS IC
H
f
fV
EIA : 1/572
(1/568)
CCIR: 1/576
(1/567)
2fH
EIA : 1/525
CCIR: 1/625
V reset
H timing
V timing
19
20
41
42
43
44
Pulse Generation Circuit
EXTf
INTfH
HD
VD
SYNC
BLK
H
37
CLKI
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
38
8
4
2
3
INTfH phase setting
9
10
8
7
11
– 1 –
CLKO
E94320A52-PP
Pin Configuration
Vss
34
33
NC
EIA/CCIR
32
MODE2
31
TEST6
30
29
DD
V
28
Vss
TEST5
27
MODE1
26
TEST4
25
24
NC
23
Vss
22
CXD8302Q
TEST3
TEST7
NC
CLKO
CLKI
DD
V
Vss
HD
VD
SYNC
BLK
35
36
37
38
39
40
41
42
43
44
1
Vss
2
DLY0
3
DLY1
4
DLY2
TEST2
21
INTfH
20
EXTfH
19
TEST1
18
DD
V
17
Vss
16
EXTSYNC
15
14
EXTHD
13
EXTVD
12
Vss
6
5
DD
V
Vss
7
DLY3
8
DLY4
9
DLY5
10
DLY6
11
DLY7
– 2 –
Pin Description
CXD8302Q
Pin No. Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
DLY0
DLY1
DLY2
VDD
VSS
DLY3
DLY4
DLY5
DLY6
DLY7
VSS
EXTVD
EXTHD
EXTSYNC
VSS
I/O
Description
—
I
Pin 20 (INTfH) phase setting. (With pull-up resistor)
I
Pin 20 (INTfH) phase setting. (With pull-up resistor)
I
Pin 20 (INTfH) phase setting. (With pull-up resistor)
—
—
I
Pin 20 (INTfH) phase setting. (With pull-up resistor)
I
Pin 20 (INTfH) phase setting. (With pull-up resistor)
I
Pin 20 (INTfH) phase setting. (With pull-up resistor)
I
Pin 20 (INTfH) phase setting. (With pull-up resistor)
I
Pin 20 (INTfH) phase setting (MSB). (With pull-up resistor)
—
I
External VD input. (With pull-up resistor)
I
External HD input. (With pull-up resistor)
I
External SYNC input. (With pull-up resistor)
—
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
TEST1
EXTfH
INTfH
TEST2
TEST3
VSS
NC
TEST4
MODE
TEST5
VSS
VDD
TEST6
MODE2
EIA/CCIR
—
O
Test output (normally OPEN).
O
External fH output.
O
Internal fH output.
O
Test output (normally OPEN).
O
Test output (normally OPEN).
—
—
I
Test input (normally High). (With pull-up resistor)
I
High: SYNC sync mode, Low: VD/HD sync mode. (With pull-up resistor)
I
Test input (normally Low). (With pull-down resistor)
—
—
I
Test input (normally High). (With pull-up resistor)
High: Component digital mode, Low: Composite digital mode.
I
I
High: EIA mode, Low: CCIR mode. (With pull-up resistor)
(With pull-up resistor)
33
34
35
36
37
NC
VSS
TEST7
NC
CLKO
—
—
O
Test output (normally OPEN).
—
O
Inversed output of CLKI.
– 3 –
Loading...