Sony CXD3607R Datasheet

CXD3607R

Timing Generator for Progressive Scan CCD Image Sensor

Description

The CXD3607R is a timing generator IC which generates the timing pulses required by Progressive Scan CCD image sensors as well as signal processing circuits.

Features

• Base oscillation frequency 57.3MHz

• High-speed/low-speed shutter function

• Supports FINE and DRAFT mode drive

(15 frames/s, 60 frames/s possible)

• Random trigger shutter function

(Supports TRIG and TRIGOUT mode drive)

• Horizontal driver for CCD image sensor

• Vertical driver for CCD image sensor

Applications

Progressive scan CCD cameras

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDDa, b Vss – 0.3 to +7.0 V

• Input voltage VI Vss – 0.3 to VDD + 0.3 V

• Output voltage VO1 Vss – 0.3 to VDD + 0.3 V

• Operating temperature

• Storage temperature

48 pin LQFP (Plastic)

VL –10.0 to Vss V VH VL – 0.3 to +26.0 V

VO2 VL – 0.3 to Vss + 0.3 V VO3 VL – 0.3 to VH + 0.3 V

Topr –20 to +75 °C

Tstg –55 to +150 °C

Applicable CCD Image Sensors

ICX285 (Type 2/3, 1450K pixels)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Recommended Operating Conditions

• Supply voltage VDDa 4.75 to 5.25 V

VDDb 3.0 to 3.6 V VM 0.0 V VH 14.55 to 15.45 V VL –7.5 to –6.5 V

• Operating temperature Topr –20 to +75 °C

– 1 –

E01318-PS

Block Diagram

CXD3607R

OSCI

OSCO

CKI

CKO

MCKO

SSI SCK SEN

VD

HD

TRIG

27

26

25

23 22

29 30 31

32

33

34

XSHD

16

XSHP

17

Register

XCPDM

19 20 21

18

1/2

XCPOB

PBLK

1

ADCLKRGV

10

SS

11 12

Pulse Generator

H1

V Driver

13

H2

14

1

DD

V

15 28

24 36

38 39 40 42 47 48

37 41 45

VDD2

DD

3

V V

DD

4

SS

2

V

SS

3

V

1

SS

4

V

V1 V4 V2A V2B V3 SUB

V

M

V

H

V

L

2

RST

378

SYNSL

9

TEST1

TEST2

– 2 –

35

WEN

Pin Configuration (Top View)

CXD3607R

V

V1

V4

V2A

V

V2B

NC NC

V

NC

V3

SUB

29

SSI

3

DD

V

OSCI

OSCO

262728

25

CKI

24

23

22

21

20

19

18

17

16

15

14

13

V

SS

2

CKO

MCKO

ADCLK

PBLK

XCPOB

XCPDM

XSHP

XSHD

V

DD

2

DD

1

V

H2

3

SS

V

36

M

37

35

WEN

TRIG

HD

VD

323334

31

SEN

SCK

30

38

39

40

H

41

42

43

44

L

45

46

47

48

1 2 3 4 5 6 7 8 9 10 11 12

4

SS

V

RST

SYNSL

NC

4

DD

V

TEST1

TEST2

RG

1

SS

V

H1

∗

Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.

– 3 –

Pin Description

CXD3607R

No.

1 2

3 4

5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Symbol I/O Description VSS4 RST

SYNSL NC

NC NC VDD4 TEST1 TEST2 RG VSS1 H1 H2 VDD1 VDD2 XSHD XSHP XCPDM XCPOB PBLK ADCLK MCKO CKO VSS2 CKI OSCO OSCI VDD3 SSI SCK SEN VD HD TRIG WEN

GND (GND for common logic block)

—

Internal system reset input. (High: Normal operation, Low: Reset operation)

I

Normally apply reset during power-on. Control input used to switch sync system. (High: CKI sync, Low: MCKO sync)

I

(Leave open.)

—

(Leave open.)

—

(Leave open.)

—

3.3V power supply. (Power supply for common logic block)

—

IC test pin 1 (Normally fix to GND.)

I

IC test pin 2 (Normally fix to GND.) With pull-down resistor

I

CCD reset gate pulse output.

O

GND (GND for H1 and H2 pins)

—

Horizontal CCD drive clock output.

O

Horizontal CCD drive clock output.

O

5.0V power supply. (Power supply for H1 and H2 pins)

—

3.3V power supply. (Power supply for common logic block)

—

CCD data level sample-and-hold pulse output.

O

CCD precharge level sample-and-hold pulse output.

O

CCD dummy signal clamp pulse output.

O

CCD optical black signal clamp pulse output.

O

Pulse output for horizontal and vertical blanking period pulse cleaning.

O

Clock output for analog/digital conversion IC.

O

System clock output for signal processing IC. (28.6MHz)

O

Inverter output. (57.3MHz)

O

GND (GND for common logic block)

—

Inverter input. (57.3MHz)

I

Inverter output for oscillation. (57.3MHz)

O

Inverter input for oscillation. (57.3MHz)

I

3.3V power supply. (Power supply for common logic block)

—

Serial interface data input for internal mode settings.

I

Serial interface clock input for internal mode settings.

I

Serial interface strobe input for internal mode settings.

I

Vertical sync signal input.

I

Horizontal sync signal input.

I

Trigger pulse input.

I

Memory write timing pulse output.

O

With pull-down resistor

– 4 –

CXD3607R

No.

36 37 38 39 40 41 42 43 44 45 46 47 48

Symbol I/O Description VSS3

M

V V1 V4 V2A VH V2B NC NC VL NC V3 SUB

GND (GND for common logic block)

—

GND (GND for vertical driver)

—

CCD vertical register clock output.

O

CCD vertical register clock output.

O

CCD vertical register clock output.

O

15.0V power supply. (Power supply for vertical driver)

—

CCD vertical register clock output.

O

(Leave open.)

—

(Leave open.)

—

–7.0V power supply. (Power supply for vertical driver)

—

(Leave open.)

—

CCD vertical register clock output.

O

CCD electronic shutter pulse output.

O

– 5 –

CXD3607R

Electrical Characteristics

DC Characteristics (Within the recommended operating conditions)

Item

Supply voltage 1

Supply voltage 2

Supply voltage 3

Supply voltage 4

Supply voltage 5

Input voltage 1

Input

∗1, ∗2

voltage 2

Output voltage 1

Output voltage 2

VDD1

VDD2 to 4

VH

VM

VL RST, TEST1,

SSI, SCK, SEN,

∗1

VD, HD, TRIG

SYNSL, TEST2

XCPDM, XCPOB, PBLK, ADCLK, WEN

XSHD, XSHP, CKO

Pins

Symbol

VDDa

VDDb

VH

VM

VL

Vt+ Vt–

VOH1

VOL1 VOH2 VOL2

Conditions Min. Typ. Max. Unit

Feed current where IOH = –3.3mA

Pull-in current where IOL = 2.4mA Feed current where IOH = –6.6mA Pull-in current where IOL = 4.8mA

4.75

3.0

14.55

—

–7.5

0.8VDDb

VDDb – 0.8

5.0

3.3

15.0

0

–7.0

5.25

3.6

15.45

—

–6.5

0.2VDDb

0.4

V

V V

Output voltage 3

Output voltage 4

RG, MCKO

H1, H2

VOH3 VOL3 VOH4 VOL4 IOL

Output current 1

V1, V2A, V2B, V3, V4

VOM1 VOM2 VOH

Output current 2

∗1

These input pins are Schmitt trigger inputs, and have a protective diode on the power supply side in the IC.

SUB

IOSL IOSH

Feed current where IOH = –10.4mA Pull-in current where IOL = 7.2mA Feed current where IOH = –22.0mA Pull-in current where IOL = 14.4mA V1, V2A, V2B, V3, V4 = –8.25V V1, V2A, V2B, V3, V4 = –0.25V V2A, V2B = 0.25V V2A, V2B = 14.75V SUB = –8.25V SUB = 14.75V

VDDb – 0.8

0.4

VDDa – 0.8

0.4

10.0 –5.0

5.0 –7.2

5.4 –4.0

Therefore, they do not support 5V input.

∗2

These input pins are with pull-down resistor in the IC.

Note) This table shows the conditions for 3.3V drive.

V V V

V mA mA mA mA mA mA

– 6 –

CXD3607R

Inverter I/O Characteristics for Oscillation (Within the recommended operating conditions)

Item Pins

Logical Vth

Input voltage

Output voltage

Feedback resistor

Oscillator frequency

OSCI

OSCO

OSCI OSCO

Symbol

LVth

IH

V VIL VOH VOL

RFB

f

Conditions Min. Typ. Max. Unit

— —

— Feed current where IOH = –9mA Pull-in current where IOL = 9mA

VIN = VDDb or VSS

—

0.7V

V

DDb/2

500k

—

30

Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment

(Within the recommended operating conditions)

Item Pins

Logical Vth

Input voltage

Input amplitude

CKI

Symbol

LVth VIH VIL VIN

Conditions Min. Typ. Max. Unit

— — —

fmax 75MHz sine wave

—

0.7VDDb —

0.3

DDb

VDDb/2

— — — —

2M

—

VDDb/2

— — —

— —

0.3VDDb —

VDDb/2

5M

75

— —

0.3VDDb —

V V V V V

Ω

MHz

V V V

Vp-p

Note) Input voltage is the input voltage characteristics for direct input from an external source. Input

amplitude is the input amplitude characteristics in the case of input through a capacitor.

Switching Characteristics (VH = 15.0V, VM = GND, VL = –7.0V)

Item

Rise time

Fall time

Output noise voltage

Symbol TTLM TTMH TTLH TTML TTHM TTHL VCLH VCLL VCMH VCML

VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL

Conditions Min. Typ. Max. Unit

200 200

30 200 200

30

350 350

60 350 350

60

500 500

90 500 500

90

1.0

ns ns ns ns ns ns

V V V V

1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge.

2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND.

3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. See the CCD image sensor data sheet for details.

– 7 –

Switching Wa veforms

CXD3607R

V2A, V2B

V1, V3, V4

TTLM

10%

TTLM

10%

TTMH TTHM

90%

10%

90%

10%

90%

TTLH TTHL

90%90%

TTML

10%

TTML

10%

H

V

M

V

L

V

M

V

L

V

H

Waveform Noise

SUB

VCLH

10% 10%

VCMH

VCLL

VCML

V

L

V

M

VL

– 8 –

AC Characteristics

AC characteristics between the serial interface clocks

CXD3607R

Symbol

ts1 th1 ts2 ts3

SSI

SCK

SEN

SSI setup time, activated by the rising edge of SCK SSI hold time, activated by the rising edge of SCK SCK setup time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SCK

0.2V

DD

b

0.2V

0.8VDDb

b

th1ts1

ts2

DD

0.2V

DD

b

ts3

Definition Min. Typ. Max. Unit

Serial interface clock internal loading characteristics

DD

b

0.2V

DD

b

0.8V

DD

b

0.2V

(Within the recommended operating conditions)

20 20 20 20

Example: During FINE mode

ns ns ns ns

HD

V2

SCK

SEN

∗

Be sure to maintain a constantly high SEN logic level from around the falling edge of the HD 8H after the

0.2V

DD

ts1

0.8V

b

DD

b

8H 9H

0.2VDDb

th1

0.8V

DD

b

falling edge of VD to around the 9H falling edge and during that horizontal period.

(Within the recommended operating conditions)

Symbol

ts1 th1

Second SCK clock setup time after the rising edge of SEN, activated by the falling edge of HD

SEN hold time, activated by the falling edge of 9H HD

Definition Min. Typ. Max. Unit

5

30

– 9 –

ns µs

CXD3607R

Serial interface clock output variation characteristics

The serial interface data “Standby setting” is loaded to the CXD3607R and controlled at the rising edge of the second SCK clock after the rising edge of SEN.

SEN

0.8VDDb

SCK

Output signal

tpdPULSE

(Within the recommended operating conditions)

Symbol Definition Min. Typ. Max. Unit

tpdPULSE

Output signal delay, activated by the rising edge of the second SCK clock after the rising edge of SEN

10 ns

100

RST loading characteristics

RST

0.2VDDb

tw1

(Within the recommended operating conditions)

Symbol Definition Min. Typ. Max. Unit

tw1

RST pulse width

35

VD, HD and TRIG loading characteristics

DD

b

VD/HD/TRIG

0.2V

DD

b

ts1

th1

0.8V

ns

MCKO

0.2VDDb

0.8VDDb

MCKO load capacitance = 16pF

(Within the recommended operating conditions)

Symbol Definition Min. Typ. Max. Unit

ts1 th1

VD/HD/TRIG setup time, activated by the rising edge of MCKO VD/HD/TRIG hold time, activated by the rising edge of MCKO

20

5

– 10 –

ns ns

Output variation characteristics

CXD3607R

MCKO

WEN

WEN load capacitance = 10pF

Symbol Definition

tpd1

Time until WEN changes after the rise of MCKO

0.8VDDb

tpd1

(Within the recommended operating conditions)

Min. Typ. Max. Unit

ns–60

– 11 –

CXD3607R

Description of Operation

Pulses output from the CXD3607R are controlled mainly by the RST and SYNSL pins and by the serial interface data.

Control by the RST Pin

System reset is performed by setting the CXD3607R RST pin (Pin 2) low. After reset is canceled, the serial data block is “XSHP, XSHD logic phase adjustment setting” D0 bit = 1 and all other bits = 0. In addition, when RST = low, some circuit operations in the IC are stopped as shown in the Pin Status Table below.

Pin Status Table (RST = low)

Pin No. Symbol I/O status

—

L

ACT

— — — — — —

ACT

—

ACT ACT

— —

ACT ACT

H H

H ACT ACT ACT

—

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1 2 3 4 5 6 7 8 9

VSS4 RST SYNSL NC NC NC VDD4 TEST1 TEST2 RG VSS1 H1 H2 VDD1 VDD2 XSHD XSHP XCPDM XCPOB PBLK ADCLK MCKO CKO VSS2

Pin No. Symbol I/O status

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

CKI OSCO OSCI VDD3 SSI SCK SEN VD HD TRIG WEN VSS3 VM V1 V4 V2A VH V2B NC NC VL NC V3 SUB

ACT ACT ACT

—

DIS DIS DIS DIS DIS DIS

L

— —

VL VL VM

—

VM

— — — —

VM VL

Note) ACT means that the circuit is operating, and DIS means that loading is stopped.

L indicates a low output level, and H a high output level in the controlled status. VM and VL indicate the voltage levels applied to VM (Pin 37) and VL (Pin 45), respectively.

– 12 –