Sony CXD3511Q Datasheet

Digital Signal Driver/Timing Generator
Description
CXD3511Q
240 pin QFP (Plastic)
Features
Various picture quality adjustment functions such
as user adjustment, white balance adjustment and
gamma correction
OSD MIX, black frame processing, mute and
limiter functions
LCD panel color shading correction function
Selectable delay line
Drives various Sony data projector LCD panels
such as SXGA and XGA
Controls the CXA3512R and CXA3562R sample-
and-hold drivers
Line inversion and field inversion signal generation
Supports AC drive of LCD panels during no signal
Applications
LCD projectors and other video equipment
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (VSS = 0V)
Supply voltage VDD1 VSS – 0.5 to +3.0 V
VDD2 VSS – 0.5 to +4.0 V
Input voltage VI VSS – 0.5 to VDD1 + 0.5 V
Output voltage VO VSS – 0.5 to VDD1 + 0.5 V
Storage temperature
Tstg –55 to +125 °C
Junction temperature Tj 125 °C
Recommended Operating Conditions
Supply voltage VDD1 2.3 to 2.7 V
VDD2 3.0 to 3.6 V
Operating temperature Topr –20 to +75 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00Y06-PS
Block Diagram
CXD3511Q
R, G, B IN
R, G, B OSD
YM
YS
PCTL PCLK PDAT
CLKC CLKP
CLKN CLKSEL1 CLKSEL2
PLLDIV
HDIN VDIN
8 × 2 × 3 2 × 2 × 3
2 2
10
PARALLEL I/F
PLL
DQ
Q
DSD
10 × 2 × 3
TG
Direct Clear
R, G, B OUT
CLKOUT
CTRL
RGT, DWN
PCG, BLK, HST, ENBR, ENBL, VSTR, VSTL, VCKR, VCKL, HCK1, DCK1, DCK2, HCK2, DCK1X, DCK2X, XRGT, FRP, XFRP, PRG, DENB, CLP, PO1, PO2, PO3, PO4, PO5, PST, HD1, HD2
XCLR1 XCLR2 XCLR3
– 2 –
Pin Configuration
CXD3511Q
R1IN2 R1IN1 R1IN0 R2IN7 R2IN6
V
R2IN5 R2IN4 R2IN3 R2IN2 R2IN1 R2IN0 G1IN7 G1IN6 G1IN5
V
G1IN4 G1IN3 G1IN2 G1IN1 G1IN0 G2IN7 G2IN6 G2IN5 G2IN4 G2IN3
V
G2IN2 G2IN1 G2IN0 B1IN7 B1IN6 B1IN5 B1IN4 B1IN3 B1IN2 B1IN1
V
B1IN0 B2IN7 B2IN6 B2IN5 B2IN4 B2IN3 B2IN2 B2IN1
B2IN0 R1OSD1 R1OSD0
V
G1OSD1 G1OSD0 B1OSD1 B1OSD0
YM1
R1IN5
R1IN6
R1IN7
VSSV
DD2
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
HD1
166167168169170171172173174175176177178179180
R1IN3
R1IN4
181 182 183 184 185 186
DD2
187
V
SS
188 189 190 191 192 193 194 195 196 197
DD1
198
SS
V
199 200 201 202 203 204 205 206 207 208
DD1
209
V
SS
210 211 212 213 214 215 216 217 218 219 220
DD1
221
V
SS
222 223 224 225 226 227 228 229 230 231 232 233
DD2
234
SS
V
235 236 237 238 239 240
DD1
PO5
CLP
PO4
VSSV
PRG
163
165
164
DENB
SHST
XFRP
DD1
FRP
V
HD2
PO1
PO2
PO3
PST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
YS1
R2OSD1
R2OSD0
G2OSD1
G2OSD0
SS
DD2
V
YS2
YM2
V
B2OSD1
B2OSD0
PCTL
PCLK
PDAT9
SS
DD2
V
V
PDAT8
PDAT7
PDAT6
PDAT5
DD1
V
PDAT4
PDAT3
PDAT2
PDAT1
SS
V
PDAT0
XCLR1
XCLR2
XCLR3
VSSPCG
VDIN
HDIN
CTRL
SSVSS
V
DD1VDD2
DWN
VSTL
V
VCKL
DD1VDD1
V
CLKP
CLKC
DD2
ENBL
BLK
HST
VSSV
141142143144145146147148149150151152153154155156157158159160161162
41 42 43 44 53 54 55 56 57 58 59 60
SS
DD1
DD2
V
V
V
CLKN
CLKSEL1
SS
XRGT
RGT
HCK2
HCK1
V
DCK1
135136137138139140
DCK1X
134
133
132
131
45 46 47 48 49 50 51 52
SS
SS
V
V
PLLDIV
B2OUT0
B2OUT1
CLKOUT
CLKSEL2
130
SS
V
DCK2X
129
B2OUT2
B2OUT3
SS
DCK2
V
127128
DD2
V
B2OUT4
DD2
V
ENBR
126
125
SS
V
B2OUT5
124
VCKR
VSTR
123
B2OUT6
B2OUT7
122
R2OUT9
R1OUT8
121
B2OUT8
B2OUT9
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
R1OUT7 R1OUT6 R1OUT5 R1OUT4 R1OUT3 V
SS DD2
V R1OUT2 R1OUT1 R1OUT0 R2OUT9 R2OUT8 R2OUT7 R2OUT6 R2OUT5 R2OUT4 R2OUT3 R2OUT2 V
SS
V
DD1
V
DD2
R2OUT1 R2OUT0 G1OUT9 G1OUT8 G1OUT7 G1OUT6 G1OUT5 G1OUT4 G1OUT3 V
SS
V
DD1
G1OUT2 G1OUT1 G1OUT0 G2OUT9 V
DD2
G2OUT8 G2OUT7 G2OUT6 G2OUT5 G2OUT4 V
SS
V
DD1
G2OUT3 G2OUT2 G2OUT1 G2OUT0 B1OUT9 B1OUT8 B1OUT7 B1OUT6 B1OUT5 V
SS DD2
V B1OUT4 B1OUT3 B1OUT2 B1OUT1 B1OUT0
– 3 –
Pin Description
Pin No.
1 2 3 4 5 6 7 8
9 10 11 12
Symbol
YS1 R2OSD1 R2OSD0 G2OSD1 G2OSD0 VDD2 VSS B2OSD1 B2OSD0 YM2 YS2 PCTL
I/O
I
OSD YS input (port 1)
I
OSD Red data input (port 2)
I
OSD Red data input (port 2)
I
OSD Green data input (port 2)
I
OSD Green data input (port 2)
I/O power supply
GND
I
OSD Blue data input (port 2)
I
OSD Blue data input (port 2)
I
OSD YM input (port 2)
I
OSD YS input (port 2)
I
Parallel I/F control signal input
Description
CXD3511Q
Input pin processing for open status
L
— — — — — — — —
L L
H 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
PCLK PDAT9 PDAT8 PDAT7 PDAT6 VDD2 VSS PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 VDD1 PDAT0 XCLR1 XCLR2 XCLR3
I
Parallel I/F clock input
I
Parallel I/F data input
I
Parallel I/F data input
I
Parallel I/F data input
I
Parallel I/F data input
I/O power supply
GND
I
Parallel I/F data input
I
Parallel I/F data input
I
Parallel I/F data input
I
Parallel I/F data input
I
Parallel I/F data input
Internal operation power supply
I
Parallel I/F data input
I
External clear (Low: reset)
I
External clear (Low: reset)
I
External clear (Low: reset)
— — — — —
— — — — — — — —
H
H
H 30 31 32 33 34 35 36 37
VSS HDIN VDIN VSS VSS CLKC VDD1 VDD1
GND
I
Horizontal sync signal input
I
Vertical sync signal input
GND
GND
I
Clock input (CMOS input)
Internal operation power supply
Internal operation power supply
— — — — — — — —
4
CXD3511Q
Pin No.
38 39 40 41 42 43
44 45
46 47 48 49 50 51 52
Symbol
CLKP CLKN VDD2 CLKSEL1 VDD1 VSS
CLKSEL2 PLLDIV
VSS CLKOUT VSS B2OUT0 B2OUT1 B2OUT2 B2OUT3
I/O
I
Clock input (small-amplitude differential input, positive polarity)
I
Clock input (small-amplitude differential input, negative polarity)
I/O power supply
I
Input clock selection. (High: CLKC, Low: CLKP, CLKN)
Internal operation power supply
GND Internal clock path selection.
I
(High: no frequency division, Low: frequency division)
I
Internal PLL setting. (High: 55MHz or less, Low: 55MHz or more)
GND
O
Internal clock output (inverted output)
GND
O
Blue data output (port 2)
O
Blue data output (port 2)
O
Blue data output (port 2)
O
Blue data output (port 2)
Description
Input pin processing for open status
— — —
L
— —
L L
— — — — — — —
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
B2OUT4 VDD2 VSS B2OUT5 B2OUT6 B2OUT7 B2OUT8 B2OUT9 B1OUT0 B1OUT1 B1OUT2 B1OUT3 B1OUT4 VDD2 VSS B1OUT5 B1OUT6
O
Blue data output (port 2)
I/O power supply
GND
O
Blue data output (port 2)
O
Blue data output (port 2)
O
Blue data output (port 2)
O
Blue data output (port 2)
O
Blue data output (port 2)
O
Blue data output (port 1)
O
Blue data output (port 1)
O
Blue data output (port 1)
O
Blue data output (port 1)
O
Blue data output (port 1)
I/O power supply
GND
O
Blue data output (port 1)
O
Blue data output (port 1)
— — — — — — — — — — — — — — — — —
70 71 72 73 74
B1OUT7 B1OUT8 B1OUT9 G2OUT0 G2OUT1
O
Blue data output (port 1)
O
Blue data output (port 1)
O
Blue data output (port 1)
O
Green data output (port 2)
O
Green data output (port 2)
— — — — —
5
CXD3511Q
Pin No.
75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Symbol
G2OUT2 G2OUT3 VDD1 VSS G2OUT4 G2OUT5 G2OUT6 G2OUT7 G2OUT8 VDD2 G2OUT9 G1OUT0 G1OUT1 G1OUT2 VDD1 VSS
I/O
O
Green data output (port 2)
O
Green data output (port 2)
Internal operation power supply
GND
O
Green data output (port 2)
O
Green data output (port 2)
O
Green data output (port 2)
O
Green data output (port 2)
O
Green data output (port 2)
I/O power supply
O
Green data output (port 2)
O
Green data output (port 1)
O
Green data output (port 1)
O
Green data output (port 1)
Internal operation power supply
GND
Description
Input pin processing for open status
— — — — — — — — — — — — — — — —
91 92 93 94 95 96 97 98 99
100 101 102 103 104 105 106 107
G1OUT3 G1OUT4 G1OUT5 G1OUT6 G1OUT7 G1OUT8 G1OUT9 R2OUT0 R2OUT1 VDD2 VDD1 VSS R2OUT2 R2OUT3 R2OUT4 R2OUT5 R2OUT6
O
Green data output (port 1)
O
Green data output (port 1)
O
Green data output (port 1)
O
Green data output (port 1)
O
Green data output (port 1)
O
Green data output (port 1)
O
Green data output (port 1)
O
Red data output (port 2)
O
Red data output (port 2)
I/O power supply
Internal operation power supply
GND
O
Red data output (port 2)
O
Red data output (port 2)
O
Red data output (port 2)
O
Red data output (port 2)
O
Red data output (port 2)
— — — — — — — — — — — — — — — — —
108 109 110 111
R2OUT7 R2OUT8 R2OUT9 R1OUT0
O
Red data output (port 2)
O
Red data output (port 2)
O
Red data output (port 2)
O
Red data output (port 1)
— — — —
6
CXD3511Q
Pin No.
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Symbol
R1OUT1 R1OUT2 VDD2 VSS R1OUT3 R1OUT4 R1OUT5 R1OUT6 R1OUT7 R1OUT8 R1OUT9 VSTR VCKR ENBR VDD2 VSS
I/O
O
Red data output (port 1)
O
Red data output (port 1)
I/O power supply
GND
O
Red data output (port 1)
O
Red data output (port 1)
O
Red data output (port 1)
O
Red data output (port 1)
O
Red data output (port 1)
O
Red data output (port 1)
O
Red data output (port 1)
O
Vertical display start timing pulse output
O
Vertical display transfer clock output
O
Gate enable pulse output
I/O power supply
GND
Description
Input pin processing for open status
— — — — — — — — — — — — — — — —
128 129 130 131 132 133 134 135 136
137 138
139 140 141 142 143 144
DCK2 DCK2X VSS DCK1X DCK1 VSS HCK1 HCK2 RGT
XRGT VDD2
VSS HST BLK ENBL VCKL VDD2
O
DCK2 pulse output
O
DCK2X pulse output
GND
O
DCK1X pulse output
O
DCK1 pulse output
GND
O
Horizontal display transfer clock output 1
O
Horizontal display transfer clock output 2
I/O
Horizontal scan direction switching signal I/O Horizontal scan direction switching signal output (reversed
O
polarity of RGT)
I/O power supply
GND
O
Horizontal display start timing pulse output
O
BLK pulse output
O
Gate enable pulse output
O
Vertical display transfer clock output
I/O power supply
— — — — — — — — —
— —
— — — — — —
145 146 147
VDD1 VSTL DWN
Internal operation power supply
O
Vertical display start timing pulse output
I/O
Vertical scan direction switching signal I/O
7
— — —
CXD3511Q
Pin No.
148 149
150 151 152 153 154 155 156 157 158 159 160 161 162
Symbol
CTRL PCG
VSS PST PO3 PO2 PO1 HD2 VDD1 FRP XFRP SHST DENB PRG VDD1
I/O
Scan direction control method switching
I
(Low: internal register, High: external)
O
Collective precharge timing pulse output
GND
O
Dot sequential precharge start timing pulse output
O
Parallel output 3
O
Parallel output 2
O
Parallel output 1
O
Horizontal auxiliary pulse output 2
Internal operation power supply
O
AC drive inversion timing pulse output
O
AC drive inversion timing pulse output (reversed polarity of FRP)
O
SHST pulse output
O
DENB pulse output
O
2-step precharge timing pulse output
Internal operation power supply
Description
Input pin processing for open status
L
— — — — — — — — — — — — — —
163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179
VSS PO4 CLP PO5 HD1 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 VDD2 VSS R1IN7 R1IN6 R1IN5 R1IN4
GND
O
Parallel output 4
O
CLP pulse output
O
Parallel output 5
O
Horizontal auxiliary pulse output 1
Test pin (Connect to GND.)
Test pin (Connect to GND.)
Test pin (Connect to VDD2.)
Test pin (Connect to VDD2.)
Test pin (Connect to VDD2.)
Test pin (Connect to VDD2.)
I/O power supply
GND
I
Red data input (port 1)
I
Red data input (port 1)
I
Red data input (port 1)
I
Red data input (port 1)
— — — — — — — — — — — — — — — — —
180 181 182 183 184
R1IN3 R1IN2 R1IN1 R1IN0 R2IN7
I
Red data input (port 1)
I
Red data input (port 1)
I
Red data input (port 1)
I
Red data input (port 1)
I
Red data input (port 2)
— — — — —
8
CXD3511Q
Pin No.
185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Symbol
R2IN6 VDD2 VSS R2IN5 R2IN4 R2IN3 R2IN2 R2IN1 R2IN0 G1IN7 G1IN6 G1IN5 VDD1 VSS G1IN4 G1IN3
I/O
I
Red data input (port 2)
I/O power supply
GND
I
Red data input (port 2)
I
Red data input (port 2)
I
Red data input (port 2)
I
Red data input (port 2)
I
Red data input (port 2)
I
Red data input (port 2)
I
Green data input (port 1)
I
Green data input (port 1)
I
Green data input (port 1)
Internal operation power supply
GND
I
Green data input (port 1)
I
Green data input (port 1)
Description
Input pin processing for open status
— — — — — — — — — — — — — — — —
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217
G1IN2 G1IN1 G1IN0 G2IN7 G2IN6 G2IN5 G2IN4 G2IN3 VDD1 VSS G2IN2 G2IN1 G2IN0 B1IN7 B1IN6 B1IN5 B1IN4
I
Green data input (port 1)
I
Green data input (port 1)
I
Green data input (port 1)
I
Green data input (port 2)
I
Green data input (port 2)
I
Green data input (port 2)
I
Green data input (port 2)
I
Green data input (port 2)
Internal operation power supply
GND
I
Green data input (port 2)
I
Green data input (port 2)
I
Green data input (port 2)
I
Blue data input (port 1)
I
Blue data input (port 1)
I
Blue data input (port 1)
I
Blue data input (port 1)
— — — — — — — — — — — — — — — — —
218 219 220 221
B1IN3 B1IN2 B1IN1 VDD1
I
Blue data input (port 1)
I
Blue data input (port 1)
I
Blue data input (port 1)
Internal operation power supply
— — — —
9
CXD3511Q
Pin No.
222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237
Symbol
SS
V B1IN0 B2IN7 B2IN6 B2IN5 B2IN4 B2IN3 B2IN2 B2IN1 B2IN0 R1OSD1 R1OSD0 VDD2 VSS G1OSD1 G1OSD0
I/O
GND
I
Blue data input (port 1)
I
Blue data input (port 2)
I
Blue data input (port 2)
I
Blue data input (port 2)
I
Blue data input (port 2)
I
Blue data input (port 2)
I
Blue data input (port 2)
I
Blue data input (port 2)
I
Blue data input (port 2)
I
OSD red data input (port 1)
I
OSD red data input (port 1)
I/O power supply
GND
I
OSD green data input (port 1)
I
OSD green data input (port 1)
Description
Input pin processing for open status
— — — — — — — — — — — — — — — —
238
B1OSD1
239
B1OSD0
240
YM1
H: Pull-up, L: Pull-down
I
OSD blue data input (port 1)
I
OSD blue data input (port 1)
I
OSD YM input (port 1)
— —
L
– 10 –
CXD3511Q
Electrical Characteristics
DC Characteristics (Topr = –20 to +75°C, VSS = 0V)
Item Symbol Applicable pins Conditions Min. Typ. Max.
Supply voltage
Input voltage 1
Input voltage 2
Input voltage 3
VDD1 VDD2 VIH1 VIL1 VIH2 VIL2 VC VIH3
1
HDIN, VDIN, PCTL, PCLK, PDAT0 to PDAT9
2
CLKP, CLKN
VIL3
Output voltage
Current consumption
1
Input pins other than those indicated in items Input voltage 2 and Input voltage 3.
2
VIH3 > VC (max.) and VIL3 < VC (min.).
3
Tj [°C] Toprmax [°C] + θja [°C/W] × PD [W].
VOH VOL
PD
All output pins
3
— —
CMOS input cell
CMOS Schmitt trigger input cell
Small-amplitude differential input
— —
CLKP = 200MHz
2.3
3.0
2.0
–0.3
0.8VDD2 –0.3
1.718
1.868 VSS
VDD2 – 0.5
VSS
2.5
3.3
— — — —
2.0 VC + 0.4 VC – 0.4
— —
2600
(Tj = 125 [°C], Toprmax = 75 [°C], θja = 16 [°C/W], when mounted on a 4-layer substrate)
2.7
3.6
DD2 + 0.3
V
0.8
V
DD2 + 0.3
0.2VDD2
2.281 VDD2
2.131 VDD2
0.2
3120
Unit
V
mW
AC Characteristics (Topr = –20 to +75°C, VDD1 = 2.5 ± 0.2V, VDD2 = 3.3 ± 0.3V, VSS = 0V)
Item Symbol Applicable pins Conditions Min. Typ. Max. Unit
Clock input period Input setup time
tis
CLKP, CLKN, CLKC
RGB input, OSD input,
— —
5
2.5
— —
— —
HDIN, VDIN
Input hold time Output rise/fall
delay time Output rise/fall
delay time Output rise/fall
delay time Cross-point time
difference HCK1 duty
tih tor/tof
tor/tof tor/tof
t
th/(th + tl)
4
RGB output
CLKOUT HCK1, HCK2, DCK1,
DCK1X, DCK2, DCK2X HCK1
CL = 20pF
CL = 20pF
CL = 50pF
CL = 20pF CL = 20pF
1.5 2
2
1.5
–5 48
5
4
4.5
50
10
ns
8
8.5
5
52
%
HCK2 duty
tl/(th + tl)
Phase compensation PLL operating
frequency
4
Output pins other than RGB output, CLKOUT, PO1 to PO5, RGT, XRGT and DWN.
HCK2
CL = 20pF
PLLDIV = L
PLLDIV = H
48 55
27.5
50
— —
52
100
MHz
55
– 11 –
Timing Definition
1/2 frequency­divided inputs
RGB input, OSD input, HDIN, VDIN
1/2 frequency­divided inputs
Outputs other than CLKOUT
Outputs other than CLKOUT
CLKP, CLKC
CLKN
CLKP, CLKC
CLKN
CLKP, CLKC
CLKN
CLKP, CLKC
CLKN
CLKOUT
VC, 50%
VC
VC, 50%
VC
tof
tor
tis tih
VC, 50%
VC
VC, 50%
VC
50% 50%
tor
50%
50%
VC, 50%
VC
VC, 50%
50%
IH3
V V
IL3
V
IH3
V
IL3
V
IH3
V
IL3
V
IH3
V
IL3
V
DD2
V
SS
IH3
V V
IL3
V
IH3
V
IL3
V
IH3
V
IL3
V
IH3
V
IL3
V
DD2
V
SS
V
DD2
V
SS
V
DD2
V
SS
CXD3511Q
, V
DD2
, V
SS
, V
DD2
, V
SS
, V
DD2
, V
SS
, V
DD2
, V
SS
HCK1, DCK1, DCK2
HCK2, DCK1X, DCK2X
CHK1, HCK2
tof
50%
50%
50%
50%
t∆t
50% 50% 50%
th tl
– 12 –
V
DD2
V
SS
V
DD2
V
SS
V
DD2
V
SS
CXD3511Q
Parallel I/F Block AC Characteristics (Topr = –20 to +75°C, VDD1 = 2.5 ± 0.2V, VDD2 = 3.3 ± 0.3V, VSS = 0V)
Item PCTL setup time with respect to rise of PCLK PCTL hold time with respect to rise of PCLK PDAT[9:0] setup time with respect to rise of PCLK PDAT[9:0] hold time with respect to rise of PCLK PCLK pulse width
5
T: Master clock (CLKP, CLKN, CLKC) period [ns]
Timing Definition
tcs
50%PCTL
tw tw
PCLK
PDAT[9:0]
50% 50%
tds tdh
50% 50%
Symbol
tcs tch tds tdh tw
tch
8T
50%
Min.
8T 4T 4T 4T
Typ.
5
— — — — —
DD2
V
V
SS
V
DD2
V
SS
V
DD2
V
SS
Max.
— — — — —
Power-on and Initialization of Internal Circuit
As for this IC, two systems of supply voltage should be turned on simultaneously. The initialization of the internal circuit should be also performed by maintaining the system clear pin at low during the specified time after setting the supply voltage in the range of recommended operating conditions and stabilizing as shown in the figure below. Keep in mind that the internal circuit may not be initialized correctly if system clear cancellation is performed before the supply voltage is set in the range of the recommended operating conditions.
V
DD1
, V
DD2
V
DD1
, V
DD2
XCLR1, XCLR2, XCLR3
TR
TR > 200ns
V
SS
V
DD2
V
SS
– 13 –
CXD3511Q
Description of Operation
1. Description of Input Pins
(a) System clear pins (XCLR1, XCLR2 and XCLR3)
All internal circuits are initialized by setting XCLR1 (Pin 27) low. In addition, the internal PLL is initialized by setting XCLR2 (Pin 28) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 29) low. Initialization should be performed when power is turned on. There are no particular restrictions on the initialization order.
(b) Sync signal input pins (HDIN and VDIN)
Horizontal and vertical separate sync signals are input to HDIN (Pin 31) and VDIN (Pin 32), respectively. The CXD3511Q supports only non-inter lace sync signals with a dot clock of 200MHz or less.
(c) Master clock input pins (CLKP/CLKN and CLKC)
Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The master clock input pins have two systems consisting of CLKP/CLKN (Pins 38 and 39) for small-amplitude differential input (center level: 2.0V, amplitude: ±0.4V), and CLKC (Pin 35) for CMOS level input. In addition, be sure to make the number of dot clocks in 1H as even number. Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate properly.
(d) Clock selection pins (CLKSEL1 and CLKSEL2)
The master clock input pins can input either the system dot clock or the 1/2 frequency-divided clock. The internal clock path is selected according to CLKSEL1 (Pin 41) and CLKSEL2 (Pin 44).
Setting
Symbol
CLKSEL1 CLKSEL2
Input clock selection Clock input pin selection
Function
L CLKP/CLKN input Dot clock input
H CLKC input 1/2 frequency-divided clock input
(e) PLL setting pin (PLLDIV)
PLLDIV (Pin 45) sets the divider setting of the internal phase compensation PLL circuit. Set PLLDIV low when the internal clock frequency is 55 to 100MHz, or high when 27.5 to 55MHz. In addition, note that the frequency of the clock input to the CXD3511Q must be within the phase compensation PLL operating range, even during free running.
– 14 –
CXD3511Q
(f) RGB signal input pins (R1IN, R2IN, G1IN, G2IN, B1IN and B2IN)
These pins input RGB signals that have been demultiplexed to 1:2. The Red signal is input to R1IN (Pins 176 to 183) and R2IN (Pins 184, 185 and 188 to 193), the Green signal to G1IN (Pins 194 to 196 and 199 to 203) and G2IN (Pins 204 to 208 and 211 to 213), and the Blue signal to B1IN (Pins 214 to 220 and 223) and B2IN (Pins 224 to 231).
(g) OSD signal input pins (R1OSD, R2OSD, G1OSD, G2OSD, B1OSD, B2OSD, YM1, YM2, YS1 and YS2)
These pins input OSD signals that have been demultiplexed to 1:2. The Red signal is input to R1OSD (Pins 232 and 233) and R2OSD (Pins 2 and 3), the Green signal to G1OSD (Pins 236 and 237) and G2OSD (Pins 4 and 5), and the Blue signal to B1OSD (Pins 238 and 239) and B2OSD (Pins 8 and 9). In addition, the YM signal is input to YM1 (Pin 240) and YM2 (Pin 10), and the YS signal to YS1 (Pin 1) and YS2 (Pin 11).
– 15 –
CXD3511Q
2. RGB Signal and OSD Signal Pipeline Delay
The RGB signal I/O pipeline delay is 54 dot clocks. In addition, the OSD, YM and YS signal pipeline delay is 34 dot clocks. Note that the phase relationship between each clock and the RGB signals is as shown in the figures below. This relationship is the same for the OSD, YM and YS signals.
(1) CLKPOL = L
HDIN input (negative polarity)
Dot clock
1/2 frequency-divided clock
R1, G1, B1OUT
R2, G2, B2OUT
(2) CLKPOL = H
HDIN input (negative polarity)
1/2 frequency-divided clock
R1, G1, B1IN
R2, G2, B2IN
CLKOUT
Dot clock
R1, G1, B1IN
R2, G2, B2IN
N – 2
N – 1 N + 1 N + 3 N + 5 N + 7 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19
N – 56 N – 54 N – 52 N – 50 N – 48 N – 46 N – 44 N – 42 N – 40 N – 38 N – 36
N – 55 N – 53 N – 51 N – 49 N – 47 N – 45 N – 43 N – 41 N – 39 N – 37 N – 35
N – 2 N N + 2 N + 4 N + 6 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18
N – 1 N + 1 N + 3 N + 5 N + 7 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19
N N + 2 N + 4 N + 6 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18
CLKOUT
R1, G1, B1OUT
R2, G2, B2OUT
N – 56 N – 54 N – 52 N – 50 N – 48 N – 46 N – 44 N – 42 N – 40 N – 38 N – 36
N – 55 N – 53 N – 51 N – 49 N – 47 N – 45 N – 43 N – 41 N – 39 N – 37 N – 35
– 16 –
3. Description of DSD Block Signal Processing Functions
The DSD block signal processing flow is shown below.
CXD3511Q
R, G, B IN
Sub bright Mute 1 OSD
Selectable delay line
Data path switch
Black frame
Mute 2 Limiter Post bright
Pre gain Pre bright User gain User bright Sub gain
YS, YM, R, G, B OSD
Pattern generator
Post gain
Gamma correction
Cycle offset
Color shading correction
R, G, B OUT
The various signal processing functions are described below. Note that the coefficients used for each arithmetic operation are set through the parallel I/F block. See the individual descriptions of each parallel I/F block item for a detailed description of the parallel I/F block.
(a) Data path switch block
This block can switch the path of the data input to ports 1 and 2. The setting is as follows.
Select signal: 1 = Path switched, 0 = Path not switched (Set independently for R, G and B)
Select signal (R, G, B_DAT_SW)
Input (port 1)
Input (port 2)
8
8
Selector
Selector
8
8
Output (port 1)
Output (port 2)
– 17 –
CXD3511Q
(b) Pre gain block
This block performs multiplication processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 8 bits Gain setting: 0 to 1.9921875 (= 255/128) times, variable in 256 steps (Set independently for R, G and B ports 1 and 2)
Multiplication is performed using the 8-bit input and an 8-bit coefficient, and the upper 10 bits c[15:6] of the operation results are output. Next, the c[6] value is checked and rounding is performed to 9 bits. The MSB of the rounded 9 bits is checked, clipping is performed, and the lower 8 bits are output.
Coefficient b[7:0]
Input a[7:0]
8
a × b
108
c[15:6]
Rounding
and
clipping
8
Output
(c) Pre bright block
This block performs addition and subtraction processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 5 bits with code, MSB = code bit Bright setting: –16 to +15 scales, variable with an accuracy of 1 bit (Set independently for R, G and B ports 1 and 2)
Multiplication is performed using the 8-bit input and a 5-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[4] = 0, and subtraction when b[4] = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed.
Input a[7:0]
Coefficient b[4:0]
8
5
Addition/subtraction
and
clipping
8
Output
(d) User gain block
This block performs multiplication processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 8 bits Gain setting: 0 to 7.96875 (= 255/32) times, variable in 256 steps (Settings shared by R, G and B)
Multiplication is performed using the 8-bit input and an 8-bit coefficient, and the upper 12 bits c[15:4] of the operation results are output. Next, the c[4] value is checked and rounding is performed to 11 bits. The MSB of the rounded 11 bits is checked, clipping is performed, and the lower 10 bits are output.
Coefficient b[7:0]
Input a[7:0]
8
a × b
128
c[15:4]
Rounding
and
clipping
10
Output
– 18 –
CXD3511Q
(e) User bright block
This block performs addition and subtraction processing as the user control bright adjustment. The settings are as follows.
Coefficient: 11 bits with code, MSB = code bit Bright setting: –1024 to +1023 scales, variable with an accuracy of 1 bit (Settings shared by R, G and B)
Multiplication is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed.
Input a[9:0]
Coefficient b[10:0]
10
11
Addition/subtraction
and
clipping
10
Output
(f) Sub gain block
This block performs multiplication processing as the white balance gain adjustment. The settings are as follows.
Coefficient: 8 bits Gain setting: 0 to 3.984375 (255/64) times, variable in 256 steps (Set independently for R, G and B)
Multiplication is performed using the 10-bit input and an 8-bit coefficient, and the upper 13 bits c[17:5] of the operation results are output. Next, the c[5] value is checked and rounding is performed to 12 bits. The upper 2 bits of the rounded 12 bits is checked, clipping is performed, and the lower 10 bits are output.
Coefficient b[7:0]
Input a[9:0]
8
a × b
1310
c[17:5]
Rounding
and
clipping
10
Output
(g) Sub bright block
This block performs addition and subtraction processing as the white balance bright adjustment. The settings are as follows.
Coefficient: 11 bits with code, MSB = code bit Bright setting: –1024 to +1023 scales, variable with an accuracy of 1 bit (Set independently for R, G and B)
Multiplication is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow or underflow, clipping is performed.
Input a[9:0]
Coefficient b[10:0]
10
11
Addition/subtraction
and
clipping
10
Output
– 19 –
CXD3511Q
(h) Black frame block
This block performs processing to fix the blanking period of the video signal to the desired level regardless of the front-end signal processing results. If the number of pixels calculated from the effective period of the video signal to be displayed is less than the number of pixels of the LCD panel on which the signal is to be displayed, the blanking period of the video signal is displayed in the excess pixels. At this time, the displayed blanking period can be fixed to the desired level regardless of the gain and bright adjustment or other picture quality adjustment results by processing with this block. The settings are as follows.
FRM_ON: 1 = Black frame processing ON, 0 = OFF FRM_DAT: Black frame level setting FRM_H1, FRM_H2: Set the black frame horizontal display range in 1-dot units FRM_V1, FRM_V2: Set the black frame vertical display range in 1-line units (All settings shared by R, G and B)
Here, the desired range of the video signal is replaced with 10-bit data (FRM_DAT) by switching the video signal (port 1 and por t 2) and the coefficients using the pulse output from the pulse decoder.
Internal HD
Internal VD
Internal MCLK
Processing ON/OFF (FRM_ON)
Input (port 1)
Coefficient (FRM_DAT)
Input (port 2)
Pulse decoder
10 10
10
12 12 11 11
Selector
Selector
Horizontal display range (FRM_H1) Horizontal display range (FRM_H2) Vertical display range (FRM_V1) Vertical display range (FRM_V2)
Output (port 1)
10
Output (port 2)
10
(i) Mute 1 block
This block performs mute processing by replacing the video signal with data of the desired level. The settings are as follows.
MUTE1_ON: 1 = Mute processing ON, 0 = OFF (Setting shared by R, G and B) R, G, B_MUTE1: RGB mute data (Set independently for R, G and B)
Input
Coefficient
(R, G, B_MUTE1)
Select signal (MUTE1_ON)
10 10
Selector
– 20 –
10
Output
CXD3511Q
(j) Pattern generator block
This block generates and outputs the set fixed pattern independently of the input signal. This function is valid when PG_ON = 1. When PG_R (G, B)_ON is "0", the signal level goes to 000h respectively for R, G and B. The raster display pattern is displayed in the effective area, and all other display patterns are displayed in the window area. Here, the effective area is set by PG_HST, PG_HSTP, PG_VST and PG_VSTP, and the window area is set by PG_HWST, PG_HWSTP, PG_VWST and PG_VWSTP. The display pattern signal level is set independently for R, G and B by PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0]. Within the effective area, the pattern and non-pattern signal levels can be switched by PG_R (G, B)_SEL. At this time, the signal level outside the effective area goes to 000h. During horizontal ramp, horizontal stair, vertical ramp and vertical stair display, the PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] settings are invalid.
The display patterns and signal levels are as follows.
(1) Raster display
When PG_PAT[2:0] = 0h, a raster is displayed.
PG_SIG2R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
0
0h
x x
1
0h
PG_SIG1R (G, B)
– 21 –
PG_STRP_SW
PG_STAIR_SW
x x
x: Don't care
(2) Window display
When PG_PAT[2:0] = 1h, a window is displayed.
CXD3511Q
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
0
1h
x x
1
1h
x x
– 22 –
x: Don't care
CXD3511Q
(3) Vertical stripe display
When PG_PAT[2:0] = 2h and PG_STRP_SW = 0, vertical stripes are displayed. The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
0
2h
0 x
1
2h
0 x
PG_SIG2R (G, B)
x: Don't care
– 23 –
CXD3511Q
(4) Diagonal stripes
When PG_PAT[2:0] = 2h and PG_STRP_SW = 1, diagonal stripes are displayed. The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
0
2h
1 x
1
2h
1 x
PG_SIG2R (G, B)
x: Don't care
– 24 –
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