The CXD3511Q incorporates digital signal
processor type RGB driver, color shading correction,
selectable delay line and timing generator functions
onto a single IC. Operation is possible with a system
clock up to 200 [MHz] (max.). This IC can process
video signals in bands up to UXGA standard, and
can output the timing signals for driving various Sony
LCD panels such as SXGA and XGA.
CXD3511Q
240 pin QFP (Plastic)
Features
• Various picture quality adjustment functions such
as user adjustment, white balance adjustment and
gamma correction
• OSD MIX, black frame processing, mute and
limiter functions
• LCD panel color shading correction function
• Selectable delay line
• Drives various Sony data projector LCD panels
such as SXGA and XGA
• Controls the CXA3512R and CXA3562R sample-
and-hold drivers
• Line inversion and field inversion signal generation
• Supports AC drive of LCD panels during no signal
Applications
LCD projectors and other video equipment
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (VSS = 0V)
• Supply voltageVDD1VSS – 0.5 to +3.0V
VDD2VSS – 0.5 to +4.0V
• Input voltageVIVSS – 0.5 to VDD1 + 0.5 V
• Output voltageVOVSS – 0.5 to VDD1 + 0.5 V
• Storage temperature
Tstg –55 to +125°C
• Junction temperature
Tj125°C
Recommended Operating Conditions
• Supply voltageVDD12.3 to 2.7V
VDD23.0 to 3.6V
• Operating temperature
Topr –20 to +75°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Item
PCTL setup time with respect to rise of PCLK
PCTL hold time with respect to rise of PCLK
PDAT[9:0] setup time with respect to rise of PCLK
PDAT[9:0] hold time with respect to rise of PCLK
PCLK pulse width
5
∗
T: Master clock (CLKP, CLKN, CLKC) period [ns]
Timing Definition
tcs
50%PCTL
twtw
PCLK
PDAT[9:0]
50%50%
tdstdh
50%50%
Symbol
tcs
tch
tds
tdh
tw
tch
8T
50%
Min.
∗
8T
4T
4T
4T
Typ.
5
—
—
—
—
—
DD2
V
V
SS
V
DD2
V
SS
V
DD2
V
SS
Max.
—
—
—
—
—
Power-on and Initialization of Internal Circuit
As for this IC, two systems of supply voltage should be turned on simultaneously. The initialization of the
internal circuit should be also performed by maintaining the system clear pin at low during the specified time
after setting the supply voltage in the range of recommended operating conditions and stabilizing as shown in
the figure below. Keep in mind that the internal circuit may not be initialized correctly if system clear
cancellation is performed before the supply voltage is set in the range of the recommended operating
conditions.
V
DD1
, V
DD2
V
DD1
, V
DD2
XCLR1, XCLR2,
XCLR3
TR
TR > 200ns
V
SS
V
DD2
V
SS
– 13 –
CXD3511Q
Description of Operation
1. Description of Input Pins
(a) System clear pins (XCLR1, XCLR2 and XCLR3)
All internal circuits are initialized by setting XCLR1 (Pin 27) low. In addition, the internal PLL is initialized by
setting XCLR2 (Pin 28) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 29) low.
Initialization should be performed when power is turned on. There are no particular restrictions on the
initialization order.
(b) Sync signal input pins (HDIN and VDIN)
Horizontal and vertical separate sync signals are input to HDIN (Pin 31) and VDIN (Pin 32), respectively. The
CXD3511Q supports only non-inter lace sync signals with a dot clock of 200MHz or less.
(c) Master clock input pins (CLKP/CLKN and CLKC)
Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The
master clock input pins have two systems consisting of CLKP/CLKN (Pins 38 and 39) for small-amplitude
differential input (center level: 2.0V, amplitude: ±0.4V), and CLKC (Pin 35) for CMOS level input. In addition, be
sure to make the number of dot clocks in 1H as even number.
Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate
properly.
(d) Clock selection pins (CLKSEL1 and CLKSEL2)
The master clock input pins can input either the system dot clock or the 1/2 frequency-divided clock. The
internal clock path is selected according to CLKSEL1 (Pin 41) and CLKSEL2 (Pin 44).
Setting
Symbol
CLKSEL1
CLKSEL2
Input clock selection
Clock input pin selection
Function
L
CLKP/CLKN input
Dot clock input
H
CLKC input
1/2 frequency-divided clock input
(e) PLL setting pin (PLLDIV)
PLLDIV (Pin 45) sets the divider setting of the internal phase compensation PLL circuit. Set PLLDIV low when
the internal clock frequency is 55 to 100MHz, or high when 27.5 to 55MHz. In addition, note that the frequency
of the clock input to the CXD3511Q must be within the phase compensation PLL operating range, even during
free running.
– 14 –
CXD3511Q
(f) RGB signal input pins (R1IN, R2IN, G1IN, G2IN, B1IN and B2IN)
These pins input RGB signals that have been demultiplexed to 1:2. The Red signal is input to R1IN (Pins 176
to 183) and R2IN (Pins 184, 185 and 188 to 193), the Green signal to G1IN (Pins 194 to 196 and 199 to 203)
and G2IN (Pins 204 to 208 and 211 to 213), and the Blue signal to B1IN (Pins 214 to 220 and 223) and B2IN
(Pins 224 to 231).
(g) OSD signal input pins (R1OSD, R2OSD, G1OSD, G2OSD, B1OSD, B2OSD, YM1, YM2, YS1 and YS2)
These pins input OSD signals that have been demultiplexed to 1:2. The Red signal is input to R1OSD (Pins
232 and 233) and R2OSD (Pins 2 and 3), the Green signal to G1OSD (Pins 236 and 237) and G2OSD (Pins
4 and 5), and the Blue signal to B1OSD (Pins 238 and 239) and B2OSD (Pins 8 and 9). In addition, the YM
signal is input to YM1 (Pin 240) and YM2 (Pin 10), and the YS signal to YS1 (Pin 1) and YS2 (Pin 11).
– 15 –
CXD3511Q
2. RGB Signal and OSD Signal Pipeline Delay
The RGB signal I/O pipeline delay is 54 dot clocks. In addition, the OSD, YM and YS signal pipeline delay is 34
dot clocks. Note that the phase relationship between each clock and the RGB signals is as shown in the
figures below. This relationship is the same for the OSD, YM and YS signals.
(1) CLKPOL = L
HDIN input (negative polarity)
Dot clock
1/2 frequency-divided clock
R1, G1, B1OUT
R2, G2, B2OUT
(2) CLKPOL = H
HDIN input (negative polarity)
1/2 frequency-divided clock
R1, G1, B1IN
R2, G2, B2IN
CLKOUT
Dot clock
R1, G1, B1IN
R2, G2, B2IN
N – 2
N – 1 N + 1 N + 3 N + 5 N + 7 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19
N – 56 N – 54 N – 52 N – 50 N – 48 N – 46 N – 44 N – 42 N – 40 N – 38 N – 36
N – 55 N – 53 N – 51 N – 49 N – 47 N – 45 N – 43 N – 41 N – 39 N – 37 N – 35
N – 2NN + 2 N + 4 N + 6 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18
N – 1 N + 1 N + 3 N + 5 N + 7 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19
NN + 2 N + 4 N + 6 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18
CLKOUT
R1, G1, B1OUT
R2, G2, B2OUT
N – 56 N – 54 N – 52 N – 50 N – 48 N – 46 N – 44 N – 42 N – 40 N – 38 N – 36
N – 55 N – 53 N – 51 N – 49 N – 47 N – 45 N – 43 N – 41 N – 39 N – 37 N – 35
– 16 –
3. Description of DSD Block Signal Processing Functions
The DSD block signal processing flow is shown below.
CXD3511Q
R, G, B IN
Sub brightMute 1OSD
Selectable
delay line
Data path
switch
Black
frame
Mute 2LimiterPost bright
Pre gainPre brightUser gainUser brightSub gain
YS, YM, R, G, B OSD
Pattern
generator
Post gain
Gamma
correction
Cycle
offset
Color shading
correction
R, G, B OUT
The various signal processing functions are described below. Note that the coefficients used for each
arithmetic operation are set through the parallel I/F block. See the individual descriptions of each parallel I/F
block item for a detailed description of the parallel I/F block.
(a) Data path switch block
This block can switch the path of the data input to ports 1 and 2. The setting is as follows.
Select signal: 1 = Path switched, 0 = Path not switched (Set independently for R, G and B)
Select signal (R, G, B_DAT_SW)
Input (port 1)
Input (port 2)
8
8
Selector
Selector
8
8
Output (port 1)
Output (port 2)
– 17 –
CXD3511Q
(b) Pre gain block
This block performs multiplication processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 8 bits
Gain setting: 0 to 1.9921875 (= 255/128) times, variable in 256 steps
(Set independently for R, G and B ports 1 and 2)
Multiplication is performed using the 8-bit input and an 8-bit coefficient, and the upper 10 bits c[15:6] of the
operation results are output. Next, the c[6] value is checked and rounding is performed to 9 bits. The MSB of
the rounded 9 bits is checked, clipping is performed, and the lower 8 bits are output.
Coefficient
b[7:0]
Input
a[7:0]
8
a × b
108
c[15:6]
Rounding
and
clipping
8
Output
(c) Pre bright block
This block performs addition and subtraction processing independently for ports 1 and 2. The settings are as
follows.
Coefficient: 5 bits with code, MSB = code bit
Bright setting: –16 to +15 scales, variable with an accuracy of 1 bit
(Set independently for R, G and B ports 1 and 2)
Multiplication is performed using the 8-bit input and a 5-bit coefficient with code. The coefficient MSB is the
code bit. Addition is performed when b[4] = 0, and subtraction when b[4] = 1. However, when performing
subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow
or underflow, clipping is performed.
Input
a[7:0]
Coefficient
b[4:0]
8
5
Addition/subtraction
and
clipping
8
Output
(d) User gain block
This block performs multiplication processing independently for ports 1 and 2. The settings are as follows.
Coefficient: 8 bits
Gain setting: 0 to 7.96875 (= 255/32) times, variable in 256 steps
(Settings shared by R, G and B)
Multiplication is performed using the 8-bit input and an 8-bit coefficient, and the upper 12 bits c[15:4] of the
operation results are output. Next, the c[4] value is checked and rounding is performed to 11 bits. The MSB of
the rounded 11 bits is checked, clipping is performed, and the lower 10 bits are output.
Coefficient
b[7:0]
Input
a[7:0]
8
a × b
128
c[15:4]
Rounding
and
clipping
10
Output
– 18 –
CXD3511Q
(e) User bright block
This block performs addition and subtraction processing as the user control bright adjustment. The settings are
as follows.
Coefficient: 11 bits with code, MSB = code bit
Bright setting: –1024 to +1023 scales, variable with an accuracy of 1 bit
(Settings shared by R, G and B)
Multiplication is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the
code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing
subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow
or underflow, clipping is performed.
Input
a[9:0]
Coefficient
b[10:0]
10
11
Addition/subtraction
and
clipping
10
Output
(f) Sub gain block
This block performs multiplication processing as the white balance gain adjustment. The settings are as follows.
Coefficient: 8 bits
Gain setting: 0 to 3.984375 (255/64) times, variable in 256 steps
(Set independently for R, G and B)
Multiplication is performed using the 10-bit input and an 8-bit coefficient, and the upper 13 bits c[17:5] of the
operation results are output. Next, the c[5] value is checked and rounding is performed to 12 bits. The upper 2
bits of the rounded 12 bits is checked, clipping is performed, and the lower 10 bits are output.
Coefficient
b[7:0]
Input
a[9:0]
8
a × b
1310
c[17:5]
Rounding
and
clipping
10
Output
(g) Sub bright block
This block performs addition and subtraction processing as the white balance bright adjustment. The settings
are as follows.
Coefficient: 11 bits with code, MSB = code bit
Bright setting: –1024 to +1023 scales, variable with an accuracy of 1 bit
(Set independently for R, G and B)
Multiplication is performed using the 10-bit input and an 11-bit coefficient with code. The coefficient MSB is the
code bit. Addition is performed when b[10] = 0, and subtraction when b[10] = 1. However, when performing
subtraction, set the two's complement in the lower bits of the coefficient. When the operation results overflow
or underflow, clipping is performed.
Input
a[9:0]
Coefficient
b[10:0]
10
11
Addition/subtraction
and
clipping
10
Output
– 19 –
CXD3511Q
(h) Black frame block
This block performs processing to fix the blanking period of the video signal to the desired level regardless of
the front-end signal processing results.
If the number of pixels calculated from the effective period of the video signal to be displayed is less than the
number of pixels of the LCD panel on which the signal is to be displayed, the blanking period of the video
signal is displayed in the excess pixels. At this time, the displayed blanking period can be fixed to the desired
level regardless of the gain and bright adjustment or other picture quality adjustment results by processing with
this block. The settings are as follows.
FRM_ON: 1 = Black frame processing ON, 0 = OFF
FRM_DAT: Black frame level setting
FRM_H1, FRM_H2: Set the black frame horizontal display range in 1-dot units
FRM_V1, FRM_V2: Set the black frame vertical display range in 1-line units
(All settings shared by R, G and B)
Here, the desired range of the video signal is replaced with 10-bit data (FRM_DAT) by switching the video
signal (port 1 and por t 2) and the coefficients using the pulse output from the pulse decoder.
Internal HD
Internal VD
Internal MCLK
Processing ON/OFF
(FRM_ON)
Input (port 1)
Coefficient (FRM_DAT)
Input (port 2)
Pulse decoder
10
10
10
12
12
11
11
Selector
Selector
Horizontal display range (FRM_H1)
Horizontal display range (FRM_H2)
Vertical display range (FRM_V1)
Vertical display range (FRM_V2)
Output (port 1)
10
Output (port 2)
10
(i) Mute 1 block
This block performs mute processing by replacing the video signal with data of the desired level. The settings
are as follows.
MUTE1_ON: 1 = Mute processing ON, 0 = OFF (Setting shared by R, G and B)
R, G, B_MUTE1: RGB mute data (Set independently for R, G and B)
Input
Coefficient
(R, G, B_MUTE1)
Select signal (MUTE1_ON)
10
10
Selector
– 20 –
10
Output
CXD3511Q
(j) Pattern generator block
This block generates and outputs the set fixed pattern independently of the input signal. This function is valid
when PG_ON = 1. When PG_R (G, B)_ON is "0", the signal level goes to 000h respectively for R, G and B.
The raster display pattern is displayed in the effective area, and all other display patterns are displayed in the
window area. Here, the effective area is set by PG_HST, PG_HSTP, PG_VST and PG_VSTP, and the window
area is set by PG_HWST, PG_HWSTP, PG_VWST and PG_VWSTP.
The display pattern signal level is set independently for R, G and B by PG_SIG1R (G, B)[9:0] and PG_SIG2R
(G, B)[9:0]. Within the effective area, the pattern and non-pattern signal levels can be switched by PG_R (G,
B)_SEL. At this time, the signal level outside the effective area goes to 000h. During horizontal ramp, horizontal
stair, vertical ramp and vertical stair display, the PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] settings are
invalid.
The display patterns and signal levels are as follows.
(1) Raster display
When PG_PAT[2:0] = 0h, a raster is displayed.
PG_SIG2R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
0
0h
x
x
1
0h
PG_SIG1R (G, B)
– 21 –
PG_STRP_SW
PG_STAIR_SW
x
x
x: Don't care
(2) Window display
When PG_PAT[2:0] = 1h, a window is displayed.
CXD3511Q
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_SIG2R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
0
1h
x
x
1
1h
x
x
– 22 –
x: Don't care
CXD3511Q
(3) Vertical stripe display
When PG_PAT[2:0] = 2h and PG_STRP_SW = 0, vertical stripes are displayed.
The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
0
2h
0
x
1
2h
0
x
PG_SIG2R (G, B)
x: Don't care
– 23 –
CXD3511Q
(4) Diagonal stripes
When PG_PAT[2:0] = 2h and PG_STRP_SW = 1, diagonal stripes are displayed.
The stripe period is set by PG_STEP in 2-dot units. The stripe width is set by PG_WIDTH in 1-dot units.
PG_SIG2R (G, B)
PG_SIG1R (G, B)
PG_SIG1R (G, B)
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
PG_R (G, B)_SEL
PG_PAT[2:0]
PG_STRP_SW
PG_STAIR_SW
0
2h
1
x
1
2h
1
x
PG_SIG2R (G, B)
x: Don't care
– 24 –
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